-1480 (70)-
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`Research Notes 1
`
`Novel SOI Technology Using Preferential Polishing
`
`Tsuneo Hamaguchi* and Nobuhiro Endo**
`
`10.2, 2.5
`
`* Research and Development Planning and Technical Service Division, NEC Corporation, 1-1, Miyazaki 4-chome,
`Miyamae-ku, Kawasaki 213
` ** Microelectronics Laboratories, NEC Corporation, 1-1, Miyazaki 4-chome, Miyamae-ku, Kawasaki 213
`
`(Accepted July 2, 1987)
`
`The paper describes a device transfer technique using preferential polishing having considerably different
`polishing rates between silicon and silicon dioxide to form an SOI structure by extracting only a device layer from
`a wafer by using the field oxide layer within the device layer as a polishing stopper, and bonding the device to an
`insulating substrate. As a result of applying this technique to bipolar and MOS devices, a notable improvement in
`the voltage resistance was achieved without degrading transistor characteristics.
`
`1. Introduction
`
`SOI (silicon-on-insulator) technology for forming LSI’s on insulators is important for achieving high
`speed LSI’s, as well as increasing their breakdown voltage and radiation resistance.
`Conventional exemplary SOI forming methods include heteroepitaxy, such as SOS (silicon on sapphire)1),
`for example, recrystallization using a laser2) and an electron beam3), and single-crystal separation, such as SIMOX
`(separation by implanted oxygen)4). However, these methods have not been able to produce crystals of high
`enough quality to form VLSI’s.
`This gave rise to the development of a device transfer technique where only the device layer from the
`silicon wafer which has completed a device formation process is extracted and transferred onto an insulator. This
`technique, although depends on how the device layer and insulator are bonded, can form a SOI structure at low
`temperatures. A device transfer technique was first reported by Nielen, et al.5) They used etching as a method to
`remove the substrate while leaving only the device layer behind. Utilizing the dependency of etching rates on
`impurity concentrations, they formed the device by forming an epitaxial layer on a substrate having a high
`impurity concentration. However, this method requires epitaxial growth, as well as a high impurity concentration
`substrate, thereby restricting the type of devices that can be formed.
`Meanwhile, chemical mechanical polishing has been widely used in silicon wafer processing, and is
`characterized by the planarization ability without imparting strain. Moreover, using an amine for the chemical
`solution, the processing rate for silicon becomes markedly higher than that of silicon dioxide. This is referred to
`as "preferential polishing."
`In preferential polishing, field oxide layers, which are provided in the device layers for separating
`individual transistors, can serve as processing stoppers, enabling the extraction of only the device layers6).
`This paper discusses an SOI structure which was formed by separating only a device layer by using
`preferential polishing.
`
`2. Preferential Polishing
`
`Polishing is a method for processing a wafer by pressing the wafer against the surface of a polishing cloth
`provided on a rotary disk, which is operated while supplying a processing solution.
`Preferential polishing provides selectivity in processing rates, and the materials having the selectivity vary
`depending on the chemical solutions used. Generally speaking, ethylenediamine pyrocatechol is known as an
`2- are formed on the
`etchant for silicon. The silicon etching mechanism using this etchant7) is such that Si(OH)6
`silicon surface by the ionization and redox reactions of amine, which are then chelated with pyrocatechol and
`dissolved in the solution.
`2- with pyrocatechol is replaced with a mechanical action,
`In preferential polishing, the removal of Si(OH)6
`i.e., "wiping" with a polishing cloth. The polishing is performed in two stages: a chemical reaction process by
`amine, water, and silicon, and a mechanical removal process of "wiping" with the polishing cloth.
`FIG. 1 shows the results of the experiments performed to confirm the two stages of preferential polishing.
`
`SONY 1004
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`001
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`Novel SOl Teclmology Using Preferential Polishing
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`-1481 (71)-
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`Silicon is slightly etched by amine. Silicon is not polished with water alone. Polishing becomes possible
`only when amine is used in the chemical solution, and the combined effect of the chemical reaction of amine and
`the mechanical action of the polishing cloth allows the polishing to progress. Silicon dioxide, on the other hand,
`does not react with amine, and thus is not polished at all.
`I01r----------.
`IO~ 0
`
`Processing
`Rate (~tm/h)
`
`Q
`
`10-a
`
`J0-4
`
`0
`
`c
`A
`B
`Processing Conditions
`
`FIG. 1
`Preferential polishing mechanism. Polishing conditions are
`A: chemical etching with an aqueous amine solution, B:
`polishing with water at a pressm·e of 1.9 x 104 Pa, and C:
`polishing with an aqueous amine solution at a pressme of
`1.9 x 104 Pa.
`Si: n-type ( 100), 8 to 10 Q ·cm. Si02: thetmal oxide film
`grown at 950°C.
`
`FIG. 1 shows the case of ann-type (1 00) orientation silicon wafer. The same tendency is shown in cases
`of a p-type and other orientations (111) and (11 0). The chemical etching rate for the (111) orientation is about
`1/10 of those of the (100) and (ll 0) orientations, but no difference in polishing rate based on orientations was
`observed. Thus, the etching rate using amine is presmnably limited by the separation of the reaction products
`from the silicon surface.
`FIG. 2 shows a cross-sectional view of a wafer having a field oxide film being polished. h1 the region
`where silicon dioxide is not exposed at the surface (on the right hand side of the figm·e), Si(OH)/ fotmed at the
`smface is wiped off by a polyester fiber polishing cloth, and polishing progresses. ill the region where silicon
`dioxide is exposed (on the left hand side of the figure), silicon dioxide prevents the wiping ofSi(OH)l because
`the polishing cloth is flat-shaped. As a result, the polishing does not progress, and thus the silicon (device layer)
`stmounded by the field oxide can be preserved.
`
`Supporting substrate
`
`FIG. 2
`Polishing of a substrate having a field oxide
`film. The oxide film is not exposed on the
`right side of the figme, and Si(OH)l is
`removed by a polishing cloth. The oxide fihn
`is exposed on the left side of the figure, and
`Si(OH)i· is not removed.
`
`FIG. 3 is a cross-sectional scamling electron micrograph of the substrate with the oxide film exposed after
`forming 2 J..llll wide, 3 f.lm deep trenches in a device layer, burying the polysilicon by covering the surface with a
`200 nm oxide film, and polishing from the opposite side of the device surface (back smface). Polishing stopped
`at the oxide film having a thickness of only 200 nm, and the polished surface was flat. This indicates that the
`polishing progressed on the flat surface, and at the instant silicon dioxide was exposed, polishing of
`silicon no longer progressed. Thus, preferential polishing enables processing using the field oxide film
`as a stopper, removing the substrate while leaving only the device layer behind.
`
`002
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`-1482 (72)-
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`Applied Physics Vol. 56, No. 11 (1987)
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`Polysilicon
`
`Silicon dioxide fihn
`
`Polishing stuface
`
`FIG. 3
`Scanning electron micrograph of a cross section of a
`substrate with the field oxide fihu exposed. The field
`oxide film is covered with silicon dioxide of 200 tllll in
`thickness on the surface, and includes trenches filled
`with polysilicon.
`
`Supporting substtate Adhesive
`
`i~o.~.,.
`
`FIG. 4
`substrate
`Schematic cross-sectional view of a
`illustrating the size and the polished shape of a
`transistor (silicon) region.
`
`=
`
`Polishing
`
`SiOt
`
`Since the polishing cloth is composed of fibers, the greater the spaces between silicon dioxide which is a
`stopper, i.e., the greater the areas of open silicon regions, the easier for the polishing cloth fibers to enter, resulting
`in excessive polishing and creating recesses as shown in FIG. 4. This indicates that the smaller the areas of open
`silicon regions, i.e., the higher the integration density of a. device, the more effective preferential polishing
`becomes.
`
`3. Formation of SOl by Device Transfer
`FIG. 5 shows the device transfer process. FIG. 5(a) illustrates a silicon wafer on which a device has
`ah·ea.dy been formed, but before processing, and (b) illustrates the state where the device surface is bonded to a
`supporting substrate A. An epoxy- or polyi.nlide-based adhesive is used. As illustrated in FIG. 5 (c), most of the
`thickness (about 430 f.J.Ill) of the wafer on which the device has been formed is removed by lapping (rough
`polishing). Alumina was used as abrasive grains. The remainder was removed by preferential polishing to leave
`only the device layer behind. Since lapping utilizes the action of abrasive grains, strain remains on the processed
`smface although the processing rate is high. Accordingly, at least 40 J..Lm is removed by polishing in order to
`impart no strain to the device layer. Since the relationship between the lapping ammmt and time is linear, the
`processing amom1t is easily controlled by time.
`
`Device layer
`Silicon wafer
`
`Supporting substrate A
`Adhesive
`
`Adhesive
`
`Supporting substrate B
`(Quartz glass)
`
`Device layer
`Supporting substrate B
`(Quartz glass)
`
`003
`
`FIG. 5
`(a) silicon wafer on
`Device transfer process:
`which a device layer is formed, (b) bonding of
`the silicon wafer and supporting substrate A,
`(c) removal of the silicon wafer (lapping +
`preferential polishing),
`(d) bonding with
`suppmting substrate B (quartz glass wafer), (e)
`removal of the suppmting substrate A, and (f)
`removal of an adhesive, thereupon the device
`layer is transferred to suppmting substrate B.
`
`( f )
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`Novel SOI Technology Using Preferential Polishing
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` -1483 (73)-
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`As shown in FIG. 5 (d), the device layer left behind by preferential polishing is bonded to a supporting
`substrate B (quartz glass). As shown in FIG. 5 (e), the supporting substrate A is removed by lapping and
`preferential polishing in the same manner as that for exposing the device surface. In this case, the adhesive serves
`as a polishing stopper. Finally, as illustrated in FIG. 5 (f), the adhesive is removed by oxygen plasma ashing to
`complete the process of transferring only the device active layer onto another supporting substrate across the
`entire wafer.
`
`FIG. 6
`A 100-mm-diameter wafer; (a) before transfer,
`and (b) after transfer. On the wafer, an array of
`10,000 bipolar transistor chips is formed within
`the device layer of 1 m in thickness. After the
`transfer, letters can be seen through the device
`layer on the wafer.
`
`
`
`
`
`Figure 6 shows the state where an array of 10,000 parallel connected bipolar transistors formed on a wafer
`of 100 mm in diameter was transferred onto a quartz glass wafer. The device layer is 1 m in thickness, and the
`characters can be seen through the wafer after the transfer. As shown in FIG. 7, the transistor structure is formed
`within a 1-m-thick epitaxial layer, the depths of the base and emitter being 0.2 m and 0.08 m, respectively,
`and the LOCOS (local Oxidation of Silicon) isolation layer serves as a preferential polishing stopper.
`
`Base emitter collector
`
`
`
`Polishing surface
`
`
`
`FIG. 7
`Structure of a bipolar transistor. The transistor
`is formed in a 1-m-thick epitaxial layer and
`has a base depth of 0.2 m and an emitter depth
`of 0.08 m.
`
`
`
`FIG. 8 shows the characteristics of the transferred transistor array: (a) the collector-base breakdown
`voltage, and (b) the collector current and collector voltage. There were no changes observed in these
`characteristics before or after the transfer, meaning that preferential polishing did not cause any damage to the
`transistors. Furthermore, the breakdown voltage between the transistors is considerably improved from 12 V
`before the transfer to 100 V or higher. This is because the breakdown voltage before the transfer depends on the
`n+-p+ junction between the buried collector and channel stopper regions, as opposed to the pressure resistance of
`the adhesive after the transfer.
`
`FIG. 8
`the bipolar
`Characteristics of
`transistor array after the transfer:
`(a)
`collector-base
`breakdown
`voltage, and (b)
`the collector
`current vs. the collector voltage.
`
`
`
`FIG. 9 is a scanning electron micrograph of a cross section of the substrate after transferring a 0.4-m-
`thick MOSFET device layer onto a quartz glass. As is clear from the figure, the use of preferential polishing is
`also applicable to thinning of a submicron-thickness device.
`
`The foregoing transfer process requires two polishing steps. It is possible to create a hole from the rear
`surface of the device layer exposed by polishing through the silicon dioxide layer to the aluminum pad, as shown
`in FIG. 5(c), to expose the aluminum electrode at the rear surface for connection (e.g., wire bonding)8) to perform
`only one polishing step. This method not only shortens the device transfer process, but also provides superior
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`-1484 (74)-
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`Applied Physics Vol. 56, No. 11 (1987)
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`characteristics, such as forming wiring on both surfaces of the device layer, as well as controlling the substrate
`potential, which was difficult to do using conventional SOI techniques.
`
`Polishing
`surface
`
`Silicon layer 0.4 μm
`
`Adhesive layer
`
`FIG. 9
`Scanning electron micrograph of a
`cross section of a substrate after the
`transfer of MOS transistors.
`
`
`
`
`4. Conclusions
`
`Preferential polishing progresses in two stages of chemical reaction and mechanical removal, and is
`capable of polishing silicon at a rate that is at least 104 times that of silicon dioxide. This technology enables the
`formation of an SOI device by device transfer where the wafer is thinned by utilizing the oxide film formed
`within the device layer as a stopper, and transferring only the device active layer onto an insulating substrate.
`
`Various applications are conceivable for the device transfer technology because of its ability to form only
`a device layer on a variety of substrates. For example, transferring a device layer onto a high thermal conductive
`substrate would resolve thermal problems. Bonding or stacking different types of devices together, such as
`gallium arsenide devices and silicon devices, for example, or stacking the silicon devices together, would enable
`the formation of a hybrid, multifunctional, high integration density three-dimensional LSI, and so on – dreams
`keep growing. In order to realize these, however, technological development in interlayer connection, etc., is
`necessary.
`
`Finally, we would like to express our deepest appreciation to General Manager Itsuki Yamada and Section
`Manager Toshio Okubo of the Prototype Department, and General Manager Koichi Yoshimi of the VLSI Research
`Department for providing this research opportunity. We would also like to thank Mr. Masao Tajima for his
`cooperation in the scanning electron microscope observation.
`
`References
`
`
`8) Nobuhiro Endo, Tsuneo Hamaguchi, and Naonori
`Kasai: 47th Applied Physics Society Conference
`Draft Papers (1986) p. 495.
`
`005
`
`

`
`ttl JAPAN INTERFACE
`
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`CERTIFICATION OF TRANSlATION
`
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`3. I certify that the English translation of the document identified below is a true
`and correct translation, to the best of my knowledge and ability, of the original
`Japanese document:
`
`• Article titled "Novel SOl Technology Using Preferential Polishing" authored by
`Tsuneo Hamaguchi, et al.
`
`I hereby certify under penalty of perjury under the laws of the United States of America
`that the foregoing is true and oorrect.
`
`Executed this 16th day of March, 2015.
`
`By: -~-· _Q -----=::......_1
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