-
`
`'
`
`G Muted States Patent [19]
`Riseman
`
`[11]
`[45]
`
`4,169,000
`Sep. 25, 1979
`
`[54] METHOD OF FORMING AN INTEGRATED
`CIRCUIT STRUCTURE WITH
`FULLYJENCLOSED AIR ISOLATION
`
`3,332,137
`3,341,743
`3,343,255
`
`7/1967 Kenney ............................ .. 29/589 X
`9/1967 Ramsey ........................ .. 357/49 X
`9/1967 Donovan .
`.... .. 357/49 X
`
`3,381,369
`
`5/1968
`
`Stoller . . . . . . . . . . . . . .
`
`. . . . . . . . .. 29/580
`
`[75] Inventor: Jacob Riseman, Poughkeepsie, NY.
`
`[73] Assignee= lc'ltematifmaliusineis lgll?lfhines
`
`.
`
`.
`
`orpora lOIl, rmon ,
`'
`
`_
`[21] Appl' No" 904’713
`[22] Filed:
`May 10, 1978
`
`[62]
`
`Related us. Application Data
`Division of S61‘. No. 719,888, Sep. 2, 1976, Pat, No.
`4,106,050.
`[51] Int Cl 2
`[52] Us"
`'
`'
`
`""""""""" "
`
`H01L 21/306_ HOIL 21/76
`148/1§7_ 29/576 W,
`56/6415, 56/648:
`56/659. 156;“; 357/’49. 357/5’O. 357/55’
`[ss] Field of Search, ............ ..’. ....... .. 1118/15, 175, 187;
`156/645, 648, 657, 659, 662; 29/576 W, 580,
`589; 357/47, 49, 50, 55
`References Cited
`U.S. PATENT DOCUMENTS
`
`3,489,961
`3,689,992
`
`3,787,710
`
`1/1970 Frescura et a1. . . . . .
`9 1972 S h
`t
`l. . . . . . .
`
`. . , . .. 357/49 X
`. . . . .. 29 580 X
`
`1/1974 cil’llllltiileglel?lz'lil ................... .. 357/49 x
`
`Primary Examiner—-R. Dean
`Assistant Examiner—W. G. Saba
`Attorney, Agent, or Firm—Theodore E. Galanthay
`
`ABSTRACT
`[57]
`A method for forming a fully-enclosed air isolation
`structure which comprises etching a pattern of cavities
`extending from one surface of a silicon substrate into the
`substrate to laterally surround and electrically isolate
`said plurality of substrate pockets, and then forming a
`?rst layer of silicon dioxide on said ?rst substrate sur
`face- Next, a Planat Second layer comprising Silicon
`dioxide is formed over a second silicon substrate, after
`which this planar layer is fused to said silicon dioxide
`layer to thereby fully enclose said cavities. Then, the
`second silicon substrate is removed.
`
`[56]
`
`3,300,832
`
`1/1967 Cave ................................ .. 357/49 X
`
`7 Claims, 8 Drawing Figures
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`Raytheon2051-0001
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`Sony Corp. v. Raytheon Co.
`IPR2015-01201
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`US. Patent Sep.25,1979
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`>Sheet1of2
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`US. Patent Sep. 25, 1979
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`Sheet 2 of2
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`1
`
`METHOD OF FORMING AN INTEGRATED
`CIRCUIT STRUCTURE WITH FULLY-ENCLOSED
`AIR ISOLATION
`
`This is a division of application Ser. No. 719,888 ?led
`9/2/76, now US. Pat. No. 4,106,050.
`
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`4, 169,000
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`silicon need not be deposited in which case, the chan
`nels would provide air-isolation. Next, the other or
`planar surface of the semiconductor member may be
`either mechanically ground down or chemically etched
`until the bottom portions of the previously etched chan
`nels are reached. This leaves the structure wherein a
`plurality of pockets of semiconductor material sur
`rounded by a thin dielectric layer are either supported
`on a polycrystalline silicone substrate and separated
`from each other by the extensions of the polycrystalline
`substrate or in the absence of the polysilicon, a structure
`in which the pockets of semiconductor material are, in
`effect, “air-isolated” from each other. While such struc
`tures provide an essentially ?at and thus wirable planar
`surface of coplanar pockets of semiconductor material,
`such integrated circuit structures have limited utility
`with integrated circuits of high device densities. This is
`due to the fact that the etched channels which corre
`spond to the isolation regions must be formed from the
`back side of the integrated circuit substrate and etched
`until the level of the active planar surface of the sub
`strate is reached.
`It is recognized in the art that when etching from the
`back side of an integrated circuit member the etching
`must be made to greater depth than when etching di
`rectly from the planar front surface in order to insure
`uniform lateral isolation. It is also recognized that when
`etching through a member, the extent of lateral etching
`will be substantially the same as the depth of etching.
`Accordingly, when etching channels from the back side
`of the substrate, so much lateral “real estate” is con
`sumed on the wafer that such an approach has very
`limited practicality in high density integrated circuits.
`On the other hand, if the etching to form the channels
`in the above dielectric isolation or air-isolation structure
`is carried out from the active or front surface of the
`integrated circuit, only limited lateral etching is neces
`sary to reach practical isolation depths. However, the
`result is an essentially corrugated active surface rather
`than a planar one. Such a corrugated active surface is,
`of course, dif?cult to wire, i.e., form integrated circuit
`metallurgy interconnections by conventional photo
`lithographic integrated circuit fabrication techniques.
`Another approach which has been utilized for form
`ing lateral dielectric isolation in the art involves the
`formation of recessed silicon dioxide lateral isolation
`regions, usually in the epitaxial layer where the semi
`conductor devices are to be formed, through the expe
`dient of ?rst selectively etching a pattern of recesses in
`the layer of silicon, and then thermally oxidizing the
`silicon in the recesses with appropriate oxidation block
`ing masks, e.g., silicon nitride masks, to form recessed
`or inset regions of silicon dioxide which provide the
`lateral electrical isolation. Representative of the prior
`art teaching in this area are US Pat. No. 3,648,125 and
`an article entitled, “Locos Devices”, E. Kooi et a1,
`Philips Research Report 26, pp. 166-180 (1971).
`While this approach has provided both planarity at
`the active device integrated circuit surface as well as
`good lateral dielectric isolation, it has encountered
`some problems. Originally, the art applied the silicon
`nitride masks directly onto the silicon substrates. This
`gave rise to problems associated with high stresses cre
`ated on the underlying silicon substrate by the silicon
`nitride-silicon interface. Such stresses were found in
`many cases to produce dislocations in the silicon sub
`strate which appear to result in undesirable leakage
`current pipes and otherwise adversely affect the electri
`
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`
`BACKGROUND OF THE INVENTION
`The present invention relates to integrated circuit
`structures and more particularly to dielectric isolation
`in such integrated circuit structures, particularly by
`air-isolation.
`The form of most existing integrated circuits is the
`so-called monolithic form. Such a structure contains
`great numbers of active and passive devices in a block
`or monolith of semiconductor material. Electrical con
`nections between these active and passive devices are
`generally made on a surface of the semiconductor block
`of material. Until recently, junction isolation has been
`by far the most widely practiced manner of isolating
`devices or circuits in the integrated circuit from each
`other. For example, active P-type diffusions are custom
`arily used to isolate conventional PET and bipolar de
`vices from one another and from other devices such as
`the resistors and capacitors. Such junction isolation is
`also used in integrated circuits utilizing ?eld effect tran
`sistor devices. More detailed descriptions of junction
`isolation may be, found in U.S. Pat. Nos. 3,319,311;
`3,451,866; 3,508,209 and 3,539,876.
`Although junction isolation has provided excellent
`electrical isolation in integrated circuits which have
`functioned very effectively over the years, at the pres
`ent stage of the development of the integrated circuit
`art, there is an increasing demand in the ?eld of digital
`integrated circuits for faster switching circuits. It has
`long been recognized that the capacitive effect of the
`isolating P-N junctions has a slowing effect on the
`switching speed of the integrated circuits. Until re
`cently, the switching demands of the integrated circuits
`have been of a suf?ciently low frequency that the ca
`pacitive effect in junction isolation has presented no
`major problems. However, with the higher frequency
`switching demand which can be expected in the ?eld in
`the future, the capacitive effect produced by junction
`isolation may be an increasing problem. In addition,
`junction isolation requires relatively large spacing be
`tween devices, and, thus, relatively low device densities
`which is contrary to higher device densities required in
`large scale integration. Junction isolation also tends to
`give rise to parasitic transistor effects between the isola
`tion region and its two abutting regions. Consequently,
`in recent years there has been a revival of interest in
`integrated circuits having dielectric isolation instead of
`junction isolation. In such dielectrically isolated cir
`cuits, the semiconductor devices are isolated from each
`other by insulative dielectric materials or by air.
`Conventionally, such dielectric isolation in integrated
`circuits has been formed by etching channels in a semi
`conductor member corresponding to the isolation re
`gions from the back side of the member, i.e., the side
`opposite to the planar surface at which the devices and
`wiring of the integrated circuit are to be formed. This
`leaves an irregular or channeled surface over which a
`substrate back side, usually a composite of a thin dielec
`tric layer forming the interface with the semiconductor
`member covered by a thicker layer of polycrystalline
`silicon is deposited. Alternatively, the polycrystalline
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`cal characteristics of the interface. In order to minimize
`such interface stresses with silicon nitride layers, it has
`become the practice in the art to form a thin layer of
`silicon dioxide between the silicon substrate and the
`silicon nitride layer. During such thermal oxidation,
`there is a substantial additional lateral penetration of
`silicon oxide from the thermal oxidation beneath the
`silicon nitride. This lateral penetration is greatest at the
`mask-substrate interface to provide a laterally sloping
`structure known and recognized in the prior art as the
`undesirable “bird’s beak”.
`The publications, “Local Oxidation of Silicon; New
`Technological Aspects”, by J. A. Appels et al, Philips
`Research Report 26, pp. 157-165, June 1971, and “Se
`lective Oxidation of Silicon and its Device Applica
`tion”, E. Kooi et al, Semiconductor Silicon 1973, pub
`lished by the Electrochemical Society, Edited by H. R.
`Huff and R. R. Burgess, pp. 860-879, are representative
`of the recognition in the prior art of the “bird’s beak”
`problems associated with silicon dioxide-silicon nitride
`composite masks, particularly when used in the forma
`tion of recessed silicon dioxide by thermal oxidation.
`Because of such “bird’s beak” problems, the art has
`experienced some dif?culty in achieving well-de?ned
`lateral isolation boundaries.
`In addition, while, as previously mentioned, air isola
`tion has been used in the prior art in integrated circuits,
`no practical approach has been developed for the appli
`cation of air isolation to high density, large scale inte
`grated circuits.
`
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`SUMMARY OF THE INVENTION
`Accordingly, it is an object of the present invention
`to provide an air-isolated integrated circuit structure
`with a planar wirable surface.
`It is another object of the present invention to pro
`vide an air-isolated integrated circuit structure in which
`the air isolation regions are of minimal dimensions so
`that the integrated circuit structure is adaptable to high
`device density integrated circuits.
`It is a further object of the present invention to pro
`vide an air-isolated integrated circuit structure in which
`both the upper and lower surfaces of the structure are
`planar.
`It is yet a further object of the present invention to
`provide a dielectrically isolated integrated circuit struc
`ture in which both upper and lower surfaces are planar
`and which is substantially free from stresses created by
`changes in volume in the semiconductor material dur
`ing integrated circuit fabrication heating steps.
`It is an even further object of the present invention to
`provide a method for fabricating an integrated circuit
`structure having the above described advantages.
`In accordance with the present invention, there is
`provided an integrated circuit member comprising a
`semiconductor substrate having formed therein a pat
`tern of cavities extending from one surface of the sub
`strate into the substrate and fully enclosed within the
`member, a plurality of pockets of semiconductor mate
`rial extending from said surface laterally surrounded
`and electrically insulated by said cavities and a planar
`layer of electrically insulative material on the surface.
`The integrated circuit member is formed by a fabrica
`tion method comprising ?rst etching a pattern of cavi
`ties extending from one surface of a ?rst silicon sub
`strate into the substrate; the cavities laterally surround
`and electrically isolate the plurality of silicon substrate
`pockets. Next, a ?rst layer of silicon dioxide is formed
`
`4
`on this ?rst substrate surface. There is also formed over
`a second silicon substrate a planar second layer com
`prising a glass, and preferably a siliceous glass. The
`glass composition may be any conventional glass com
`position including those described in Volume 10, pp.
`533-546, of the Encyclopedia of Chemical Technology,
`Kirk and Othmer, Second Edition, published in 1966 by
`Interscience Publishers. However, the silicate glasses,
`such as those described on pp. 540-545 in the above
`encyclopedia, have been found to be particularly desir
`able. The term “siliceous glass” as used in this applica
`tion, is meant to include all silica-containing glasses
`including glasses which are substantially unmodi?ed
`silica (SiOZ). In addition, among the silicate glasses
`which may be used are alkali silicate glasses which are
`modi?ed by NaZO, soda-lime glasses, borosilicate
`glasses, alumino-silicate glasses, and lead glasses. Then,
`the two substrates are bonded together by fusing the
`planar layer over the second substrate to the silicon
`dioxide layer over the ?rst substrate to thereby fully
`enclose the cavities. Finally, the second silicon substrate
`is removed from the fused structure.
`The resulting structure is one having a planar surface,
`at which the active devices of the integrated circuit may
`be subsequently formed, i.e., the surface of the ?rst
`silicon substrate covered by the planar layer of silicon
`dioxide. Further, since the cavities have been formed by
`etching down from this surface rather than the back side
`surface of the structure, only minimal lateral integrated
`circuit “real estate” has been consumed in forming such
`cavities. In addition, the back side surface of the struc
`ture remains unetched and thus planar. Finally, because
`of the fully enclosed air-isolation, the structure has
`cavities capable of absorbing changes in volume of the
`silicon material resulting from the application of heat
`during the processing steps. Thus, heat-induced stresses
`are minimized.
`The foregoing and other objects, features and advan
`tages of the invention will be apparent from the follow
`ing more particular description of the preferred embodi
`ments of the invention, as illustrated in the accompany
`ing drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIGS. 1-7 are diagrammatic sectional views of a
`portion of an intregrated circuit in order to illustrate the
`method of forming the preferred embodiment of the
`present invention.
`
`PREFERRED EMBODIMENTS OF THE
`PRESENT INVENTION
`FIGS. 1-7 illustrate the preferred embodiment of the
`present invention. On a suitable P- wafer 10 having a
`resistivity of 10 ohm/cm, an N+ region 11 which will
`subsequently serve as a subcollector is formed by con
`ventional thermal diffusion of impurities as set forth for
`example in US. Pat. No. 3,539,876. When introduced
`into substrate 10, N+ region 11 has a surface concentra
`tion of 1021 atoms/cm3. Region 11 may also be formed
`by conventional ion implantation techniques.
`Then, FIG. 2, a pattern of recesses or cavities 12 are
`etched in the substrate. This pattern of recesses corre
`sponds to the desired air-isolation pattern for the inte
`grated circuit structure. Recesses 12 are formed by
`etching utilizing a conventional mask such as a silicon
`dioxide mask formed by standard photolithographic
`integrated circuit fabrication techniques which mask
`has apertures corresponding to the recessed pattern to
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`be formed. Then, the substrate may be etched in the
`silicon dioxide is also resistant to such etchants and may
`conventional manner ‘through the apertures de?ned in
`be used alone without the nitride. In any event, if, as in
`the silicon dioxide mask.
`FIG. 4A, silicon nitride is to be used, a layer 202 having
`It should be noted that these recesses may be formed
`a thickness in the order of from 1000 A-ZOOO A may be
`utilizing a conventional etchant for silicon such as a
`formed by any conventional technique‘ such as the
`composition of nitric acid and diluted hydro?uoric acid
`chemical vapor deposition reaction of silane and ammo
`in which case they will have the conventional sloped or
`nia. Alternatively, silicon nitride layer 22 may be depos
`tapered shape of recesses etched in silicon. Alterna
`ited by conventional RF sputter deposition techniques.
`tively, they may be formed by a technique of vertical
`At this point, the structure of FIG. 4A is abutted
`walled etching as described in the aforementioned
`against the structure of FIG. 4 and silicon dioxide layer
`R.C.A. Review article, June 1970, particularly at pages
`20 is fused to silicon dioxide layer 14 to fully enclose
`272-275, wherein the substrate 10 should have a (110)
`cavity pattern 12.
`surface orientation and the etchant utilized would be a
`The fushion of layers 14 and 20 may be achieved by
`boiling mixture of 100 grams KOH in 100 cc of water in
`heating the abutting structure in the steam atmosphere
`which case recesses 12 will have the substantially verti
`at temperatures in the order of l200° C. for about one
`cal-walled structure. For purposes of the present illus
`half hour. Alternatively, fusion temperature may be
`tration, recesses 12 are in the order of 2 microns in
`reduced by forming a thin layer of phosphosilicate glass
`depth.
`or borosilicate glass on the surfaces of either silicon
`Next, FIG. 3, utilizing conventional integrated circuit
`dioxide layers 14 and 20. This may be accomplished by
`fabrication techniques, N-type epitaxial layer 13 is de
`the simple expedient of slightly etching the surfaces of
`posited over the substrate. Epitaxial layer 13 has a maxi
`layers 14 and 20 prior to the fusion step to make these
`mum impurity concentration or doping level of l0l8
`layers hydrophilic and then depositing a small amount
`atoms/cm3 and is deposited by conventional techniques
`of either boric acid solution (saturated aqueous boric
`at a temperature in the order of from 950° C.-1150° C.
`acid solution) or dilute phosphoric acid solution on
`During the deposition of epitaxial layer 13, portions of
`25
`either or both of the layers 14 and 20. This results in a
`the layer 13’ are deposited in cavities 12. Layer 13 has a
`thin layer of either borosilicate or phosphorsilicate glass
`thickness of about 2 microns. It should be noted that if
`being formed on the surface of the silicon dioxide layers
`it is considered desirable in the integrated circuit struc
`thus treated. These glasses may also be formed by dop
`ture to avoid deposition of epitaxial layer portions 13' in
`ing with boron or silicon in the conventional manner.
`the cavities 12, epitaxial layer 13 may be deposited im
`When such a thin borosilicate or phosphosilicate glass
`mediately after Step 1 and prior to the formation of the
`layer is formed on the surface, the fusion step may be
`cavities in Step 2. In such a case, cavities 12 should be
`etched to a depth beyond the P—/N+ junction. Since
`then carried out at a lower temperature in the order of
`1100° C. by heating in an oxidizing ambient, e.g., heat
`substrate 10 is P—, it may be subject to conventional
`surface inversion problems well-known in the art in
`ing in steam for about ?fteen minutes followed by heat
`certain integrated circuit applications. A higher concen
`ing in dry oxygen for about ?fteen minutes to complete
`tration of P dopant may be introduced in those portions
`the fusion. Alternatively, the slight etch to make one of
`of cavity 12 abutting substrate 10 by standard impurity
`the layers hydrophilic may be used alone to similarly
`introduction techniques such as diffusion or ion implan
`reduce the required fusion temperatures.
`tation subsequent to the formation of the trench but
`In a variation of the illustrated embodiment, any
`prior to the formation of silicon dioxide layer 14.
`standard borosilicate or phosphosilicate glass having a
`Next, FIG. 4, a layer of silicon dioxide 14 preferably
`high melting point of at least 1100“ C. may be used in
`having a thickness in the order of from 3,000 A—l0,000
`place of silicon dioxide to provide the siliceous material
`A is formed over the surface as shown using any con
`of layer 20. This high temperature glass may be depos
`ventional silicon dioxide formation technique such as
`ited by any conventional technique such as sedimenta
`chemical vapor deposition or RF sputter deposition, or
`tion, RF sputtering or vapor phase deposition.
`preferably, by standard thermal oxidation.
`Silicon substrate 21 is then removed and silicon ni
`Next, as shown in FIG. 4A, a layer of silicon dioxide
`tride layer 22 optionally removed to provide the struc
`20 which is to provide the planar surface of the inte
`ture shown in FIG. 6 wherein silicon dioxide layer 20
`grated circuit structure is deposited on a separate wafer
`provides a planar surface over the entire structure fully
`21 of silicon. Wafer 21 should be as thin as possible but
`enclosing air-isolation cavity pattern 12. Silicon wafer
`still be handleable without breakage. Wafer 21 may be
`21 may be removed by any combination of conventional
`either monocrystalline or polycrystalline silicon. Such a
`wafer polishing, grinding or etching techniques. Most
`thickness may be conveniently between 3 and 5 mils.
`conveniently, most of the upper portion of substrate 21,
`Silicon dioxide layer 20 which has a thickness in the
`FIG. 5, may be ?rst removed by any conventional pol
`order from g to 3 microns may be formed by any of the
`ishing or grinding technique followed by any conven
`conventional techniques for forming silicon dioxide on
`tional etching technique including chemical etching or
`a semiconductor substrate, e.g., chemical vapor deposi
`sputter etching with either nonreactive or reactive ions.
`tion, sputter deposition or thermal oxidation of the sili
`As ‘set forth previously, the etching may be carried out
`con substrate. However, in accordance with one aspect
`using selected etchants or etching techniques to which
`of the present invention which will be described in the
`either the silicon nitride layer 22 if used or the silicon
`present embodiment, it may be desirable to have an
`dioxide layer 20 is more resistant than is silicon wafer
`intermediate layer of an etch barrier material such as
`21. If present, the silicon nitride layer 22 may be option
`silicon nitride between silicon substrate 21 and silicon
`ally removed using a conventional etchant for silicon
`dioxide layer 20. As will be hereinafter described, when
`65
`nitride to which the silicon dioxide is resistant. Such a
`silicon substrate 21 is removed by chemical etching,
`conventional etchant for silicon nitride is hot phos
`silicon nitride is somewhat more resistant to conven
`phoric acid or hot phosphoric salt.
`tional silicon etchants than is silicon dioxide, although
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`The resulting structure shown in FIG. 6 has a planar
`silicon dioxide layer over a plurality of silicon pockets
`23 which are laterally air-isolated by cavity pattern 12.
`Then, utilizing the structure of FIG. 6, the active
`devices of the integrated circuit may be formed utilizing
`conventional integrated circuit fabrication techniques
`to introduce regions of selected conductivity-types such
`as P region 24 into isolated silicon pockets 23 (FIG. 7)
`through openings 25 formed in silicon dioxide layer 20
`by conventional integrated circuit photolithographic
`fabrication techniques. Then, after such regions are
`formed, the regions may be readily interconnected by
`conventional integrated circuit metallization or wiring
`techniques subsequently formed on the planar surface of
`silicon dioxide layer 20.
`It should be noted that for any of the foregoing pro
`cessing steps involving etching either to form recesses
`in layers or substrates or to remove layers, any conven
`tional etching technique may be employed such as those
`described in US. Pat. No. 3,569,876. Alternatively, any
`of the above etching steps may be carried out by sputter
`etching, utilizing conventional sputter etching appara
`tus and methods such as those described in US. Pat. No.
`3,598,710, particularly sputter etching carried out utiliz
`ing reactive gases such as oxygen or hydrogen or chlo
`rine. U.S. Pat. No. 3,471,396 sets forth a listing of inert
`or reactive gases or combinations thereof which may be
`used in sputter etching.
`While the invention has been particularly shown and
`described with reference to the preferred embodiments
`thereof, it will be understood by those skilled in the art
`that various changes in form and details may be made
`35
`therein without departing from the spirit and scope of
`the invention.
`What is claimed is:
`
`4,169,000
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`1. A method for fabricating an integrated circuit
`member comprising
`etching a pattern of cavities extending from one sur
`face of a ?rst silicon substrate into said substrate,
`said cavities laterally surrounding and electrically
`insulating a plurality of substrate pockets,
`forming a ?rst layer of silicon dioxide on said ?rst
`substrate surface,
`forming a planar second layer comprising siliceous
`glass over a second silicon substrate,
`fusing said planar layer to said silicon dioxide layer to
`thereby fully enclose said cavities, and
`removing said second silicon substrate.
`2. The method of claim 1 wherein said planar sili
`ceous glass layer is a layer of silicon dioxide.
`3. The method of claim 1 wherein said planar sili
`ceous glass layer is a layer of a high temperature glass
`having a melting point of at least 1100° C.
`4. The method of claim 2 wherein a layer of silicon
`nitride is deposited on said second silicon substrate
`before the formation of said planar layer.
`5. The method of claim 4 wherein at least the ?nal
`portion of said second silicon substrate is removed by
`etching down to said silicon nitride layer.
`6. The method of claim 2 wherein said ?rst layer of
`silicon dioxide is deposited on said ?rst substrate surface
`so as to form a lateral layer of silicon dioxide on the
`lateral surfaces of said substrate pockets abutting said
`cavities.
`7. The method of claim 1 further including the steps
`of
`forming at least one opening through said planar
`layer'coincident with a portion of an underlying
`substrate pocket, and
`selectively introducing impurities through said open
`ing into said substrate to form a region of a selected
`conductivity-type in said substrate.
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