United States Patent [191
`Matsuda et al.
`
`[11]
`[45]
`
`4,131,909
`Dec. 26, 1978
`
`[54] SEMICONDUCTOR INTEGRATED CIRCUIT
`ISOLATED THROUGH DIELECTRIC
`MATERIAL AND A METHOD FOR
`MANUFACTURING THE SAME
`[75] Inventors: Takashi Matsuda; Kazuo Niwa;
`Yasusuke Sumitomo, all of
`Yokohama, Japan
`Tokyo Shibaura Electric 00., Ltd.,
`Tokyo, Japan ,
`,[21] Appl. No.: 735,784
`[22] Filed:
`Oct. 26, 1976
`[30]
`Foreign Application Priority Data
`Oct. 25, 1975 [JP]
`Japan .............................. .. 50-128773
`
`[7 3] Assignee:
`
`[51] Int. cm ................... .. H01L 27/12; H011. 29/78;
`H01L 27/02; HOlL 29/04
`[52] US. Cl. ...................................... .. 357/49; 357/23;
`357/41; 357/59; 357/67; 29/571
`[58] Field of Search ..................... .. 357/23, 41, 49, 59,
`357/67
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`3,191,061
`
`6/1965 Weimer ................................ .. 357/41
`
`4/ 1968 Thornton ............................. .. 357/49
`3,381,182
`3,407,479 10/1968 Fordemwalt et a1.
`.... .. 357/49
`
`3,475,664 10/1969 DeVries . . . . . . . . . . . . . .
`
`. . . . .. 357/49
`
`3,514,676
`
`5/ 1970 Fa . . . . . . . . . . . .
`
`. . . . .. 357/42
`
`3,602,981
`
`9/1971 Kooi . . . . . . . .
`
`. . . . .. 357/49
`
`3,865,649
`
`2/ 1975 Beasom . . . . . . . . . . . . . . .
`
`. . . . .. 357/42
`
`3,874,918
`3,944,447
`
`.... .. 357/49
`4/1975 Nechtow et a1.
`3/ 1976 Magdo et a1. ........................ .. 357/49
`
`Primary Examiner—Wi1liam D. Larkins
`Assistant Examiner-Gene M. Munson
`Attorney, Agent, or Firm-Oblon, Fisher, Spivak,
`McClelland & Maier
`[57]
`ABSTRACT
`A semiconductor integrated circuit includes ?rst and
`second island regions, surrounded by a bottomed dish
`like dielectric layer formed on one side of a support
`body. A MOS transistor element is formed in the ?rst
`island region, whose gate region is located at the bottom
`side of the island region. The gate electrode is con
`nected to a bottom portion of the second island region,
`which is used as a gate electrode contact region, in the
`support body using a interconnection lead. There is a
`method for manufacturing the above device.
`
`6 Claims, 13 Drawing Figures
`
`Raytheon2050-0001
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`Sony Corp. v. Raytheon Co.
`IPR2015-01201
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`

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`U.S. Patent
`
`Dec. 26, 1978
`
`Sheet 1 of3
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`4,131,909
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`Raytheon2050-0002
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`US. Patent Dec. 26, 1978
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`Sheet 2 of3
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`4,131,909
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`26
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`27
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`FIGBE
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`Raytheon2050-0003
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`US. Patent Dec. 26, 1978
`
`Sheet30f3 ,
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`4,131,909
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`Raytheon2050-0004
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`

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`1
`
`SEMICONDUCTOR INTEGRATED CIRCUIT
`ISOLATED THROUGH DIELECTRIC‘ MATERIAL
`AND A METHOD FOR MANUFACTURING THE
`SAME
`
`BACKGROUND OF THE INVENTION
`Field of Invention
`This invention relates to a semiconductor integrated
`circuit whose island region is electrically isolated
`through a dielectric layer, and a method for manufac
`turing the same.
`Description of the Prior Art
`It is known that a digital integrated circuit using
`Metal Oxide Semiconductor Transistor (hereinafter
`referred to merely as MOS transistor) is superior to a
`circuit using bipolar transistors in such points as integra
`tion density, power consumption and ease of manufac
`
`ture.
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`4,131,909
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`However ‘in the MOS integrated circuit, the thickness
`of the monocrystalline layer is about 1 pm. Accordingly
`it is very difficult to make the thickness constant within
`a scattering value of i0.1 am using a lapping method
`or an etching process. Therefore, application of this
`technique to the MOS integrated circuit is very diffi
`cult.
`Furthermore, in the process where a polycrystalline
`layer is formed by gas phase growth, at ?rst the size of
`a polycrystalline particle is small. However it becomes
`larger and larger with the advance of the polycrystal
`line growth, which causes a warp of the semiconductor
`substrate owing to the difference of the expansion coef
`ficient of the polycrystalline layer in the direction of its
`depth. Furthermore, warping occurs also owing to the
`difference of expansion coefficient between the poly
`crystalline layer and the monocrystalline layer in which
`the semiconductor element is formed. This warp of the
`semiconductor substrate is difficult to be got rid of, and
`make the subsequent photoetching process difficult.
`For these reasons, the prior art as above mentioned is
`unsuitable for manufacturing the semiconductor inte
`grated circuit.
`
`is
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`However, in operating speed, the former is inferior to
`the latter. To overcome this shortcoming of the MOSv
`integrated circuit, namely to increase the operating
`speed, the SOS (Silicon on Sapphire or Spinel) tech
`nique was recently developed. This technique is as fol
`lows: after growing a silicon layer having 1 pm thick
`ness on one surface of sapphire monocrystalline sub
`strate by using epitaxial process, a selective etching is
`made to remove the epitaxial layer selectively, leaving
`some portions where circuit elements-are formed. This
`technique has some merits as follows compared with the
`conventional one.
`1) High speed of the circuit operation owing to the
`decrease of parastic capacitance according to the de
`crease of PN junctions.
`2) High integration density of the integrated circuit
`owing to the decrease of the area of isolation region
`between circuit elements. However, this SOS technique
`is accompanied with such inconvenient phenomenon as
`lattice defects owing to the difference of lattice constant
`and crystal construction between silicon and sapphire,
`occurrence of aluminum impurity by reaction of the
`sapphire substrate with silicon layer and warp of the
`sapphire substrate owing to the difference of the expan
`sion coefficients of both. These increase the leakage
`current of the device two to three fold compared with
`bulk silicon’s, which makes the power consumption
`high. Furthermore, the carrier mobility becomes
`smaller sharply, and accordingly, the operating speed of
`the integrated circuit is decreased. For these reasons, it
`50
`is difficult to apply this SOS technique to CMOS (Com
`plementary Metal Oxide Semiconductor) circuit and
`the Dynamic circuit.
`On the other hand conventionally known is a semi
`conductor integrated circuit in which an electrical insu
`lation is made between semiconductor elements using a
`dielectric layer. A plurality of semiconductor elements
`of the integrated circuit are arranged at a predetermined
`interval on one side of a semiconductor polycrystalline
`layer, and a dielectric layer or insulator separation layer
`60
`is formed in a manner to insulate the semiconductor,
`elements from the polycrystalline layer. In this inte
`grated circuit, the ?oating capacitance is very small, so
`that high break down voltage is obtained. Accordingly
`the abovementioned technique is especially used in the
`65
`bipolar integrated circuit in which the thickness of
`monocrystalline layer is about 3 pm to 10 um, so that
`therefore, the scatter of the thickness is of little matter.
`
`SUMMARY OF THE INVENTION
`This invention overcomes the problems arising from
`the processing sequence and the construction of the
`prior art wherein the polycrystalline layer is grown by
`gas phase.
`One object of this invention is to provide a method
`capable of easily manufacturing a semiconductor inte
`grated circuit isolated through dielectric material.
`Another object of this invention is to provide a semi
`conductor integrated circuit having an island region
`isolated through dielectric material, and having a MOS
`transistor element in the island region, whose gate re
`gion is located at the bottom side of the island region.
`Yet another object of this invention is to provide a
`semi-conductor integrated circuit without warp of the
`support body.
`Further object of this invention is to provide a semi
`conductor integrated ‘circuit whose power consumption
`is small and operating speed is very high.
`In one aspect of this invention, a semiconductor inte
`grated circuit comprises a support body, at least one
`bottomed enclosed dielectric layer whose one end is
`open at one surface of the support body forming an
`island region, a MOS transistor element in the island
`region having source, drain and gate regions, wherein
`said source and drain regions are formed adjacent to
`said one surface of the support body and the gate region
`is formed at a bottom portion of the island region.
`In another aspect of this invention, a method for
`manufacturing a semiconductor integrated circuit com
`prises the steps of: forming a mask layer on one side
`surface of ?rst semiconductor substrate having ?rst
`conductivity; removing at least two portions of the
`mask layer; etching the semiconductor substrate down
`to a predetermined depth through the exposed portions
`thereof to form ?rst and second mesa regions; forming
`a gate insulating layer at a portion on the top surface of
`the ?rst mesa region; forming source and drain regions
`in the first mesa region and gate electrode contact re
`gion in second island region so as to reach to the bottom
`of the mesa regions respectively, by diffusing an impu
`rity having second conductivity type forming a gate
`electrode on said gate insulating layer and an intercon
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`nection lead which connects said gate electrode andv
`said gate electrode contact region; growing a insulating
`layer which surrounds the mesa regions to form island
`regions; ?tting a second substrate to said ?rst semicon
`ductor substrate including said island regions using a
`glass adhesive plaster at low temperature; etching the
`?rst semiconductor substrate to exposure said source,
`drain and gate electrode contact regions, forming
`source electrode, drain electrode and gate outer elec
`trode on the exposure surface of said island region,
`contacting to said exposed regions respectively.
`
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`BRIEF DESCRIPTION OF THE DRAWINGS
`This invention will now be explained in reference to
`the accompanying drawings, in which:
`FIG. 1 is a plan view showing an embodiment of this '
`invention.
`FIG. 2 is a sectional view taken along the A-A line
`of FIG. 1 showing an embodiment of this invention.
`FIGS. 3A to 3] are process views for explaining a
`method for manufacturing a semiconductor integrated
`circuit as shown in FIGS. 1A and 1B.
`FIG. 4 is a section view showing a semiconductor
`integrated circuit according to another embodiment of
`this invention.
`25
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`4
`layers, using C.V.D. (Chemical Vapour Deposition)
`method.
`Then, as shown in FIG. 3B, selective etching is made
`so as to expose the n conductive type layer (24) leaving
`a corresponding portion where island regions are to be
`formed, using hydrazine as etchant.
`Likewise, as shown in FIG. 3C selective etching is
`made to remove the portions of the layer (24) not cov
`ered by the mask layers (25)(26), and thermal oxide
`layer (27) having 6000 A thickness is grown over the
`surface of the epitaxial layer except where covered by
`the masking layers (25)(26). Subsequently as shown in
`FIG. 3D the masking layers are removed, for instance
`silicon nitride ?lm (26) is removed by plasma etching
`method, and thermal oxide layer (25) is etched by ?uori
`dation ammonium. In this process, thermal oxide layer
`(25) isn’t- all removed, because the thickness of the layer
`(27) is 6000 A, while that of the thermal oxide layer (25)
`is 1000 A. Next, as shown in FIG. 3B gate oxide layer
`(16B) is grown on a portion of the epitaxial layer (24) in
`the oxide atmosphere at 1100° C., and as shown in FIG.
`3F polycrystalline layer is selectively grown to form
`interconnection lead (18) and gate electrode (16A).
`Subsequently, as shown in FIG. 3G boron as an impu
`rity is diffused into the portions of epitaxial layer (24)
`where source, drain and gate electrode contact regions
`(14), (15) and (16) are to be formed. In this diffusion
`process, at the same time, the impurity is doped in the
`polycrystalline layers (16A), (18) to perfect intercon-..
`nection lead (18) and gate electrode (16A) lowering the
`resistivity. As is well known the impurity penetrates in
`the polycrystalline layer (18) but not in the SiO; layer
`(16B). This diffusion is made so as to reach the layer
`(23). Furthermore, the gate electrode (16A) and inter
`connection lead (18) may be made of metal layer. In this
`case, the forming of source and drain regions must be
`made previous to the forming of gate electrode (16A)
`and interconnection lead (18). Then as shown in FIG.
`3H SiO; layer (13) having 5000 A thickness is grown on
`the entire surface of the substrate using C.V.D. method
`about at 500° C. As shown in FIG. 31, the semiconduc
`tor substrate having the abovementioned island regions
`is ?tted to another semiconductor substrate (12) using
`Pb0-Si02 system glass (28) as adhesive plaster, whose
`expansion coef?cient is about equal to the monocrystal
`line silicon substrate’s, at low temperature 500° C.,
`where the warp of substrate doesn’t happen. Then,
`substrate (22) and epitaxial layer (23) are etched away
`by some etchants down to B—B line. Firstly the sub
`strate (22) is etched using a etchant consisting of HF,
`HNO3 and CH3COOH and secondly epitaxial layer (23)
`is etched using hydrozine. Next, as shown in FIG. 3] on
`the etched surface of island regions, thermal oxide layer
`(29) having 6000 A thickness is formed, and drain,
`source and gate electrode contact portions of the ther
`mal oxide layer are apertured. Subsequently, aluminum
`layer is evaporated on the thermal oxide layer and elec
`trode contact portions of MOS transistor, and selective
`etching of the metal layer is made to form source elec
`trode (20), drain electrode (21) and gate outer electrode
`(17).
`FIG. 4 shows another embodiment according to this
`invention. In this embodiment, gate electrode (16A) of
`MOS transistor is led out using inner lead (40) which
`extends to the surface of the island region, isolated from
`other regions by insulating layer (13)(41).
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`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`There will now be discussed a semiconductor inte
`grated circuit according to one embodiment of this
`invention with reference FIGS. 1 and 2.
`'
`In FIGS. 1 and 2, a MOS transistor in a semiconducé
`tor integrated circuit according to this invention is
`shown Two island regions (10), (11) are formed in the
`glass layer (28) on the semiconductor substrate (12),
`surrounded by a dielectric layer (13), made of SiO;. In
`one island region (10), a MOS transistor having a source
`region (14), a drain region (15) and a gate region (16),
`and in another island region (11) a gate electrode
`contact region (17) are formed, in which the gate region
`(16) is formed at a bottom portion of the island region
`(10) and gate electrode (16A) is connected to the gate
`electrode contact region (17) by interconnection lead
`(18). The gate electrode contact region‘ (17) is formed at
`the same time when source region (14) and drain region
`(15) are formed by diffusing an impurity. Finally, gate
`outer electrode (19), source electrode (20) and drain
`electrode (21) are formed at apertures of the SiO; layer
`on the surface of the island regions (10), (11). Gate
`electrode (16A) and interconnection lead (18) are made
`50
`of doped polysilicon layer.
`Explanation is now made upon reference to FIGS.
`3A to SI, of a method of manufacturing a semiconduc
`tor integrated circuit of the above construction.
`In FIG. 3A, use is made of a n conductive type silicon
`wafer (22) whose top surface is oriented to a (100) face
`and whose speci?c resistance is below 0.005 (tom, and
`having the thickness of 300 um.
`Thewafer (22) has on the top surface a layer (23) of
`p conductive type having a resistivity above 1 (tom and
`a thickness of 4 pm, which is epitaxially grown using a
`known epitaxial vapour growth method. Subsequently,
`n conductive type epitaxial layer (24) having a resistiv
`ity of 5 Gem and a thickness of 1.3 pm is formed on the
`p conductive type layer (23). Furthermore a thermal
`oxide layer (25) having 700 A thickness and a silicon
`nitride ?lm (26) having 1000 A thickness are formed on
`the n conductive type layer (24) successively as masking
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`4,131,909
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`the glass layer is a Pb-SiOz system whose expansion
`In this embodiment, the inner lead is made of alumi
`coef?cient is substantially the same as that of
`num metal layer or. double metal layers of aluminum
`monocrystalline silicon.
`and titanium.
`_
`4. The semiconductor integrated circuit recited in
`In summary, this invention provides several advan
`claim 1 wherein the ?rst island region of material is
`tages over the prior art. Among these advantages are
`doped with an impurity to lower its resistance; and the
`?rst, the warp of a support body doesn’t happen because
`support body has a second recess in the top surface
`a semiconductor substrate including island region is
`thereof, the dielectric layer being coated uniformly
`?tted to another substrate at low temperature. Second
`over the top surface and ?rst and second recesses; and
`the interconnection of circuit elements is easy and the
`including a second island region of material disposed
`integration density of the integration circuit becomes
`over the dielectric layer in the second recess, the second
`high because the interconnections can be made in the
`island region including a gate electrode contact region
`support body. Lastly, the method according to this
`and interconnection means for electrically connecting
`invention hasn’t a lapping process, therefore the manu
`the gate electrode contact region to the insulated gate
`facturing of the semiconductor integrated circuit be- .
`electrode of the metal-oxide-semiconductor transistor
`15
`comes easy and accurate.
`element of the ?rst island region; a ?rst electrode led
`Although this invention has been disclosed and illus
`out from the source region of the metal-oxide-semicon
`trated with reference to particular applications, the
`ductor transistor element; a second electrode led out
`principles involved are susceptible of numerous other
`from the drain electrode of the metal-oxide-semicon
`applications which will be apparent to those skilled in
`ductor transistor element; and a third electrode led out
`the art. The invention is, therefore, to be limited only as
`from the gate electrode contact region.
`indicated by the scope of the amended claims.
`5. The semiconductor integrated circuit recited in
`What is claimed as new and desired to be secured by
`claim 4 wherein the interconnection means is a doped
`Letters Patent of the United States is:
`polycrystalline silicon layer.
`1. A semiconductor integrated circuit comprising:
`6. A semiconductor integrated circuit comprising:
`a support body having a top surface and a ?rst
`a support body having a top surface and a stepped
`stepped recess in the top surface, the ?rst recess
`recess in the top surface, the recess having an upper
`having an upper step and a lower step;
`step and a lower step;
`a dielectric layer coated uniformly over the top sur
`a dielectric layer coated uniformly over the top sur
`face and the ?rst recess;
`face and the recess in the top surface;
`a ?rst island region of material disposed over the
`an island region of material disposed in the recess, the
`dielectric layer in the ?rst recess, the ?rst island
`island region having a top surface and forming a
`region forming a metal-oxide-semiconductor tran
`metal-oxide-semiconductor transistor element hav
`sistor element having separated source and drain
`ing separated source and drain regions on the upper
`regions on the upper step of the ?rst recess and an
`step of the recess and an insulated gate electrode on
`insulated gate electrode on the lower step of the
`the lower step of the recess; and
`?rst recess.
`a gate outer electrode on the top surface of the island
`2. A semiconductor integrated circuit recited in claim
`region, the gate outer electrode being led out from
`1 wherein:
`the gate electrode using a lead which extends to the
`the support body consists of a substrate and a glass
`top surface of the island region and is isolated from
`layer on the substrate.
`the source and drain regions by insulating layers.
`3. A semiconductor integrated circuit recited in claim
`2 wherein:
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