EXHIBIT B
`
`Micron Technology, Inc. at al., Petitioners - Ex. 1046
`Micron Technology, inc. and Micron Memory Japan. Inc. v. Massachusetts Institute of Technology
`|PR2015-01037
`1
`
`
`
`Micron Technology, Inc. at al., Petitioners - Ex. 1046
`Micron Technology, inc. and Micron Memory Japan. Inc. v. Massachusetts Institute of Technology
`|PR2015-01037
`1
`
`
`
`}
`
`Construction Analysis
`
`|
`
`Lattice ispLSI2032-180L
`CPLD
`
`s R
`
`eport Number: SCA 9712-573
`
`
`
`
`17350 N. Hartford Drive
`Soolisdale, AZ 35255
`Phone: 602-515-9780
`Fax: 502-515-9781
`e-mail: ice@ice-corp.com
`Internet: http://www,ice-corp.com
`
`INTEGRATED CIRCUIT EHGINEERING
`
`
`
`D
`
`TEXT
`
`TITLE
`
`INTRODUCTION
`
`MAJOR FINDINGS
`
`TECHNOLOGY DESCRIPTION
`
`Die Pmcess and Design
`
`ANALYSIS RESULTS
`
`Die Process and Design
`
`ANALYSIS PROCEDURE
`
`TABLES
`
`Overall Evaluation
`
`Die Material Analysis
`
`Horizontal Dimensions
`
`Vertical Dimensions
`
`2-3
`
`Suooow
`
`
`
`IE I EQD QCTION
`
`This report describes a constmction analysis ofthe lattice ispLSI 2032-180L Complex
`
`Programmable Logic Device (CPLD). One device packaged in a 44-pin Thin Quad-Flat-Pack
`
`(TQFP) was received for the analysis.
`
`MAJOR FINDINGS
`
`Questionable Items:1
`
`I Excessive metal 2 and metal 1 aluminum thinning.
`
`Special Features:
`
`0 Three types of EEPROM cells were used.
`
`0 Mature technology using thin tunnel-oxide windows.
`
`Ifllese itemspresent possible quality or reliability concerns. fliey should be discussed
`with the manu_f:rcturer to determine theirpossible impact on the intended application.
`
`-1-
`
`
`
`TECHNOLOGY DESCRIPTION
`
`Die Process and Design‘ :
`
`Fabrication process: Selective oxidation CMOS process employing twin-wells in an N
`
`substrate. No epi was used.
`
`Final passivationf A layer ofnitride over a layer of glass (no die coat was present).
`
`Metallization: Two levels of metal interconnect were used. Both metal 2 and metal 1
`
`consisted of aluminum with a thin titaniun1—nitride (TiN) cap and barrier. Standard vias
`
`and contacts were employed (no plugs)-
`
`Interlevel dielectric: Interlevel dielectric (between M2 and M1) consisted of two layers
`
`ofglass, with a spin-on-glass (SOG) between to provide planarization.
`
`Prc-metal dielectric: Consisted of a single layer of reflow glass (probably BPSG) over
`
`various densified oxides.
`
`Polysilicon: A single layer of dry-etched polycide (poly and tungsten silicide) was
`
`used. This layer formed all gates on the die, and in the cell array it forrnedthe
`
`capacitors, word lines, and tunnel oxide device. Oxide sidewall spacers were used on
`
`all gates, and left in place.
`
`Diffusion: Standard implanted N+ and P+ diffusions formed the sourcesfdrains of the
`
`MOS transistors.
`
`Wells: Twin-wells in an N substrate. A shallow N-well was located under the P-
`
`channel devices. N-channel devices were located within the P—wells. A step was noted
`
`in the local oxide at the edges ofthe well boundaries.
`
`
`
`TEQEINOLOGX DESCRIPTIOE (continued)
`
`0 The memoxy cell consisted of a standard EEPROM dwign- Metal was used to form
`
`the bit lines. Poly was used to form the Wordfselect lines, capacitors, and the tunnel
`
`oxide devices.
`
`I Redundancy fuses were not present
`
`
`
`ANALYSIS RESULIS
`
`Die Process:
`
`F’
`
`1 - 43
`
`Questionable Items:1
`
`0 Excessive metal 2 and metal 1 aluminum thinning.
`
`Special Features:
`
`0 Three types of EEPROM cells were used.
`
`0 Mature technology using thin tunnel-oxide windows.
`
`General Items:
`
`0 Fabrication pmcess: Selective oxidation CMOS process employing twin-well in a N
`
`substrate (no epi was used). No problems were found in this process.
`
`0 Pmeess implementation; Die layout was clean and efiicient. Alignment was good at all
`
`_ levels. No damage or contamination was found.
`
`0 Die coat: No die coat was present.
`
`I Final passivation: A layer ofnitride over a layer of glass. An integrity test indicated
`
`defect-free passivalion. Edge seal was good.
`
`I Metallizafion: Both metal 2 and metal 1 consisted of aluminmn with a thin titanium-
`
`nitride (Ti.N) cap and barrier defined by dry—etch techniques. Standard vias and contacts
`
`were used (no plugs).
`
`1These itemspresentpossible quality or reliability concerns. They should be discussea’
`with the manufacturer to determine their possible impact on the intended application.
`
`-4-
`
`
`
` (confinuw)
`
`0 Metal patterning: The metal layers were patterned by a dry etch ofnormal quality.
`
`Contacts were completely stmounded by metal and metal lines were widened at
`
`contacts.
`
`I Metal defects: No voiding, notching, or neckdown was noted in either metal layer.
`
`0 Metal step coverage: Metal 2 aluminum thinnedup to 100 percentatvias. Itwas
`
`reduced to 95 percent with the addition of the cap and barrier. Metal 1 aluminum
`
`thinned up to 100 percent at the contacts. This thinning was reduced to 95 percent with
`
`the addition ofthe cap and barrier. This thinning appears to be excessive and not under
`
`good controL
`
`I
`
`Interlevel dielectric: Interlevel dielectric (between M2 and M1) consisted of two layers
`
`of glass with a spin-on-glass between for planarization. No problems were found with
`
`these layers.
`
`0 Pre-metal dielectric: Consisted of a single layer ofreflow glass (probably BPSG) over
`
`a densified oxide. The glass was reflowed before contact cuts only. No problems were
`
`found.
`
`I
`
`0 Vias and contacts: Via and contact cuts appeared to be defined by a two-step dry etch.
`
`No over-etching or other contact problems were found
`
`0
`
`Polysilicon: A single layer of polycide (poly and tungsten silicide) was used to form
`
`all the gates on the die. In the cell, poly formed the wordfselect lines, capacitors, and
`
`the tunnel oxide device. Oxide sidewall spacers were used on all gates and left in place.
`
`I Diffusions: Standard implanted N+ and P+ difiilsions formed the sourcesfdrains of
`
`the MOS transistors. Difiisions were not silicided. No problems were noted.
`
`
`
`AN A LYSLS EESUL 13 (continued)
`
`0
`
`Isolation: Local oxide (LOCOS) isolation was used. A step was present in the oxide at
`
`the well boundaries.
`
`0 EEPROM arrays: Three types of EEPROM memory cells were used. Metal was
`
`used to form the bit lines. Poly formed the wordfselect lines, capacitors, and the tunnel
`
`oxide device. Smallest cell pitch was 8.95 x 13.5 microns.
`
`0 Redundancy fuses were not present on the die.
`
`
`
`PROCEDQ 3 E
`
`The devices were subjected to the following analysis procedures:
`
`Internal optical inspection
`
`SEM inspection of passivation
`
`Passivation integrity test
`
`Delayer to metal 2 and inspect
`
`Aluminum removal (metal 2)
`
`Delayer to metal 1 and inspect
`
`Dclayer to polyisubstrate and inspect
`
`Die sectioning (90° for _sEM)*
`
`Die material analysis
`
`Measure horizontal dimensions
`
`Measure vertical dimensions
`
`*Delineation ofcros.s'—secfion.s' is by silicon etch zmless otherwise indicated
`
`10
`
`
`
`OVERALL QUALIIZ EVALUATION: Overall Rating: Normal
`
`DETAIL OF EVALUATION
`
`Die surface integrity:
`
`Toolrnarks (absence)
`
`Particles (absence)
`
`Contamination (absence)
`
`Process defects (absence)
`
`General workmanship
`
`Passivation integrity
`
`Metal definition
`
`Metal integrity
`
`Contact-coverage
`
`Contact registration
`
`G3CJ%ZG}ZGJC)CDCD
`
`G = Good, P = Poor, N = Normal, NP = Normal/Poor
`
`D! E MATERIAL ANALYSIS
`
`Final passivation:
`
`A layer ofnitride over a layer of silicon-
`dioxide.
`
`Metallization 2:
`
`_
`
`Aluminum with a thin titanium-nitride (TiN) cap and
`
`barrier. An apparent titanium (Ti) adhesion layer
`under the barrier metal.
`
`Interlevel dielectric:
`
`'
`
`Two layers of silicon-dioxide.
`
`Metallization 1:
`
`Aluminum with a thin titaniu1n—nitride (TiN) cap and
`
`barrier. An apparent titanium (Ti) adhesion layer
`
`under the barrier metal.
`
`Pre-metal dielectric:
`
`A single layer ofBPSG reflow glass over a densified oxide.
`
`Poly:
`
`Tungsten (W) silicide.
`
`- 3 _
`
`
`
`HO
`
`O
`
`D
`
`ENSI NS
`
`Die size:
`
`Die area:
`
`2.1 X 4.5 mm (84 X175 mils)
`
`9.5 mm2 (14,700 milsz)
`
`Min pad size:
`
`0.1}: 0.1 mm (4.1 x 4.1 mils)
`
`Min pad Window:
`
`'
`
`0.08 x 0.08 mm (3.4 x 3.4 mils)
`
`Min pad space:
`
`Min metal 2 width:
`
`Minmetal 2 space:
`
`0.05 mm (2.2 mils)
`
`1.1 micron
`
`1.3 micron
`
`Min metal 2 pitch - (uncontacted):
`
`2.2 microns
`
`— (contacted):
`
`2.6 microns
`
`Min via:
`
`1.0 micron
`
`Min metal 1 width:
`
`0.8 micron
`
`Minmetal 1 space:
`
`1.0 micron
`
`Min metal 1 pitch - (uncontactcd):
`
`1.85 microns
`
`— (contacted):
`
`Min contact
`
`Min poly width - (cell):
`
`Min poly width - (periphery):
`
`Min poly space:
`
`2.3 microns
`
`1.0 micron
`
`0.65 micron
`
`0.5 micron
`
`0.9 micron
`
`Min gate length1 - (N-channel):
`
`0.5 micron
`
`- (P-channel):
`
`0.65 micron
`
`Cell area’ (smallest):
`
`120.8 microns?
`
`Cell sizez (smallest):
`
`8.95 x 13.5 microns
`
`1Physical gate length.
`2CeH shown in Figures 22 - 31.
`
`-10-
`
`12
`
`
`
`VE TIC
`
`DIM NSI N
`
`Die thickness:
`
`0.3 mm (13 mils)
`
`Lama
`
`Passivznion 2:
`
`Passivation 1:
`
`Metal 2 - cap:
`
`- aluminum:
`
`- banicr:
`
`0.45 micron
`
`0.27 micron
`
`0.04 micron
`
`0.74 micron
`
`0.11 micron
`
`Intcrlcvel dielecttic 1 - glass 2:
`
`0.48 micron
`
`- SOG:
`
`- glass 1:
`
`Metal 1 — cap:
`
`- aluminum:
`
`_- barrier:
`
`'
`
`Reflow glass:
`
`Poly - silicidc:
`
`- poly:
`
`Lowl oxide:
`
`N+ SID diffusion:
`
`P+ Sfi) diffusion:
`
`N—Wcll:
`
`P—wel1:
`
`I
`
`0 — 1.2 microns
`
`0.17 micron
`
`0.07 micron
`
`0.47 micron
`
`0.1 1 micron
`
`0.3 - 0.75 micron
`
`0.15 micron
`
`0.12 micron
`
`0.48 micron
`
`0.25 micron
`
`0.25 micron
`
`1.0 micron
`
`3.5 microns
`
`-11-
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