June 11-12, 1991
`Santa Clara Marriott Hotel
`Santa Clara, CA
`
`IEEE Catalog No.
`91TH0359-0
`
`• Library of Congress No.
`
`89-644090
`
`1991
`PROCEEDINGS
`EIGHTH ~JNTERNATIONAL
`IEEE
`VLSI MULTILEVEL
`INTERCONNECTION
`CONFEREN E
`
`1991
`
`NNECTION
`
`FERENCE
`
`IN COOPERATION WITH IEEE
`Electron Devices Society
`
`IPR2015-01087 - Ex. 1038
`Micron Technology, Inc., et al., Petitioners
`1
`
`

`
`l
`1 ! ,,
`
`r
`
`EIGHTH INTERNATIONAL
`
`VLSI MULTILEVEL INTERCONNECTION
`
`CONFERENCE PROCEEDINGS
`
`Papers have been printed without editing as received from the authors.
`
`All opinions expressed in the Proceedings are those of the authors and are
`not binding on The Institute of Electrical & Electronics Engineers, Inc.
`
`IEEE Catalog Number 91 TH0359-0
`
`Library of Congress No. 89-644090
`ISBN Number 0-87942-673-x Softbound
`N/A
`Casebound
`0-87942-674-8 Microfiche
`
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`Copyright © 1991 by the Institute of Electrical and Electronics Engineers, Inc.
`
`2
`
`2
`
`

`
`A FOUR-LEVEL-METAL FULLY PLANARIZED INTERCONNECT TECHNOLOGY
`
`FOR DENSE HIGH PERFORMANCE LOGIC AND SRAM APPLICATIONS
`
`·Ronald R. Ut~echt and Robert M. Geffken
`IBM General Technology Division
`Essex Junction, Vermont 05452
`
`ABSTRACT
`
`This paper describes a four-level-metal (4LM) interconnect technology
`used to wire high-density, high-performance logic and SRAM chip designs.
`Process features
`include oxide planarization under all metal levels,
`tungsten studs for contacts and inter level vias,
`layered titanium and
`aluminum-0.5% copper metal lines patterned by reactive ion etch (RIE),
`and fusible metal links for redundancy applications.
`Functional 300K
`circuit ASIC
`logic test sites (4LM) and 256K SRAMs
`(31M) have been
`fabricated in both 125-mm and 200-mm wafer sizes. Process details are
`described along with
`the results of standard electrical tests and
`reliability stresses.
`
`INTRODUCTION
`
`The continuing drive to achieve greater density and performance in
`CMOS
`logic and SRAM applications is placing ever-increasing demands on
`multilevel interconnection technology.
`Indeed, present ASIC offerings
`with high circuit counts and large chip sizes are usually wiring-limited;
`it is not unusual to have less than 60% of the available circuits wired
`on these chips. Current-generation designs require up to five levels of
`metal to satisfy all of the wiring needs. Maximum
`layout efficiency
`requires the ability to make vertical connections between any of these
`metal levels in a minimum space. The interconnect technology chosen to
`accomplish this task must also meet
`the performance and reliability
`targets of the designs and be manufacturable.
`
`The interconnect process described in this paper was developed and
`piloted in a 125-mm logic manufacturing line and has been installed in a
`200-mm manufacturing line which it shares with 4-Mbit DRAM production at
`IBM's Essex Junction, Vermont, facility.
`In fact, this logic interconnect
`process was developed using the DRAM process as a base [1], and then
`modified in several areas to meet the needs of logic. Various process
`modules from IBM's East Fishkill [2], Yorktown [3] and Essex Junction
`development areas are included in the final integrated process.
`
`TECHNOLOGY FEATURES
`
`logic and SRAM
`technology provides
`interconnect
`This advanced
`to manufacture
`designers with
`the wireability
`features
`required
`high-density, high-performance
`logic and SRAM products.
`The wiring
`features include a
`local interconnect level and up to four levels of
`reactive-ion-etched
`(RIE)
`layered
`titanium and aluminum-0.5% copper
`wiring; each metal level is fabricated on top of a planarized insulator.
`
`20
`
`June 11-12, 1991 VMIC Conference
`TH-0359-0/91/0000-0020 $01.00 C 1991 IEEE
`
`3
`
`

`
`The metal pitch and thickness for each of the interconnect levels are
`listed in Table 1.
`
`Vertical tungsten stud vias are used to interconnect the wiring levels
`and stacked contacts and vias are allowed in the various product designs.
`As a further enhancement to wireability, metal borders around studs are
`not required for either the topside or underlying metal. Laser-blown
`metal fuses are also included in this technology and are primarily used
`for redundancy in stand-alone and imbedded SRAMs. Finally, in response
`to the I/0 requirements of VLSI
`logic, an area array of up to 1600
`lead/tin C4 terminals per chip is offered.
`
`PROCESS DESCRIPTION
`
`The basic process flow for each of the metal, insulator, and stud
`levels is repetitive and illustrated in Figure 1. The Al-Cu based film
`is sputter-deposited onto a planarized substrate, photo-patterned and
`then defined by RIE. A PECVD oxide is subsequently deposited over the
`underlying metal pattern. A deposition-etch-deposition sequence is used
`to provide adequate insulator-fill between minimum-spaced metal lines.
`The oxide is then planarized using a chemical-mechanical polish technique
`(CMP). Next, via-photo and RIE are employed to form nearly vertical vias
`down to the underlying metal level. A sputtered Ti/TiN liner and blanket
`CVD tungsten deposition processes are used to fill the vias (Figure ld).
`A second CMP process then removes the tungsten and liner material from
`the surface, leaving it in the vias (Figure le).
`
`Interconnect thickness and
`Table 1.
`wiring pitch.
`
`M1
`a) Metal deposition, patterning and RIE.
`
`Metal Level
`
`Thickness Wired Pitch
`(pm)
`(JJm)
`
`M1
`
`M2
`
`M3
`
`M4
`
`0.85
`
`1.05
`
`1.05
`
`2.0
`
`2.0
`
`2.4
`
`2.4
`
`4.8
`
`PECVD Oxide
`,---~M:-::-1:-----,1 C] C]
`b) Dep-etch-dep oxide deposition.
`
`c) Oxide chem-mech polish, via patterning
`and RIE.
`
`k\8
`PECVD Oxide
`1,__........,_,. _ ____,1 CJ
`e) Tungsten chem-mech polish removal.
`
`Figure 1. Process flow for metal, insulator
`and stud formation.
`
`21
`
`4
`
`

`
`r
`
`logic
`integrated four-level-metal
`A cross section of the final
`interconnect process is illustrated in Figure 2.
`As
`indicated,
`the
`tungsten studs are allowed to extend partially down the side of the metal
`levels.
`This is a consequence of allowing designs without
`wi.Y:ing
`metal-bordering.of vias. The final passivation is a layered structure
`of oxide, nitride and polyimide.
`An
`SEM
`cross
`section of
`a
`four-level-metal test structure fabricated with the processes described
`above is shown in Figure 3.
`
`The use of a similar process sequence under the first level of metal,
`as shown in Figure 2, avoids reliance on reflow of highly doped BPSG glass
`layers for pre-Ml planarization.
`The result is a process that yields
`superior planarity, when compared to reflow, and avoids the degradation
`of device properties and sheet resistance of salicided materials that
`accompany high-temperature processes.
`
`M4
`
`Figure 3. SEM cross section of
`four-level-metal structure.
`
`I
`I
`I
`I
`\
`
`..... _____________ ---
`
`Figure 2. Cross section of four-level(cid:173)
`metal structure .
`
`The use of redundant word and bit lines to repair defects in DRAMs
`and SRAMs is well known. Typically, the address of the redundant feature
`is incorporated into the operation of the chip by selectively blowing a
`series of fusible links. Fuses are integrated into this interconnect
`technology as part of the next to last level of metal as depicted in
`Figure 4. Any given fuse can be blown by focusing sufficient laser energy
`onto the appropriate metal line. As shown in the SEM cross section in
`Figure 5, a portion of the metal line and overlying insulator is removed
`during this operation. Unblown fuses remain passivated with oxide. This
`technique has been demonstrated by successfully fixing partially good
`256K SRAM chips. In addition, blown metal fuses have been subjected to
`
`22
`
`5
`
`

`
`Polyimide
`
`Polyimide
`
`PECVD Oxide 1
`PECVD Oxide ~
`M2
`
`M3
`
`I
`
`M2
`
`Figure 4. Cross section of metal fuse
`structure.
`
`Figure 5. SEM cross section of blown metal
`fuse.
`
`temperature-voltage-humidity reliability stressing with no
`standard
`problems observed.
`
`PROCESS INTEGRATION
`
`The interconnect technology described is unique in its heavy reliance
`on chemical-mechanical polish processes. Four oxide and four tungsten
`CMP operations are employed to produce the four wiring levels depicted.
`The integration of polishing into the technology yields many advantages.
`Photo exposures for both wiring and via levels are done on relatively
`planar surfaces. This is a key feature as manufacturing lines migrate
`toward exposure tools with higher resolution and reduced depth of focus.
`Although
`CMP
`does not yield
`true global planarization,
`local
`planarization is excellent. As a result, no topographical features are
`produced that can cause metal coverage problems and potential reliability
`defects.
`Another significant advantage of CMP
`is
`the
`relative
`insensitivity of the process to yield degradation from prior level
`defects. Finally, it has been demonstrated that the polish process for
`stud formation has an inherently larger process window and higher yield
`potential than conventional etchback techniques for forming tungsten
`studs.
`
`The key to realizing these process advantages is the ability to
`control
`oxide
`and
`tungsten
`chemical-mechanical polishing
`in
`a
`manufacturing environment. The more critical of these two operations is
`oxide CMP.
`The mean insulator thickness and tolerance across a 200-mm
`wafer must be maintained to guarantee interlevel insulator integrity and
`ensure a wide manufacturing process window at subsequent RIE via-etch
`operations.
`In addition,
`local planarization must be completely
`accomplished by oxide CMP to ensure the efficient removal of the sputtered
`liner and CVD tungsten at subsequent tungsten CMP operations. Modeling
`of the oxide CMP process is being used to predict the response of various
`pattern factors and topologies to the polish operation.
`The modeling
`
`23
`
`6
`
`

`
`been
`have
`techniques,
`along with various measurement
`results,
`incorporated into an oxide CMP control strategy that has been implemented
`in the manufacturing lines.
`
`ELECTRICAL RESULTS
`
`logic
`125-mm
`a
`from
`technology
`transfer of
`the
`in
`To aid
`manufacturing line to a 200-mm DRAM manufacturing line, a common kerf
`strategy was implemented. This kerf contains the typical interconnect
`monitors,
`including structures
`to measure contact resistance, metal
`sheet-resistance, and metal and insulator defect densities. Testing is
`done after each metal level is patterned. Nominal contact resistance and
`metal sheet-resistance values for wafers processed in the 200-mm facility
`are shown in Table 2.
`Figure 6 is a control chart from the 200-mm
`manufacturing line for a 7, 446 contact chain consisting of metal 1,
`tungsten stud and salicided N+ diffusion links. Similar results for a
`7,776 via chain consisting of metal 2, tungsten studs and metal 1 links
`are shown in Figure 7. The yield potential of this technology is further
`
`Table 2. Nominal contact resistance and metal sheet resistance.
`
`Parameter
`
`Structure
`
`Via/Contact
`Size (IJm)
`
`Nominal Value
`
`Contact Resistance
`
`M1-W-TiSi2N +
`
`Contact Resistance
`
`Contact Resistance
`
`Via Resistance
`
`Sheet Resistance
`
`M1-W-TiSi2P+
`
`M1-W-TiSi2PC
`
`M2-W-M1
`
`Metal1
`
`Sheet Resistance
`
`Metal 2/Metal 3
`
`Sheet Resistance
`
`Metal 4
`
`0.8 X 0.8
`
`0.8 X 0.8
`
`0.8 X 0.8
`
`1.2 X 1.2
`
`10
`
`~a
`c
`:::::i
`1116
`E
`.c
`0
`
`4
`
`• •
`•
`
`•
`•
`
`•
`•
`
`•
`
`•
`
`•
`
`•
`
`6
`
`~4
`:::::i
`
`Ill
`E
`.c2
`0
`
`o.4n
`
`o.4n
`
`o.4n
`
`o.2n
`
`45 mn/ o
`
`35 mn/o
`
`16 mQ/ D
`
`•
`
`2
`
`Individual Wafer Lots
`Figure 6. Control chart for Metal 1 to N +
`contact chain (sample size: 150 chains/lot).
`
`0~--~--~----.---.----.---.--~
`Individual Wafer Lots
`
`Figure 7. Control chart for Metal 2 to
`Metal 1 via chain (sample size: 150 chains/
`lot).
`
`24
`
`7
`
`

`
`including 300K
`confirmed by the fact that fully functional hardware,
`circuit ASIC logic testsites [4] and 256K SRAMs have been fabricated in
`both wafer sizes. A number of perfect SRAM chips were identified in the
`initial hardware processed in both lines.
`
`RELIABILITY
`
`In addition to yield potential, an interconnect technology must have
`excellent
`reliability performance.
`The
`layered
`titanium
`and
`aluminum-0. 5% copper wiring used in this technology exhibits excellent
`electromigration behavior. The M2 level performance for both a line and
`via electromigration stress is shown in Table 3. The reduction of T50
`associated with a via electromigration stress, as compared
`to
`line
`electromigration, is readily evident [5] This is undoubtedly due to the
`fact that there is a mass flow flux divergence at every stud to Al-Cu
`interface. The current density ground rules of studs have been derated
`to account for this effect.
`
`Table 3.
`
`Electromigration performance.
`
`Electromigration
`Test
`
`Line Current
`Density
`(106 A/cm2)
`
`Line
`
`Via
`
`1;93
`
`1.25
`
`Via Current
`Density
`(106 A/cm2)
`-
`1.04
`
`Temperature
`
`(oC)
`
`250
`
`250
`
`Tso
`
`(hr)
`
`5500
`
`210
`
`Four-level-metal testsites fabricated with this technology have also
`been
`subjected
`to
`thermal cycle,
`temperature-voltage-humidity
`and
`metal-creep reliability stressing, with no major problems observed.
`However, satisfactory performance on standard wearout tests is only one
`aspect of achieving high reliability; the final integrated process must
`also minimize process-defect-related fail modes. The approach taken in
`the design of this technology was to use process modules and integration
`which were relatively defect-insensitive.
`In addition, a number of key
`process-related defect modes have been identified and six sigma concepts
`of process control are being applied to these potential reliability fail
`modes.
`
`One of the primary reliability challenges in the integration of this
`complex multilevel structure is control of metal-creep-related voiding
`in the layered Ti and Al-Cu
`interconnect lines.
`Early development
`hardware for
`this
`technology had significant metal voiding.
`The
`experience with this phenomenon is in basic agreement with a previous
`study [6]. The process-induced voiding mechanism is quite complex with
`many contributing variables,
`including metal film composition, metal
`etch, photoresist strip, passivation, stress, and subsequent process
`temperature excursions.
`The
`final manufacturing process of
`this
`technology has been extensively modified to control creep-related metal
`
`25
`
`8
`
`

`
`Characterization data indicates that this effort has been
`voiding.
`successful. However, because of the complex multi-variable nature of the
`problem, extensive monitoring of the process is planned.
`
`SUMMARY
`
`A four-level-metal technology used for the production of high-density
`SRAM and ASIC chips has been described. The integrated process is unique
`in
`its extensive use of chemical-mechanical polishing
`for both
`planarization of interlevel oxide insulators and formation of tungsten
`studs. The fully integrated process is insensitive to several categories
`of defects and has demonstrated high yield. The ultimate reliability
`potential of the technology is also expected to be excellent.
`
`ACKNOWLEDGEMENTS
`
`The authors thank H. Cook, W. Motsiff, N. Marmillion, D. Ovitt, A.
`Puttlitz, E. Walton and G. Endicott for their contributions to process
`development, design and reliability ground rules, and process integration
`during the early development phases of this technology and for their
`continued involvment. The key contributions of W. Hill, C. Hoffman, G.
`Kerszykowski, D. Thomas and J. Kent for integration of this process into
`the 200-mm manufacturing facility are also gratefully acknowledged. The
`technical support and other contributions of R. Bombardier, R. Bleakley,
`D. Clodgo, T. Hartswick, J. Palmer, C. Pousland and P. Smith were also
`key to the success of the program.
`
`REFERENCES
`
`1. C. Kaanta, W. Cote, J. Cronin, K. Holland, P-I. Lee and T. Wright,
`"Submicron Wiring Technology with Tungsten and Planarization,"
`Proceedings of the Fifth International IEEE VMIC Conference, pp.
`21-28, June 1988.
`2. K. Beyer, W. Guthrie, S. Markarewicz, E. Mendel, W. Patrick, K. Perry,
`W. Pliskin,
`J Riseman, P. Schaible and C. Standly,
`"Chem-Mech
`Polishing Method for Producing Coplanar Metal/Insulator Films on a
`Substrate," IBM Corp., US Patent 4,944,836, July 31, 1990.
`3. D. May, M. Schadt, C-K. Hu, F. Kaufman, A. Ray, N. Mazzeo, E. Baran
`and D. Pearson, "A Two-Level Metal Fully Planarized Interconnect
`Structure Implemented on a 64Kb CMOS SRAM," Proceedings of the Sixth
`International IEEE VMIC Conference, pp. 26-32. June 1989.
`J. Petrovick, Jr., R. Taylor, A. Bertolet, A. Chu, T. Harroun, F.
`Keyser, C. LaMarche, L. Pastel, G. Richardson and B. Worth, "A 300K
`Circuit ASIC Logic Family," ISSCC Digest of Technical Papers, pp.
`88-89,- February 1990.
`5. T. Kwok, C. Tan, D. May, J. Estabil, H. Rathore and S. Basavaiah,
`"Electromigration in a Two-Level Al-Cu Interconnection with W Studs,"
`Proceedings of the Seventh International IEEE VMIC Conference, pp.
`106-112, June 1990.
`6. V. Murali, S. Sachdev, I. Banerjee, S. Casey and P. Gargini, "Metal
`Voiding Phenomenon in Aluminum and Its Alloys," Proceedings of the
`Seventh International IEEE VMIC Conference, pp. 127-132, June 1990.
`
`4.
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