Construction Analysis
`
`Samsung KM44C4000J-7
`16 Megabit DRAM
`
`Report Number: SCA 9311-300I
`
`e m i c o nductorIn
`
`dustr y
`
`®
`
`S
`
`i n c e 1964
`
`bal S
`
`rvingtheGlo
`
`e
`
`S
`
`17350 N. Hartford Drive
`Scottsdale, AZ 85255
`Phone: 602-515-9780
`Fax: 602-515-9781
`e-mail: ice@ice-corp.com
`Internet: http://www.ice-corp.com
`
`IPR2015-01087 - Ex. 1028
`Micron Technology, Inc., et al., Petitioners
`1
`
`
`
`Samsung KM44C4000J-7
`16 Megabit DRAM
`
`Report Number: SCA 9311-300I
`
`e m i c o nductorIn
`
`dustr y
`
`®
`
`S
`
`i n c e 1964
`
`bal S
`
`rvingtheGlo
`
`e
`
`S
`
`17350 N. Hartford Drive
`Scottsdale, AZ 85255
`Phone: 602-515-9780
`Fax: 602-515-9781
`e-mail: ice@ice-corp.com
`Internet: http://www.ice-corp.com
`
`IPR2015-01087 - Ex. 1028
`Micron Technology, Inc., et al., Petitioners
`1
`
`
`
` INDEX TO TEXT
`
` TITLE
`
`INTRODUCTION
`MAJOR FINDINGS
`
`TECHNOLOGY DESCRIPTION
`Assembly
`Die Process and Design
`
`ANALYSIS RESULTS I
`Assembly
`
`ANALYSIS RESULTS II
`Die Process and Design
`
`ANALYSIS PROCEDURE
`
`TABLES
`Overall Evaluation
`Package Markings
`Wirebond Strength
`Die Material Analysis (EDX and WDX)
`Horizontal Dimensions
`Vertical Dimensions
`
`
`
` PAGE
`
`1
`1
`
`2
`2 - 3
`
` 4
`
`5 - 7
`
`8
`
`9
`10
`10
`10
`11
`12
`
`- i -
`
`2
`
`
`
` INTRODUCTION
`
`This report describes a construction analysis of the Samsung KM44C4000J-7 16-megabit
`CMOS Dynamic RAM. Four samples molded in 24-pin plastic SOJ packages and date
`coded 9313 were supplied for the analysis. Analysis of the packaging and assembly is
`included.
`
` MAJOR FINDINGS
`
`Questionable Items:1
`
`• Silicon nodules occupied up to 75 percent2 of metal 2 line widths (Figure 16).
`
`Special Features:
`
`• Twin-well process with sub-micron geometries (0.3 micron poly 1 and 0.5 micron
`metal 1).
`
`• Two levels of metal, four levels of poly.
`
`• Metal 1 contacts were completely filled with aluminum (aluminum reflow).
`
`1These items present possible quality or reliability concerns. They should be discussed
`with the manufacturer to determine their possible impact on the intended application.
`
`2The seriousness depends on design margins.
`
`- 1 -
`
`3
`
`
`
` TECHNOLOGY DESCRIPTION
`
` Assembly:
`
`• 24-pin (28 pin format) plastic small-outline J-lead package (SOJ).
`
`•
`
`Iron-nickel (FeNi) leadframe.
`
`• External leads were coated with tin-lead (SnPb) solder.
`
`•
`
`Internal leadframe plating consisted of spot-plated silver (Ag) over a thin copper
`(Cu) flash. No plating was present on top of the header.
`
`• Lead-locking provisions (anchors) were present at all pins.
`
`• A dimpled header was employed.
`
`• All pins were connected.
`
`• Die attach was by silver (Ag)-epoxy.
`
`• Dicing was by the sawn method.
`
`• Wirebonding was by the thermosonic ball bond method using 1.3 mil O.D. gold wire.
`
` Die Process and Design:
`
`• Fabrication process: Selective oxidation CMOS process with twin wells in a P(?)
`substrate.
`
`• Die coat: A patterned (to clear bond pads) polyimide die coat was present to protect
`against alpha particle-induced leakage.
`
`• Overlay passivation: A layer of silicon-nitride over two layers of silicon-dioxide.
`The second layer of silicon-dioxide was multilayered.
`
`- 2 -
`
`4
`
`
`
` TECHNOLOGY DESCRIPTION (continued)
`
`• Metallization: Two levels of metal conductors were used. Metal 2 consisted of
`aluminum only. Metal 1 consisted of aluminum with a titanium-nitride cap and
`barrier. Both metal levels were defined using a dry-etch technique.
`
`•
`
`•
`
`Interlevel dielectric: Three layers of silicon-dioxide plus a filler glass (SOG) between
`interlevel glasses 2 and 3.
`
`Intermediate glass: Two layers of boron- and phosphorus-doped glass in addition to
`the various densified oxides. Intermediate glass layers (between poly 3 and
`polycide, and polycide and metal 1) had been reflowed prior to deposition of
`subsequent layers and contact cut definition.
`
`• Polysilicon: Four levels of dry-etched polysilicon were used. Poly 4 employed a
`tungsten silicide (polycide) and was used for the bit lines in the cell array and
`interconnect in the decode areas. Poly 3 (sheet) was used for the common passive
`capacitor plate and poly 2 was used for the individual active capacitor plates in the
`cell array. Poly 1 was used for all the gates on the die.
`
`• Diffusions: Standard N+ and P+ implanted source/drain diffusions formed N- and
`P-channel transistors. Transistors were formed using an LDD process with oxide
`sidewall spacers.
`
`• Wells: Twin wells in an P substrate.
`
`• Memory cells: The memory cell used an NMOS DRAM cell design consisting of a
`select gate and a stacked capacitor. Polycide formed the bit lines. Poly 1 formed the
`word lines and was "piggybacked" by metal 1. Stacked capacitors were formed by
`poly 2 pads covered by a poly 3 sheet separated by a thin oxide/nitride dielectric.
`
`• Fuses: Redundancy was implemented using polycide fuses. Laser blown fuses
`were noted on all samples. Oxide cuts were present above fuse locations and were
`then covered by the overlay passivation. No separate guardbands were found
`around the fuses.
`
`- 3 -
`
`5
`
`
`
` ANALYSIS RESULTS I
`
` Assembly
`
` Figures 1 - 7
`
`Questionable Items1: None.
`
`General Items:
`
`• Devices were packaged in 24-pin (28 pin format) plastic SOJs.
`
`• Overall package quality: Normal. No serious defects were found on the external or
`internal portions of the packages. Some small voids were noted in the plastic
`packaging material; however, overall package integrity was normal. Small gaps
`were present at the lead exits. Although they did not penetrate far into the package
`the internal plating was relatively close to the edge of the package. This could be
`monitored to ensure silver does not become exposed (and subject to dendrite
`growth).
`
`• Wirebonding: Thermosonic ball bond method using 1.3 mil O.D. gold wire. No
`bond lifts occurred and bond pull strengths were good (see page 10). Normal
`intermetallic was present at ball bonds. Wire spacing and bond placement was good.
`
`• Die attach: A silver-epoxy compound was used. Die attach quality was good with
`no voids observed.
`
`• Die dicing: Die separation was by sawing (90+ percent) with normal quality
`workmanship.
`
`1These items present possible quality or reliability concerns. They should be discussed
`with the manufacturer to determine their possible impact on the intended application.
`
`- 4 -
`
`6
`
`
`
` ANALYSIS RESULTS II
`
` Die Process and Design
`
` Figures 8 - 39
`
`Questionable Items:1
`
`• Silicon nodules occupied up to 75 percent of metal 2 line widths (Figure 16).
`
`Special Features:
`
`• Twin-well process with sub-micron geometries (0.3 micron poly 1 and 0.5 micron
`metal 1).
`
`• Two levels of metal, four levels of poly.
`
`• Metal 1 contacts were completely filled with aluminum(aluminum reflow).
`
`General Items:
`
`• Fabrication process: Selective oxidation CMOS process employing twin-wells in an
`N substrate.
`
`• Design and layout: Die layout was clean and efficient. Alignment was good at all
`levels.
`
`• Die coat: A patterned (to clear bond pads) polyimide die coat was present to protect
`against alpha particle-induced leakage. Coverage was good.
`
`• Die surface defects: No damage, process defects, or contamination was found.
`
`• Overlay passivation: A layer of silicon-nitride over two layers of silicon-dioxide.
`Overlay integrity test indicated defect-free passivation. Edge seal was good.
`
`1These items present possible quality or reliability concerns. They should be discussed
`with the manufacturer to determine their possible impact on the intended application.
`
`- 5 -
`
`7
`
`
`
` ANALYSIS RESULTS II (continued)
`
`• Metallization: Metal 2 consisted of silicon-doped aluminum only. Metal 1 consisted
`of undoped aluminum with a titanium-nitride cap and barrier.
`
`• Metal patterning: Both metal layers were defined by dry-etch techniques. Definition
`was very good and no significant overetch was present.
`
`• Metal defects: Some notches were noted in the metal 2 (Figure 15). No notches
`occupied more than 30 percent of the line width and the entire metal thickness. The
`condition present is not of real concern but should possibly be monitored. Silicon
`nodules noted following removal of metal 2 occupied up to 75 percent of the
`line width. Silicon nodules of 50 percent or greater will lead to current
`crowding, which may lead to electromigration and is thus of concern. No
`silicon nodules were noted on the barrier following the removal of aluminum 1.
`
`• Metal step coverage: Metal 2 thinning up to 65 percent was noted at vias. MIL-
`STD-883D allows up to 70 percent thinning for contacts of this size. The metal 1
`cap was not present in vias (metal 2-to-metal 1), thus was removed during via cuts.
`All metal 1 contacts were completely filled with aluminum providing a very good
`current path. Integrity of the metal 1 barrier was good.
`
`• Contacts: Contact cuts were probably defined by a two-step process (dry etch
`followed by wet etch). No over-etching of the contacts was present.
`
`•
`
`•
`
`Interlevel dielectric: The dielectric between metal 1 and metal 2 consisted of three
`layers of silicon-dioxide. Interlevel oxides 2 and 3 were separated by a filler (SOG)
`glass. No problems were found.
`
`Intermediate glass: Two layers of boron- and phosphorus-doped glass in addition to
`the various densified oxides. Glass layer 2 (between polycide and metal 1) and 1
`(between poly 3 and polycide) had been reflowed prior to deposition of subsequent
`layers and contact cuts.
`
`- 6 -
`
`8
`
`
`
` ANALYSIS RESULTS II (continued)
`
`• Polysilicon: Four levels of polysilicon were used. Poly 4 employed a tungsten silicide
`(polycide) and was used to form the bit lines in the array and as interconnect in the decode
`areas. Poly 3 (sheet) was used to form the common passive plate of the capacitors and poly
`2 was used to form the individual active capacitor plates. Poly 1 formed all gates on the die.
`Definition of all poly layers was by a dry-etch technique of good quality. No stringers or
`spurs were noted.
`
`•
`
`Isolation: Local oxide (LOCOS). No problems were present at the birdsbeak or elsewhere.
`
`• Diffusions: Standard implanted N+ and P+ diffusions were used for sources and drains.
`No problems were found. Oxide sidewall spacers were used to reduce internal capacitance
`and hot-carrier effects (LDD process).
`
`• Wells: Twin-wells were employed. Definition was normal.
`
`• Epi: No epi layer was employed. No defects were found in the substrate silicon.
`
`• Fuses: Redundancy was implemented by laser blowing polycide fuses. Blown fuses were
`present on all samples. Oxide cuts were present above fuse locations and were covered by
`the passivation.
`
`• Memory cells: A stacked capacitor DRAM cell design was employed. Cell pitch was 1.4 x
`2.8 microns (3.9 microns2). Polycide formed the bit lines, poly 3 and poly 2 formed the
`capacitor plates, and poly 1 formed the word lines and was "piggybacked" by metal 1. Poly
`3 underlaps the poly 2 capacitor plates for increased area (Figure 38).
`
`Special Features:
`
`• Samples 1 and 2 were subjected to ESD sensitivity tests. Results revealed that all
`pin combinations passed – 4000V.
`
`• Samples 3 and 4 were subjected to latch-up sensitivity tests. Pins were tested from -
`200ma to 200ma. Tests revealed no pins latched-up on either sample.
`
`- 7 -
`
`9
`
`
`
` PROCEDURE
`
`The devices were subjected to the following analysis procedures.
`
`External inspection
`
`ESD sensitivity
`
`Latch-up sensitivity
`
`X-ray
`
`Package section and material (EDX)
`
`Decapsulation
`
`Internal optical inspection
`
`SEM inspection of assembly features and passivation
`
`Passivation integrity test
`
`Wirepull test
`
`Passivation removal
`
`SEM inspection of metal 2
`
`Metal 2 removal and inspect for silicon nodules and vias
`
`Delayer to metal 1 and inspect
`
`Metal 1 removal and inspect barrier
`
`Delayer to poly/substrate and inspect poly structures and die surface
`Die sectioning (90(cid:176) for SEM)*
`
`Measure horizontal dimensions
`
`Measure vertical dimensions
`
`Die material analysis (EDX and WDX)
`
`*Delineation of cross sections is by silicon etch unless otherwise indicated.
`
`- 8 -
`
`10
`
`
`
` OVERALL QUALITY EVALUATION: Overall Rating: Normal
`
` DETAIL OF EVALUATION
`
`Package integrity
`Package markings
`Die placement
`Die attach quality
`Wire spacing
`Wirebond placement
`Wirebond quality
`Dicing quality
`Wirebond method
`
`Die attach method
`Dicing method
`
`Die surface integrity:
`Tool marks (absence)
`Particles (absence)
`Contamination (absence)
`Process defects (absence)
`General workmanship
`Passivation integrity
`Metal definition
`Metal integrity
`Contact coverage
`Contact registration
`
`N
`G
`G
`G
`G
`G
`G
`G
`Thermosonic ball bonds using 1.3
`mil gold wire.
`Silver-epoxy
`Sawing (90+ percent)
`
`G
`G
`G
`G
`G
`G
`G
`NP1
`G
`G
`
`1Silicon nodules occupied up to 75 percent of metal 2 line widths.
`
`G = Good, P = Poor, N = Normal, NP = Normal/Poor
`
`- 9 -
`
`11
`
`
`
` PACKAGE MARKINGS
`
` TOP
`
`(Logo) KOREA
`313
`KM44C4000J-7
`
` BOTTOM
`
`4YL
`C03ZAA
`
` WIREBOND STRENGTH
`
`Wire material: 1.3 mil O.D. gold
`Die pad material: aluminum
`Material at package lands: silver
`
`# of wires tested:
`Bond lifts:
`Force to break - high:
`- low:
`- avg.:
`- std. dev.:
`
`13
` 0
`18.0g
`11.0g
`14.5g
` 2.4
`
` DIE MATERIAL ANALYSIS (EDX and WDX)
`
`Passivation:
`
`Metal 2:
`
`Interlevel dielectric:
`
`Metal 1:
`
`Intermediate glass:
`
`Silicon-nitride over two layers of silicon-
`dioxide.
`
`Silicon-doped aluminum.
`
`Three levels of silicon-dioxide with a filler
`glass between layers 2 and 3.
`
`Undoped aluminum with a titanium-nitride
`cap and barrier.
`
`CVD glass containing an average of 5.2 wt.
`percent boron and 3.9 wt. percent
`phosphorus over various densified oxides.
`
`Polycide:
`
`Tungsten silicide.
`
`- 10 -
`
`12
`
`
`
` HORIZONTAL DIMENSIONS
`
`Die size:
`
`Die area:
`
`Min pad size:
`
`Min pad window:
`
`Min pad space:
`
`Min metal 2 width:
`
`Min metal 2 space:
`
`Min metal 1 width:
`
`Min metal 1 space:
`
`Min via (metal 2-to-metal 1):
`
`Min contact:
`
`Min polycide width:
`
`Min polycide space:
`
`Min poly 2 space:
`
`Min poly 1 width:
`
`Min poly 1 space:
`
`Min gate length (N-channel):
`
` (P-channel):
`
`Cell pitch:
`
`Cell size:
`
`5.8 x 16.6 mm (230 x 656 mils)
`
`97 mm2 (150,880 mils2)
`
`0.11 x 0.12 mm (4.5 x 4.7 mils)
`
`0.1 x 0.11 mm (3.8 x 4.2 mils)
`
`0.12 mm (4.7 mils)
`
`1.3 microns
`
`1.2 microns
`
`0.5 micron
`
`0.7 micron
`
`1.2 microns
`
`0.7 micron
`
`0.5 micron
`
`0.65 micron
`
`0.5 micron
`
`0.3 micron
`
`0.5 micron
`
`0.5 micron
`
`0.8 micron
`
`3.64 microns2
`
`1.4 x 2.6 microns
`
`- 11 -
`
`13
`
`
`
` VERTICAL DIMENSIONS
`
`Die thickness:
`
` Layers:
`
`Die coat:
`Passivation 3:
`Passivation 2:
`Passivation 1:
`Metal 2 - aluminum:
`Interlevel dielectric - glass 3:
` - glass 2:
` - glass 1:
`
`Metal 1 - cap:
`- aluminum:
`- barrier:
`Intermediate glass 2:
`Polycide - silicide:
` - poly 4:
`Intermediate glass 1:
`Oxide on poly 3:
`Poly 3:
`Capacitor dielectric:
`Poly 2:
`Interpoly oxide - total:
`
`- nitride:
`Poly 1:
`Local oxide (under poly 1):
`Oxide on N+:
`Oxide on P+:
`N+ source/drain:
`P+ source/drain:
`N- well:*
`
`13.5 mils (0.3 mm)
`
`9.5 microns
`0.55 micron
`0.3 micron
`0.1 micron
`0.9 micron
`0.4 micron
`0.4 micron
`0.08 micron (approx.)
`0.04 micron (approx.)
`0.55 micron
`0.15 micron
`0.5 micron
`0.2 micron
`0.05 micron (approx.)
`0.2 micron
`0.1 micron
`0.1 micron
`150 Å (approx.)
`0.15 micron
`0.35 micron
`0.04 micron (approx.)
`0.2 micron
`0.3 micron
`0.08 micron (approx.)
`0.06 micron (approx.)
`0.2 micron
`0.3 micron
`4.5 microns
`
`*It was not possible to determine well and substrate polarity with certainty.
`
`- 12 -
`
`14
`
`
`
` INDEX TO FIGURES
`
`PACKAGING AND ASSEMBLY
`
`DIE LAYOUT AND IDENTIFICATION
`
`Figures 1 - 7
`
`Figures 8 - 9
`
`PHYSICAL DIE STRUCTURES
`
`Figures 10 - 38
`
`COLOR DRAWING OF GENERAL DEVICE STRUCTURE
`
`Figure 32
`
`FUSES
`
`MEMORY CELL STRUCTURES
`
`CIRCUIT LAYOUTS
`
`Figures 33 - 34
`
`Figures 35 - 38
`
`Figure 39
`
`- ii -
`
`15
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`24
`23
`22
`21
`20
`19
`
`18
`17
`16
`15
`14
`13
`
`VSS
`DQ4
`DQ3
`CAS
`OE
`A9
`
`A8
`A7
`A6
`A5
`A4
`VSS
`
`1 2 3 4 5 6
`
`7 8 9 1
`
`0
`11
`12
`
`VCC
`DQ1
`DQ2
`W
`RAS
`A11
`
`A10
`A0
`A1
`A2
`A3
`VCC
`
`Figure 1. Package photograph and pinout diagram of the Samsung KM44C4000. Mag. 5x.
`
`16
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`PIN 1
`
`Figure 2. Topological and side x-ray views. Mag. 6x.
`
`17
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`Figure 3. Section view of the package illustrating general construction. Mag. 17x.
`
`HEADER
`
`DIE
`
`LEADFRAME
`
`PLASTIC PACKAGE
`
`18
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`J-LEAD
`
`DIE
`
`PLASTIC PACKAGE
`
`Mag. 35x
`
`SMALL GAP
`
`PLASTIC PACKAGE
`
`SnPb TINNING
`
`FeNi LEADFRAME
`
`Ag PLATING
`
`Mag. 200x
`
`Figure 4. Section views illustrating lead forming and lead exit.
`
`19
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`DIE
`
`HEADER
`
`LEADFRAME
`
`DIE
`
`Ag-EPOXY
`
`FeNi HEADER
`
`Ag PLATING
`
`Mag. 100x
`
`Mag. 250x
`
`DIE COAT
`
`DIE
`
`Mag. 600x
`
`Figure 5. Section views illustrating dicing, die attach and die coat.
`
`20
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`Mag. 170x
`
`Mag. 1000x
`
`Figure 6. SEM views of a die corner and edge seal. 60°.
`
`21
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`Mag. 550x, 60°
`
`Mag. 700x, 60°
`
`Mag. 800x
`
`Au
`
`INTERMETALLIC
`
`DIE
`
`Figure 7. SEM and section views of typical wirebonds.
`
`22
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`PIN 1
`
`Figure 8. Portion of the Samsung KM44C4000 die photograph. Mag. 30x.
`
`23
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`Figure 8a. Remaining portion of the Samsung KM44C4000 die photograph. Mag. 30x.
`
`24
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`Figure 9. Die identification markings. Mag. 800x.
`
`25
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`Mag. 4000x
`
`Mag. 13,500x
`
`Figure 10. SEM views of general passivation coverage. 60°.
`
`26
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`PASSIVATION 3
`
`METAL 2
`
`POLY 1
`
`METAL 1
`
`N+ S/D
`
`Mag. 12,000x
`
`PASSIVATION 2
`
`METAL 2
`
`PASSIVATION 1
`
`POLYCIDE
`
`METAL 1
`
`POLY 1
`
`LOCAL OXIDE
`
`Mag. 15,000x
`
`Figure 11. SEM section views illustrating general device structure.
`
`27
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`PASSIVATION 3
`
`PASSIVATION 2
`
`METAL 2
`
`PASSIVATION 1
`
`Figure 12. SEM section view of a metal 2 line profile. Mag. 25,000x.
`
`Figure 13. Topological SEM views of metal 2 patterning. Mag. 3500x, 0°.
`
`28
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`Mag. 4500x
`
`Mag. 15,000x
`
`Figure 14. SEM views of general metal 2 integrity. 60°.
`
`29
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`Mag. 8000x, 60°
`
`Mag. 10,000x, 0°
`
`Figure 15. SEM views illustrating notches in the metal 2.
`
`30
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`Mag. 8000x
`
`1.3µ LINE
`WIDTH
`
`1.0µ SILICON
`NODULE
`
`Figure 16. Topological SEM views of silicon nodules (following removal of metal 2). 0°.
`
`Mag. 20,000x
`
`31
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`PASSIVATION 3
`
`PASSIVATION 2
`
`PASSIVATION 1
`
`INTERLEVEL
`DIELECTRIC
`
`METAL 2
`
`METAL 1
`
`65% THINNING
`
`Mag. 17,500x
`
`INTERLEVEL DIELECTRIC
`
`ETCHED METAL 1
`
`Si
`
`Mag. 27,000x, 45°
`
`Figure 17. SEM views of typical vias.
`
`32
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`TiN CAP
`
`33
`44
`ALUMINUM 1
`22
`44
`11
`TiN BARRIER
`
`SOG
`
`METAL 1
`
`STAINING
`ARTIFACT
`
`Figure 18. SEM section view of metal 1 line profiles. Mag. 40,000x.
`
`Figure 19. Topological SEM views of metal 1 patterning. Mag. 4000x, 0°.
`
`33
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`Mag. 7000x
`
`TiN CAP
`
`ALUMINUM 1
`
`TiN BARRIER
`
`Mag. 25,000x
`
`Figure 20. SEM views of general metal 1 integrity. 60°.
`
`34
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`Mag. 8000x
`
`TiN BARRIER
`
`Mag. 25,000x
`
`Figure 21. SEM views of general barrier coverage. 50°.
`
`35
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`TiN BARRIER
`
`ALUMINUM 1
`
`TiN CAP
`
`INTERMEDIATE
`GLASS 2
`
`POLYCIDE
`
`metal-to-polycide
`
`TiN CAP
`
`ALUMINUM 1
`
`TiN BARRIER
`
`POLY 1
`
`LOCAL OXIDE
`
`metal 1-to-poly 1
`
`Figure 22. SEM section views of metal 1-to-poly contacts. Mag. 35,000x.
`
`36
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`TiN CAP
`
`TiN BARRIER
`
`ALUMINUM 1
`
`OXIDE ON N+
`
`N+
`
`metal 1-to-N+
`
`TiN CAP
`
`ALUMINUM 1
`
`TiN BARRIER
`
`POLY 1
`
`P+
`
`metal 1-to-P+
`
`Figure 23. SEM section views of metal 1-to-diffusion contacts. Mag. 35,000x.
`
`37
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`Figure 24. SEM view of general polycide coverage. Mag. 15,000x, 60°.
`
`W SILICIDE
`
`INTERMEDIATE
`GLASS 1
`
`POLY 4
`
`N+
`
`Figure 25. SEM section view of a polycide-to-N+ contact. Mag. 50,000x.
`
`38
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`POLYCIDE
`
`INTERMEDIATE
`GLASS 1
`
`POLY 3
`
`NITRIDE
`
`OXIDE ON
`POLY 3
`
`POLY 1
`
`polycide-to-poly 3
`
`POLYCIDE
`
`INTERMEDIATE
`GLASS 1
`
`POLY 1
`
`LOCAL OXIDE
`
`polycide-to-poly 1
`
`Figure 26. SEM section views of various polycide contacts. Mag. 50,000x.
`
`39
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`Mag. 3000x
`
`Mag. 5700x
`
`Figure 27. Topological SEM views of poly 1 patterning. 0°.
`
`40
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`Mag. 6500x
`
`Mag. 25,000x
`
`Figure 28. SEM views of general poly 1 coverage. 60°.
`
`41
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`OXIDE ON P+
`
`P+ S/D
`
`POLY 1
`
`GATE OXIDE
`
`P-channel,
`Mag. 35,000x
`
`OXIDE ON N+
`
`N+ S/D
`
`N-channel,
`Mag. 50,000x
`
`POLY 1
`
`GATE OXIDE
`
`POLYCIDE
`
`glass etch,
`Mag. 40,000x
`
`SIDEWALL
`SPACER
`
`POLY 1
`
`GATE OXIDE
`
`Figure 29. SEM section views of typical transistors.
`
`42
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`POLYCIDE
`
`POLY 1
`
`LOCAL OXIDE
`
`GATE OXIDE
`
`Figure 30. SEM section view of a local oxide birdsbeak. Mag. 50,000x.
`
`POLYCIDE
`
`FIELD OXIDE
`
`DIP
`
`Mag. 30,000x
`
`Mag. 1600x
`
`P-WELL
`
`Figure 31. Section views illustrating the well structure.
`
`43
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`PASSIVATION 1
`
`INTERLEVEL DIELECTRIC
`
`CAP
`
`BARRIER
`
`FILLER GLASS
`
`SILICIDE
`
`POLY 4
`
`PASSIVATION 3
`
`PASSIVATION 2
`
`ALUMINUM 1
`
`(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)
`
`ALUMINUM 2
`
`(cid:0)(cid:0)(cid:0)
`(cid:0)(cid:0)(cid:0)
`
`INTERMEDIATE GLASS 2
`
`INTERMEDIATE GLASS 1
`
`LOCAL OXIDE
`
`POLY 1
`
`N+ S/D
`
`OXIDE ON N+
`
`P-WELL
`
`N-WELL
`
`OXIDE ON P+
`
`P+ S/D
`
`
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`
`
`
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`
`
`
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`
`
`
`Orange = Nitride, Blue = Metal, Yellow = Oxide, Green = Poly,
`Red = Diffusion, and Gray = Substrate
`
`Figure 32. Color cross section drawing illustrating device structure.
`
`44
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`BLOWN
`
`INTACT
`
`intact
`
`passivation removed
`
`Figure 33. Topological SEM views of fuses. Mag. 8000x, 0°.
`
`45
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`intact
`
`BLOWN
`
`INTACT
`
`passivation removed
`
`Figure 34. Perspective SEM views of fuses. Mag. 6500x, 60°.
`
`46
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`“PIGGYBACK” WORD LINES
`
`metal 1
`
`BIT LINE
`
`BIT LINE
`
`Figure 35. Topological SEM views of DRAM cells. Mag. 15,000x, 0°.
`
`polycide
`
`47
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`BIT LINE CONTACT
`
`Q
`
`C
`
`MEMORY
`ENABLE
`
`unlayered, Mag. 15,000x, 0°
`
`WORD
`
`BIT
`
`Q
`
`C
`
`MEMORY
`ENABLE
`
`Figure 35a. Topological SEM view of DRAM cells along with the schematic.
`
`48
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`METAL 1 “PIGGYBACK” WORD LINES
`
`POLYCIDE
`BIT LINES
`
`metal 1
`
`polycide
`
`unlayered
`
`Figure 36. Perspective SEM views of the cell array. Mag. 8500x, 60°.
`
`49
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`METAL 1 “PIGGYBACK” WORD LINES
`
`POLY 2
`CAPACITOR PLATE
`
`POLY 3
`CAPACITOR SHEET
`
`POLYCIDE BIT LINE
`
`Mag. 15,000x
`
`POLY 1
`SELECT
`GATE
`
`POLY 1 WORD LINES
`
`POLYCIDE
`
`POLY 3
`
`POLY 1
`
`POLY 2
`N+ S/D
`
`N+ S/D
`
`W SILICIDE
`
`Mag. 30,000x
`
`Mag. 40,000x
`
`POLY 4
`
`POLY 1
`
`N+ S/D
`
`Figure 37. SEM section views of DRAM cells (parallel to bit lines).
`
`50
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`POLY 3
`
`POLY 2
`
`POLY 1
`
`Mag. 45,000x
`
`N+ S/D
`
`N+ S/D
`
`GATE OXIDE
`
`NITRIDE
`
`Mag. 50,000x
`
`CAPACITOR DIELECTRIC
`
`POLY 3
`
`POLY 2
`
`N+ S/D
`
`POLY 3
`
`glass etch,
`Mag. 50,000x
`
`NITRIDE
`
`POLY 1
`
`POLY 2
`
`NITRIDE
`
`Figure 38. Detail section views of DRAM cells.
`
`51
`
`
`
`Samsung KM44C4000
`
`Integrated Circuit Engineering Corporation
`
`input protection,
`intact,
`Mag. 500x
`
`intact,
`Mag. 800x
`
`metal 1,
`Mag. 800x
`
`Figure 39. Optical views illustrating typical input protection and circuit layout.
`
`52
`
`
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
