United States Patent [191
`Prall et a].
`
`[54] REDUCED PITCH LASER REDUNDANCY
`FUSE BANK STRUCTURE
`
`[75] Inventors: Kirk Prall; Tod S. Stone; Paul S.
`Zagar, all of Boise, Id.
`
`[73] Assignee: Micron Technology, Inc., Boise, Id.
`'
`The term of this patent shall not extend
`beyond the expiration date of Pat. No.
`5,636,172.
`
`[*1 Notice:
`
`[21] Appl. No.: 831,389
`[22] Filed:
`Apr. 1, 1997
`
`Related US- Application Data
`
`[62] Division of Ser. No. 577,468, Dec. 22, 1995, Pat No.
`5,636,172.
`[5 1] Int. Cl.6 ........................... .. H01L 27/10; H01L 29/00
`[52] US. Cl. ...................... .. 2571529; 257/209; 365/225.7
`
`US005747869A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,747,869
`*May 5, 1998
`
`5,264,725 11/1993 Mullarkey et a1. ................... .. 257/665
`5,281,868
`1/1994 Morgan ................................. .. 307/441
`5,424,672
`6/1995 Cowles et a1.
`..... .. 327/525
`5,636,172
`6/1997 Prall et a1. ......................... .. 365/2257
`
`Doc
`FOREIGN P
`0720229 7/1996 European Pat. 0E. .
`59.151454 3/1934 japan_
`61-123544 6/1936 Japan.
`05251563 9/1993v Japan .
`06310603 11/1994 Japan .
`
`8
`
`Primary Examiner-Valencia Martin Wallace
`Attome); Agent, or Firm-Schwegman, Lundberg,
`Woessner 8: Kluth, RA.
`
`[57]
`
`ABSTRACT
`
`A ‘gll?fm?w 1°‘ 3 13571;“? '?‘nkis 2155mm ‘fvhcrgin 2g
`*“1
`e SP“? ‘8 mm 6 cm.“ y “S6 ' "5“ ° gm u“. .
`wldth and vanable con?guration are placed so as to 1mm
`[58] Field of Search ................................... .. 257/209, 529;
`.
`th
`.
`b
`.
`.
`365/2253 me e average distance etween fuses and maximize fuse
`density. Alternatively, a common source is added to a
`standard laser fuse structure such that it intersects the fuses
`and the number of available fuses is doubled.
`
`[56]
`
`nefemnc? Cited
`
`U.S. PATENT DOCUMENTS
`
`5,200,652
`
`4/1993 Lee ........................................ .. 307/465
`
`11 Claims, 3 Drawing Sheets
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`
`IPR2015-01087 - Ex. 1025
`Micron Technology, Inc., et al., Petitioners
`1
`
`

`

`US. Patent
`US. Patent
`
`May s, 1998
`May 5, 1998
`
`Sheet 1 of 3
`Sheet 1 of 3
`1320
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`5,747,869
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`US. Patent
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`May s, 1998
`
`Sheet 2 of 3
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`5,747,869
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`

`US. Patent
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`May 5, 1998
`
`Sheet 3 of 3
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`5,747,869
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`

`1
`REDUCED PITCH LASER REDUNDANCY
`FUSE BANK STRUCTURE
`
`5,747,869
`
`This application is a divisional of US. patent application
`Ser. No. 08/577,468, ?led Dec. 22, 1995. US. Pat. No.
`5,636,172.
`
`TECHNICAL FIELD OF THE INVENTION
`The present invention relates generally to integrated cir
`cuits and in particular to a fuse bank structure used in
`integrated circuits.
`
`BACKGROUND OF THE INVENTION
`An integrated circuit is a complete electronic circuit,
`containing transistors, diodes, resistors, and capacitors,
`along with their interconnecting electrical conductors, con
`tained entirely within a single chip of silicon. Integrated
`circuits continue to decrease in size, and the circuits they
`contain continue to increase in complexity. This increases
`the opportunity for defective chips resulting from a failed
`element or a defective conductor. The complexity of these
`devices and the need to interconnect the circuits create very
`narrow performance tolerances. One way these needs have
`been met is to manufacture fuses into the device. Fuses can
`be opened to isolate defective areas and allow the rest of the
`circuit to be used. Fuses can also be used to trim a circuit,
`enable a particular mode, or enable or disable different
`segments of the circuit. By using ?rses integrated circuit
`manufacturers are able to reduce the amount of semicon
`ductor scrap. The continuous drive to reduce the overall size
`of integrated circuits creates a need to design fuses and other
`
`elements of integrated circuits in such a way as to the space they require.
`
`20
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`tolerances, as well as the requirements for a large passiva
`tion opening, limit the length of the fuse. Currently the
`constraints dictated by the laser repair requirements limit the
`fuse pitch to about 3 microns. The demand for increasing
`numbers of fuses combined with the ?xed pitch limitation
`create a need for improvements in the laser fuses.
`For the reasons stated above, and for other reasons stated
`below which will become apparent to those skilled in the art
`upon reading and understanding the present speci?cation,
`there is a need in the art for a design which provides an
`increased density of laser fuses.
`SUMMARY OF THE INVENTION
`The above mentioned problems with increasing the num
`ber of fuses in a memory device are addressed by the present
`invention which will be understood bad reading and study
`ing the following speci?cation. A design embodying a more
`e?icient fuse shape is described which allows placement of
`more fuses in the same amount of physical space.
`According to one embodiment of the present invention, an
`integrated circuit laser fuse system is provided, comprising
`a plurality of laser fuse banks. Each laser fuse bank com
`prises three fuses. One of the fuses is a center fuse having
`a narrow end, a wide end, and a common centerline. Another
`of the fuses is a ?rst outer fuse having a narrow end and a
`wide end, located adjacent to the center fuse such that the
`narrow end of the ?rst outer fuse is adjacent to the narrow
`' end of the center fuse and the wide end of the ?rst outer fuse
`is adjacent to the wide end of the center fuse, the wide end
`of the ?rst outer fuse is laterally offset from the narrow end
`of the ?rst outer fuse. Another fuse of the fuse bank is a
`second outer fuse having a narrow end and a wide end,
`located adjacent to the center fuse and on the side of the
`center fuse opposite the ?rst outer fuse such that the narrow
`end of the second outer fuse is adjacent to the narrow end of
`the center fuse and the wide end of the second outer fuse is
`adjacent to the wide end of the center fuse, and the wide end
`of the second outer fuse is laterally offset from the narrow
`end of the second outer fuse.
`In one embodiment of the present invention the wide end
`of the ?rst outa' fuse is laterally offset from its narrow end
`in an outwardly direction away from the center fuse and the
`wide end of the second outer fuse is laterally offset from its
`narrow end in an outwardly direction away from the center
`fuse. In another embodiment the plurality of laser fuse banks
`comprise a ?rst laser fuse bank and a second laser fuse bank
`positioned such that the second laser fuse bank is adjacent to
`the ?rst laser fuse bank, and the second laser fuse bank is
`rotated one hundred eighty (180) degrees from the ?rst laser
`fuse bank. In yet anotha' embodiment the plurality of laser
`fuse banks are polysilicon fabricated on an integrated circuit.
`According to another embodiment of the present inven
`tion the plurality of laser fuse banks are fabricated in a
`dynamic random access memory (DRAM). The DRAM
`comprises, in addition to the laser fuse banks, a plurality of
`primary memory cells and a plurality of redundant memory
`cells. The DRAM ftn'ther includes a redundant enable circuit
`comprising a latch circuit coupled to one of the fuses of the
`plurality of laser fuse banks and a comparator circuit con
`nected to the latch circuit and a plurality of external address
`inputs.
`.
`Yet another embodiment of the invention is an integrated
`circuit memory comprising an array of primary memory
`cells arranged in rows and columns, a plurality of redundant
`memory cells, and a plurality of laser fuse banks.
`In yet another embodiment of the present invention, an
`integrated laser fuse system is provided, comprising a plu
`
`Another way to reduce semiconductor scrap is to provide
`redundant elements on integrated circuits. If a primary
`element is defective a redundant element can be substituted
`for that defective element. One example of an integrated
`circuit device which uses redundant elements is electronic
`memory. Typical memory circuits comprise millions of
`equivalent memory cells arranged in addressable rows and
`columns. By providing redundant elements, defective
`‘memory cells can be replaced. Because the individual pri
`mary memory cells of a memory are separately addressable,
`replacing a defective cell typically comprises opening fuse
`type circuits to ‘program’ a redundant cell to respond to the
`address of the defective primary cell. This process is very
`e?ective for permanently replacing defective primary
`memory cells.
`Circuit designers continuously strive to achieve higher
`population capacities without a corresponding increase in
`physical size. Reducing the size of individual elements in
`integrated circuits is one way in which available die real
`estate is maximized. For example, as memory density
`increases the number of fuses needed for redundancy in a
`given memory device also increases. A 256M DRAM is
`expected to have more than 10,000 laser fuses. Most com
`ponents of the memory devices can be scaled to meet the
`space restrictions resulting from the higher densities.
`However, laser fuses used to implement redundancy can not
`be scaled due to mechanical restrictions related to current
`laser technology. Fuse width must be kept large enough to
`cover the laser spot so that the fuse can absorb a large
`quantity of heat. In addition, the fuse-to-fuse space must be
`kept large enough to allow for mechanical laser alignment
`tolerances and to prevent unintentional programming of a
`fuse adjacent to an exploding fuse. These laser alignment
`
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`5,747,869
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`3
`rality of substantially straight laser fuses, each one of the
`plurality of substantially straight laser fuses being located
`adjacent to and parallel with remaining ones of the plurality
`of substantially straight laser fuses, and a common ground
`connection interconnecting the rnidpoints of the plurality of
`laser fuses. In yet another embodiment the plurality of laser
`fuse banks are polysilicon fabricated on an integrated circuit.
`According to another embodiment of the present invention
`the integrated laser fuse system is fabricated in a dynamic
`random access memory (DRAM) comprising the laser fuse
`system, a plurality of primary memory cells, a plurality of
`redundant memory cells, a redundant enable circuit com
`prising a latch circuit coupled to one of the fuses of the
`integrated laser fuse system, and a comparator circuit con
`nected to the latch circuit and a plurality of external address
`inputs. Another embodiment of the invention is an integrated
`circuit memory comprising an array of primary memory
`cells arranged in rows and,columns. a plurality of redundant
`memory cells, and the integrated laser fuse system.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1A is a block diagram of an integrated circuit laser
`fuse bank as disclosed in one embodiment of the present
`invention;
`FIG. 1B is a block diagram showing the relative posi
`tioning of a plurality of integrated circuit laser fuse banks as
`disclosed in one embodiment of the invention;
`FIG. 2 is block diagram of a'laser fuse bank as known in
`the art.
`FIG. 3 is a block diagram of a common source laser fuse
`bank as disclosed in one embodiment of the present inven
`tion;
`FIG. 4 is block diagram of a conventional DRAM device;
`and
`FIG. 5 is block diagram of a conventional fuse circuit.
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`spacing of the narrow sections are set by the minimum
`spacing and conductor design rules, and the wider sections
`by the laser fuse spacing and width design rules. The central
`fuse is comprised of a narrow and a wide section 102a, 102k
`which are connected end-to-end and have a common center
`line 100. The wide section of the left and right fuses 101b,
`103b are connected to the narrow section of the respective
`‘fuses 101a, 103a, but are laterally offset from the narrows
`section a distance determined by laser fuse spacing rules.
`Afuse set is created by placing a left fuse, a central fuse,
`and a right fuse laterally parallel such that the narrow
`sections 101a, 102a, 1030 are adjacent and separated by the
`distance speci?ed in the minimum spacing and conductor
`design rules. In one embodiment the minimum spacing and
`conductor design rules specify a pitch of 1.25 p and a width
`of 0.5u. The wide sections 101b, 102b, 103b are adjacent
`and separated by the distance speci?ed in the laser fuse
`spacing and width design rules. FIG. 1B shows how each
`succeeding fuse set is rotated 180° and placed laterally
`parallel to the preceding fuse set such that the adjacent fuses
`of each set 103, 103' are separated by the distance speci?ed
`by the laser fuse spacing and width design rules. This pattern
`is repeated to ?ll the available physical space. The fuses
`described in this embodiment are preferably constructed of
`polysilicon, fabricated on the top surface of an integrated
`circuit, and are programmed or “opened” by using a laser to
`evaporate a portion of the polysilicon. The fuse, therefore,
`normally has a conductive path from one end to the other. By
`removing a portion of the fuse, the conductive path can be
`opened.
`Another embodiment of the invention is a fuse structure
`incorporating a common source. FIG. 2 shows the conven
`tional method wherein uniform-width fuses 201-204 are
`positioned parallel to one another using the laser fuse
`spacing and width design rules. There is a common ground
`210 on one end of the fuses. The other end of each fuse is
`connected to a fuse circuit, an example of which is discussed
`below. FIG. 3 illustrates the positioning, according to the
`present invention, of a common ground 210 perpendicular to
`the uniform-width fuses 201-204 and intersecting each of
`the fuses at their midpoint. Both ends of each fuse are
`connected to a fuse circuit. As can be seen, implementation
`of this embodiment doubles the number of available fuses
`without increasing the space requirements.
`One example of how a semiconductor device employs
`fuses Such as those disclosed by the invention is shown in
`FIG. 4. The DRAM 400 of FIG. 4 includes a DRAM array
`402 which can be accessed by a microprocessor 404 through
`input/output connections including address lines 406. The
`DRAM array includes rows and columns of randomly
`addressable memory registers. The DRAM is accessed
`through address bus 406, row and column address strobe
`signals RAS* and CAS*, write enable signal WE", an output
`enable signal OE* and by using other conventional control
`signals (not shown) which are known to one skilled in the
`art Row address latch/buffer 408 and row decoder 410
`receive and decode a row address from a row address signal
`provided on address lines, and address a corresponding row
`of the DRAM array. Likewise, column address latch/buffer
`412 and column decoder 414 receive and decode a column
`address from a column address signal provided on address
`lines, and address the corresponding column of the DRAM
`array.
`Data bus 416 receives memory register data during a write
`cycle from the microprocessor for writing to DRAM array.
`Data stored in the DRAM can be transferred during a read
`cycle on bus 416. Control logic 418 is used to control the
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`In the following detailed description of the preferred
`embodiments, reference is made to the accompanying draw
`ings which form a part hereof, and in which is shown by way
`of illustration speci?c preferred embodiments in which the
`inventions may be practiced. These embodiments are
`described in su?icient detail to enable those skilled in the art
`to practice the invention, and it is to be understood that other
`embodiments may be utilized and that logical, mechanical
`and electrical changes may be made without departing from
`the spirit and scope of the present inventions. The following
`detailed description is, therefore, not to be taken in a limiting
`sense, and the scope of the present inventions is de?ned only
`by the appended claims.
`It will be understood that the following description of a
`DRAM is intended to provide a general understanding of the
`memory and is not a complete description of all the elements
`and features of a DRAM. Further, the present invention is
`equally applicable to any size and type of integrated circuit,
`including programmable logic, microprocessors, and
`memories, and is not intended to be limited to the DRAM
`described below.
`One embodiment of the invention describes a pattern for
`e?icient placement of fuses and is illustrated in FIG. 1A.
`Shown is a fuse set comprised of three fuses, hereinafter the
`left fuse 101, the central fuse 102, and the right fuse 103.
`Each fuse has a narrow section 101a, 102a, 103a and a wide
`section 101b, 102b, 103b. In this embodiment the size and
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`many available functions of the DRAM. Various control
`circuits and signals not detailed herein initiate and synchro
`nize the DRAM operation as known to those skilled in the
`art Control circuitry 418 can include redundant memory
`element enable circuits. That is, the memory array includes
`both primary and redundant memory cells. If a primary
`memory cell is determined to be defective, a redundant
`memory cell can be programmed to function in place of the
`defective primary cell. The control circuit 418, therefore,
`controls both row decoder 410 and column decoder 414 such
`that the proper memory cell is addressed.
`Some of the inputs and outputs of DRAM 400 used to
`communicate with microprocessor 404 are described as
`follows. Write enable input (WE*) is used to select a read or
`write cycle when accessing the DRAM. To read the DRAM
`15
`array, the WE* line is high when CAS* falls. If the WE* line
`is low when CAS* falls, the DRAM is written to. Row
`address strobe nine row address bid to clock in the nine row
`address bits and strobe for WE*. CAS*, and DQ. In standard
`memories, the RAS* also acts as the master chip enable and
`must fall for the initiation of any DRAM array or transfer
`operation. Column address strobe (CAS*) input is used to
`clock in the nine column address bits.
`Address input lines are used to identify a row and column
`address to select at least one memory cell out of the available
`memory cells of DRAM array 402. DRAM data input/output
`lines 416 provide data input and output for the DRAM array.
`As stated above, the DRAM description has been simpli?ed
`for purposes of illustrating the present invention and is not
`intended to be a complete description of all the features of
`a DRAM.
`One example of how a fuse circuit is employed in an
`electronic memory is illustrated in FIG. 5. Redundant enable
`circuit 500 is typically included in a memory, such as the
`DRAM described above. The redundant enable circuit can
`be included in control circuit 418 to access a redundant
`memory cell when an address of a defective primary cell is
`received on address lines 406. A comparator 560 is used to
`compare each address line to reference line 570. Although
`only one reference line is illustrated, it will be understood
`that in a preferred embodiment each address line has a
`corresponding reference line. Further, a redundant enable
`circuit 500 is provided for each redundant memory cell
`included in the memory array.
`To enable a redundant memory cell, fuse 540 is
`programmed, as desuibed above, so that the reference line
`90 matches the address of a defective memory cell. That is,
`fuse 540 normally has a conductive path from one end to the
`other. The input to inverter 550, therefore, is low and its
`output 570 is high. When the fuse is programmed, the input
`to inverter can ?oat unless latched to a proper voltage. To
`“read” the state of the fuse and latch the input of the inverter
`transistors 510, 520 and 530 are provided. Providing a low
`signal to the gate of transistor 510 during the memory circuit
`power-up sequence, transistor 510 is activated and the
`source of transistor 520 is pulsed high to VCC. If fuse 540
`is unprogrammed then line 580 is pulled low. Conversely, if
`fuse 540 is programmed the input to inverter 550 is pulled
`high through transistor 590. The gate of transistor 530 is
`pulled low with the output of inverter 550, which turns on
`transistor S30, thereby latching the input of inverter 550
`high. It will be understood that many di?’erent circuits can
`be used to enable redundant memory elements and the
`present invention is not limited to the circuit described
`herein. Further, integrated circuits, including memories, can
`use the fuses of the present invention for any application
`where fuses may be needed.
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`
`6
`Conclusion
`A spatially optimized laser fuse bank has been described
`for use in an integrated circuit. The pattern of fuses is used
`to increase the maximum number of fuses in integrated
`circuits, thereby allowing an increase in the density of
`devices included in the circuit.
`Although speci?c embodiments have been illustrated and
`described herein, it will be appreciated by those of ordinary
`skill in the art that any arrangement which is calculated to
`achieve the same purpose may be substituted for the speci?c
`embodiment shown. This application is intended to cover
`any adaptations or variations of the present invention.
`Therefore, it is manifestly intended that this invention be
`limited only by the claims and the equivalents thereof.
`What is claimed is:
`1. An integrated circuit laser fuse system comprising:
`a plurality of laser fuse banks, each laser fuse bank
`comprising:
`a center fuse having a narrow end, a wide end, and a
`cormnon centerline;
`a ?rst outer fuse having a narrow end and a wide end,
`located adjacent to the center fuse such that the
`narrow end of the ?rst outer fuse is adjacent to the
`narrow end of the center fuse and the wide end of the
`?rst outer fuse is adjacent to the wide end of the
`center fuse, the wide end of the ?rst outer fuse is
`laterally offset from the narrow end of the ?rst outer
`fuse; and
`a second outer fuse having a narrow end and a wide
`end, located adjacent to the center fuse and on the
`side of the center fuse opposite the ?rst outer fuse
`such that the narrow end of the second outer fuse is
`adjacent to the narrow end of the center fuse and the
`wide end of the second outer fuse is adjacent to the
`wide end of the center fuse, and the wide end of the
`second outer fuse is laterally o?’set from the narrow
`end of the second outer fuse.
`2. The integrated circuit laser fuse system of claim 1
`wherein the plurality of laser fuse banks comprise:
`a ?rst laser fuse bank; and
`a second laser fuse bank positioned such that the second
`laser fuse bank is adjacent to the ?rst laser fuse bank,
`and the second laser fuse bank is rotated one hundred
`eighty (180) degrees from the ?rst laser fuse bank.
`3. The integrated circuit laser fuse system of claim 1
`wherein the wide end of the ?rst outer fuse is laterally offset
`from its narrow end in an outwardly direction away from the
`center fuse.
`4. The integrated circuit laser fuse system of claim 1
`wherein the wide end of the second outer fuse is laterally
`o?set from its narrow end in an outwardly direction away
`from the center fuse.
`5. The integrated circuit laser fuse system of claim 1
`wherein the plurality of laser fuse banks are polysilicon
`fabricated on an integrated circuit.
`6. The integrated circuit laser fuse system of claim 1
`wherein the plurality of laser fuse banks are fabricated in a
`dynamic random access memory (DRAM), the DRAM
`comprising:
`a plurality of primary memory cells; and
`a plurality of redundant memory cells.
`7. The integrated circuit laser fuse system of claim 6
`wherein the DRAM further includes a redundant enable
`circuit comprising:
`a latch circuit coupled to one of the fuses of the plurality
`of laser fuse banks; and
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`5,747,869
`
`7
`a comparator circuit connected to the latch circuit and a
`plurality of external address inputs.
`8. An integrated circuit laser fuse system comprising:
`a plurality of substantially straight laser fuses, each one of 5
`the plurality of substantially straight laser fuses being
`located adjacent to and parallel with remaining ones of
`the plurality of substantially straight laser fuses; and
`a common ground connection interconnecting the mid- 10
`points of the plurality of laser fuses.
`9. The integrated circuit laser fuse system of claim 8
`wherein the plurality of laser fuses are polysilicon fabricated
`on an integrated circuit.
`
`8
`10. The integrated circuit laser fuse system of claim 8
`wherein the plurality of laser fuses are fabricated in a
`dynamic random access memory (DRAM), the DRAM
`compnsmg:
`a plurality of primary memory cells; and
`a plurality of redundant memory cells.
`11. The integrated circuit laser fuse system of claim 10
`wherein the DRAM further includes a redundant enable
`circuit comprising:
`a latch circuit coupled to one end of one of the plurality
`of laser fuses; and
`a comparator circuit connected to the latch circuit and a
`plurality of external address inputs.
`
`* * * * *
`
`8
`
`