United States Patent 1191
`Yoo et a].
`
`5,729,041
`Mar. 17, 1998
`
`Hllllllllllllllllllllllllllllllll
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`llllllllllllllllilllllllllllllll
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`US00572904 1A
`Patent Number:
`1111
`[45] Date of Patent:
`
`[54] PROTECTIVE FILM FOR FUSE WINDOW
`PASSIVATION FOR SEMICONDUCTOR
`INTEGRATED ClRCUIT APPLICATIONS
`
`.
`[75] Inventors‘
`
`.
`-
`.‘rgxa'lm'wan Lee‘ both °f
`
`’
`
`.
`.
`.
`[73] Asslgnw Tam“ semfconducmr
`Manuf?ctlll‘mg Company, Ltd,
`Hsin-Chu. Taiwan
`
`.
`[21] AP p 1' No" 684’162
`[22] Filed:
`Jul. 19, 1996
`
`6/1991 Billig et a1. ............................... .. 29/34
`5,025,300
`8/1991 Machida et a1.
`257/635
`5,041,897
`5,065,222 11/1991 Ishii ...... ..: ......... ..
`257/640
`5,241,212
`8/1993 Montonami et a1.
`257/529
`5,329,152
`7/1994 Janai et a]. ............ ..
`257/529
`5,365,104 11/1994 Godinho et a1.
`257/529
`5,486,719
`1/1996 Sugiuraetal.
`257/640
`5 78,861 11/1996 Kinoshitaetal. ..
`257/529
`5§85,662 12/1996 Ogawa ...... ..
`257/529
`5,592,004
`1/1997 Tamura et a1. ........................ .. 257/323
`
`Primary Examiner—Tom Thomas
`Assistant Examiner—David B. Hardy
`Attorney, Agent, or Firm-George O. Saile; Stephen B.
`Ackerman; William J. Sto?’el
`
`Related US. Application Data
`
`[57]
`
`ABSTRACT
`
`_
`_
`.
`DlVlSlOll 0f SCI. N0. 328,587, 001. 24, 1994, P31. N0.
`5’578’517'
`[51] Int. Cl.6 ................................................... .. H01L 27/02
`[52] us. Cl. ............ ..
`257/529; 257/640; 257/665
`[58] Field of Search
`........................ .. 257/529, 665,
`257/640’ 641
`
`[56]
`
`References Cited
`
`U'S' PATENT DOCUMENTS
`9/1984 Inoue et a1. ........................... .. 313/366
`4,469,985
`8/1985 Takayama et a1.
`..... .. 29/578
`4,536,949
`4,618,541 10/1986 Forouhietal.
`257/640
`4,795,720
`1/1989 Kawanabe et a1. ................... .. 257/529
`
`An integrated circuit includes a conductive fusible link that
`may be blown
`laser irradiation, The inte_
`grate circuit comprises a silicon substrate; a ?rst insulating
`layer; a fusible link on the ?rst layer; a second insulating
`layer overlying the ?rst layer and the fusible link; an opening
`through the “90nd layer exposing the fuse; and a Protec?ve
`layer over the surfaces of the opening. A laser beam is
`irradiated through the opening and the protective layer to
`melt the fusible link. The protective layer is highly trans
`parent to a laser beam and does not interfere with the laser
`melting (trimming) operation. Moreover, the protective
`layer Prcvents contaminates from diffusing in through the
`opening to harm adjacent semiconductor devices.
`
`18 Claims, 3 Drawing Sheets
`
`4-8
`
`IPR2015-01087 - Ex. 1024
`Micron Technology, Inc., et al., Petitioners
`1
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`

`

`U.S. Patent
`
`Mar. 17, 1998
`
`Sheet 1 of 3
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`5,729,041
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`FIG’.
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`1
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`26
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`6O 61
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`62
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`FIG. 2 -— Prior Art
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`2
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`US. Patent
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`Mar. 17, 1998
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`Sheet 2 of 3
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`5,729,041
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`FIG. 3 — Prior Art
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`4-6\-(—
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`i
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`Y\ \\ \\ \\\\
`42‘! m S
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`26
`4
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`/ / /
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`10
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`FIG. 4
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`3
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`US. Patent
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`Mar. 17, 1998
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`Sheet 3 of 3
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`5,729,041
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`48
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`i6 ////////4
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`10
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`FIG. 5
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`4-8
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`46 _ l Ti 5°
`44 m m
`42-k
`w\\\‘
`if“ ///////%S
`10
`3
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`FIG. 6'
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`4
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`5,729,041
`
`1
`PROTECTIVE FILM FOR FUSE WINDOW
`PASSIVATION FOR SEMICONDUCTOR
`INTEGRATED CIRCUIT APPLICATIONS
`
`This application is a divisional of Ser. No. 08/328,587
`?led Oct. 24, 1994, now U.S. Pat No. 5,578,517.
`
`BACKGROUND OF THE INVENTION
`
`2
`(BPSG), spin on glass, silicon oxide and silicon nitride
`respectively. Opening 28 is formed over the fuse 26 area
`through the insulating layers 32, 34, 36. 38. Opening 28 can
`have a width of 5 microns and a length of 5 microns. An
`adjacent semiconductor device is shown with buried N+
`regions 60, 61, 62, gate oxide 64, gate 66. via 40 and metal
`layers 68, 70.
`A laser is used to blow the fuses 26. The laser is focused
`through the fuse opening 28 and irradiates the fuse 26. It is
`conventional to have an opening 28 over the fuse 26 in the
`area where the fuse 26 will be broken so that the laser
`heating will be more effective. Because the passivation
`layers overlying a fuse 26 would reduce the laser energy
`striking the fuse, the passivation layers are etched away so
`that the fuse 26 is exposed or, in an alternative, only single
`thin insulating layer or a portion of a thin insulating layer
`covers the fuse.
`The fuse 26 absorbs the heat from the laser irradiation and
`the fuse melts. In this operation, sometimes called laser
`trimming, the rapid temperature rise of the upper portion of
`the fuse 26 causes an increase in pressure. This pressure
`cause any overlying ?lm 32 to be “blown of’ and the melted
`polysilicon fuse is removed by evaporation. Laser trimming
`requires that only a very thin insulating layer cover the fuse
`because the laser must be able to penetrate the layer and melt
`the fuse. The portion of the fuse 26 and thin insulating layer
`32 over the fuse which is melted away or “blown” must not
`deposit on or interfere with near-by devices. In the example
`shown in FIG. 3, an opening 28 is formed through four
`layers: Silicon nitride 38, silicon oxide 36. spin on glass 34
`and borophosphosilicate glass (BPSG) layer 32.
`A major problem with a window opening in the passiva
`tion layers is that moisture and contamination can enter
`through the exposed passivation layers and dilfuse to the
`semiconductor devices. The di?‘used moisture and contami
`nates can decrease device reliability and yields. Moreover.
`moisture is present in the air and sodium (Na+ ions) are
`plentiful in the environment.
`As shown in FIG. 3, moisture and other contaminates can
`enter through the window 28. di?use into spin on glass layer
`34 and di?iuse to the adjacent semiconductor devices 31, 40.
`64. Water will attack the metal interconnects 70. and sodium
`and other contaminates can harm MOS devices 31. 64.
`First, water can attack the metal interconnects 70, with the
`following reaction:
`
`The formation of Al(OH)3 causes the resistance of metal
`interconnects 70 to increase and ?nally causes circuit failure.
`Second. contamination can harm MOS devices. FIG. 3
`shows an opening 28. buried N+ regions 60. 61. 62. ?eld
`oxide 31, gate oxide 64. polysilicon gate 66. and metal
`layers 68. 70. Mobile ions, such as sodium ions. can di?use
`through inter-metal dielectric layer 34. and through the
`insulating layer 34 into the ?eld oxide layer 31. Mobile ions
`in the ?eld oxide layer 31 can cause ?eld inversion which
`allows an undesired leakage current between adjacent buried
`N+ (or P+) regions 60, 61 resulting in circuit failure. Also,
`mobile ions in the gate oxide 64 will cause a transistor
`threshold shift whereby the circuit fails.
`The following three U.S. patents show fusible link
`structures. but do not adequately solve the problem of
`contamination diffusing through the window opening to
`adjacent devices and not interfering with the laser trimming
`operation.
`Billing et all, U.S. Pat. No. 5.025.300 teaches an inte
`grated circuit where a very thin protective dielectric layer
`
`1. Field of the Invention
`This invention relates to integrated circuits and semicon
`ductor devices. It relates particularly to a structure and
`method for producing integrated circuits having an
`improved contamination passivation ?lm for surface
`features, such as fusible links and photo alignments marks.
`2. Description of the Prior Art
`Fusible conductive links (fuses) are often used in rewiring
`electrical circuits to replace defective devices with redun
`dant devices. These circuits are rewired by rendering the
`fuses non-conductive (i.e., blown) by applying laser energy
`to the fuse with a laser trimming machine.
`In dynamic or static memory chips. defective memory
`cells may be replaced by blowing the fuses associated with
`the defective cells, and activating a spare row or column of
`cells. This circuit rewiring using fusible links considerably
`enhances yields and reduces the production costs.
`Logic circuits may also be repaired or recon?gured by
`blowing fuses. For example, it is common to initially
`fabricate a generic logic chip having a large number of
`interconnected logic gates. Then in a ?nal processing step.
`the chip is customized to perform a desired logic function by
`disconnecting the unnecessary logic elements by blowing
`the fuses that connect them to the desired circuitry. Still
`other applications of laser-blown fuses are possible.
`Semiconductor chips often have openings through pro
`tective insulating layers over fusible link regions to allow a
`laser to irradiate the fuse. But these openings frequently
`lowers chip yields and reliability by allowing contamination
`to penetrate from the openings to the device regions.
`FIG. 1 shows a top plan view of a semiconductor chip 12
`with openings 28 over fusible links surrounded by active
`device areas 14. A conventional fusible link (i.e., fuse) 26,
`a fusible link opening 28 and an adjacent device region 60.
`61, 62. 66. is shown in top plan view FIG. 2. Referring to
`FIG. 3, a cross-sectional view of the same link and device
`regions in FIG. 2 taken along horizontal axis labeled 3 is
`shown.
`An important challenge is to improve the reliability of the
`semiconductor devices surrounding fusible links, especially
`when a large number of the fusible link openings 28 are on
`a chip 12. A window opening 28 is normally formed through
`the insulating layers over a fuse 26 so that a laser beam can
`be used to irradiate the fuse. thereby blowing it. A problem
`with openings 28 over a fusible link regions is that moisture
`and other contaminates can dilfuse from the openings,
`through the insulating layers, into the semiconductor devices
`thus reducing circuit reliability and yields.
`As shown in FIG. 3. fuse 26 is normally formed over thick
`?eld oxide regions 31 in a semiconductor substrate 10. Fuse
`26 is formed over the ?eld oxide regions 31 to prevent
`shorting of the fuse 26 to the substrate 10. Fuse 26 can be
`formed of a metal. such as aluminum. platinum silicide,
`titanium tungsten. polysilicon. or a polycide. such as tita
`nium polycide. tungsten polycide or molybdenum polycide.
`Layers 32. 34, 36, 38 are insulating (passivation or
`dielectric) layers. such as borophosphosilicate glass
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`5,729,041
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`4
`BRIEF DESCRIPTION OF THE DRAWINGS
`The drawings show the following:
`FIG. 1 is a top plan view in greatly enlarged scale that
`illustrates fusible link regions and active semiconductor
`device areas on a semiconductor chip.
`FIG. 2 is plan view in broken section in greatly enlarged
`scale that illustrates a fusible link. fuse window, and adjacent
`semiconductor devices in accordance with the prior art.
`FIG. 3 is cross-sectional view along axis 3 in FIG. 2, in
`broken section and in greatly enlarged scale that illustrates
`a fuse opening and adjacent semiconductor devices in accor
`dance with the prior art process.
`FIGS. 4 through 6 are cross-sectional views in broken
`section that illustrate a structure and a process for forming
`a fuse opening with a protective layer in accordance with the
`invention.
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`composed of silicon dioxide, silicon nitride or silicon
`oxynitride, is formed over the fuse in a window (Billig, Col.
`4, lines 58-61). The dielectric layer has a thickness that
`allows the laser to penetrate, but the layer reduces the laser
`energy to the fuse. potentially preventing the laser from
`blowing the fuse. Also, because the dielectric layer interferes
`with the laser irradiation, its thickness uniformity must be
`tightly controlled to allow consistent laser cutting from fuse
`to fuse. In another embodiment of Billig, a thin protective
`dielectric layer is formed after the fuse is blown. This
`invention prevents shorts between conductors that otherwise
`might occur due to debris from the fuse-blowing operation.
`This embodiment has tradeolfs since the extra protective
`layer must be removed from some device surfaces. for
`example. over metal bonding areas. Also, forming the extra
`layer and partial removal steps add cost.
`Takayarna. US. Pat. No. 4.536949 discloses a method of
`forming an opening over fuses where each insulation layer
`is etched separately yielding a more accurate opening.
`However. the problem of contamination diffusing to the
`devices through the exposed sidewalls of the opening still
`exists.
`Motonarni. US. Pat. No. 5,241,212, discloses a protective
`layer covering an opening through a single insulating layer
`for a fuse. In one embodiment. the protective layer only
`covers the surface of the protective layer, but leaves the
`sidewall of the insulating layer exposed for contamination to
`diifuse through. In a second embodiment, the protective
`coating covers the top of the isolation layer, the sidewalls of
`the fuse opening and also covers the isolation over the fuse
`and the fuse. Unfortunately. the protective layer over the
`fuse inhibits the laser from heating the fuse which can cause
`problems in consistently laser n'imming (blowing) the fuse.
`Thus, it is desirable to ?nd a solution that prevents
`contamination from entering into the sidewalls of the
`openings. but does not interfere with the laser irradiation
`which heats the fuse in the laser trimming operation.
`SUMMARY OF THE INVENTION
`It is a general object of the invention to provide an
`improved structure and method for forming a protective
`layer over a fuse and fuse window of an integrated circuit.
`An more speci?c object of the present invention is to
`provide an improved structure and method for forming an
`protective layer which prevents contamination from di?us
`ing through a window opening over a fuse where the
`protective layer is has a high transmittance of laser energy
`used in laser trimming operations.
`In accordance with the above objects. a structure and
`technique for forming a protective layer. with a high trans
`mittance to laser energy, over a fusible link is provided
`A ?rst insulating layer is formed on a semiconductor
`substrate. Next. a fuse is formed on the ?rst insulating layer.
`At least one additional layer of insulating material is formed
`over ?rst insulating layer and the fuse. A window opening
`over the fuse is formed at least partially through the second
`insulating layer which either exposes the fuse or exposes a
`portion of the second insulating layer over the fuse.
`A protective passivation layer is formed over the top
`insulating layer. the sidewalls of the opening. portions of
`exposed second insulating layer. and the fuse. This protec
`tive insulating layer prevents contamination from entering
`into the insulating layer(s) while not interfering with the
`laser irradiation and trimming of the fuse.
`The protective insulating layer. which has a greater than
`50% transmittance of laser irradiation. is formed of silicon
`nitride which has a ratio of nitrogen to silicon from 1.2 to
`1.6.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIIVIENTS
`The following detailed description relates to an improved
`structure and technique for forming a protective layer over
`a fusible link and an opening in a passivation layer(s) for
`integrated circuits.
`The method of the present invention will be described as
`a protective layer over an opening for a fuse and not by way
`of limitation. The protective layer of the present invention
`can be applied to other structures, such as alignment mark
`regions. Moreover. the location of the fuse in this description
`is on the ?rst insulating layer, but the fuse may in practice
`by located on any insulating layer in the integrated circuit.
`Furthermore. four insulating layers are described in this
`invention. but in practice the actual number and composition
`of the layers may vary. Also. the composition. location and
`number of fusible links may vary in actual practice.
`Referring to FIG. 4. a ?rst isolating layer 40 is formed on
`portions a semiconductor substrate 10. First isolating layer
`40 electrically isolates adjacent semiconductor devices from
`each other. The ?rst insulating layer 40 is formed of a
`dielectric material and is preferably formed of thick silicon
`oxide. sometimes called ?eld oxide. Silicon oxide can be
`grown at atmospheric pressure at a temperature of between
`700° to 1200° C. in a wet or dry oxygen ambient in a thermal
`furnace. Layer 40 has a thickness in the range of 2000 to
`8000 angstroms and preferably. a thickness of approxi
`mately 5000 angstroms.
`A fusible link 26 is formed over the ?eld oxide 40. The
`fusible link 26 is part of a patterned metal layer formed of
`over the ?rst insulating layer 40. The ?eld oxide 40 isolates
`the fusible link from adjacent devices and most importantly,
`from the substrate 10. Alternatively, the fusible link 26 can
`be formed over other layers. such as a borophosphosilicate
`glass (BPSG) layer (e.g.. layer 42). The BPSG layer can be
`grown by conventional plasma enhanced chemical vapor
`deposition (PECVD) or atmospheric pressure chemical
`vapor deposition (APCV D) and has a thickness in the range
`of 3000 to 15.000 A.
`Fuse 26 can be formed of a metal. such as aluminum.
`platinum silicide. titanium tungsten, or polysilicon. Also.
`fuse 26 can be formed of a polycide. such as titanium
`polycide. tungsten polycide. and molybdenum polycide.
`Fuse 26 typically has a thickness in the range of 500 to 5000
`angstroms and a length in the range of 5 to 10 microns and
`a width in the range of l to 3 microns. Fuse 26 can be
`“blown” by applying laser energy which allows redundant
`circuit devices to be activated and replace defective devices.
`
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`5,729,041
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`5
`Next, a second insulating layer 42 is formed over the fuse
`26 and the ?rst insulating layer 40. Second insulating layer
`42 is formed of a dielectric material and can be formed of
`borophosphosilicate glass, phosphosilicate glass, silicon
`oxide, or other suitable insulating material. Borophospho
`silicate glass can be formed by atmospheric pressure chemi
`cal vapor deposition (APCV D) of tetraethylorthosilicate
`(TEOS) according to principles known in the art. Boron and
`phosphorus are added to the ambient during the formation of
`the borophosphosilicate glass layer. The. layer 42 is ther
`mally treated at a temperature of 850° C. for 30 minutes to
`cause ?ow and planarization. Second insulating layer 42 can
`have thickness in the range of 3000 to 15,000 angstroms and
`pgeferably a thickness of approximately 6000 angstroms
`( )
`Afterwards, a third insulating layer 44 is formed overly
`ing the second insulating layer 42. Moreover, third insulat
`ing layer 44 has a thickness in the range of 5000 to 20.000
`angstroms and preferably a thickness of approximately
`10,000 angstroms.
`Third insulating layer 44 can be formed by at least four
`alternate processes. First, layer 44 can be formed of a two
`layer structure with a PECVD layer and a spin on glass
`(SOG) layer. The layers can be applied in any order (i.e.,
`SOG-PECV D or PECVD-SOG). Spin on glass layers can be
`formed using a siloxane or silicate, which is deposited,
`baked and cured at approximately 400° C. Silicon oxide is
`deposited by plasma enhanced chemical vapor deposition
`(PECV D). Both the SOG and PECVD layers can be etched
`back.
`In the second process, layer 44 can be formed by making
`a three layer sandwich structure of a) silicon oxide, b) spin
`on glass and c) silicon oxide. The bottom silicon dioxide
`layer can be deposited using plasma enhanced chemical
`vapor deposition (PECVD)) by reacting silane and nitrous
`oxide in an argon plasma at 200° to 450° C. The bottom
`silicon dioxide layer has a thickness of approximately 2000
`Angstroms. The middle spin on glass (SOG) layer can be
`formed using a siloxane or silicate . which is deposited,
`baked and cured at approximately 400° C. The middle spin
`on glass layer has a thickness of approximately 3000 Aug
`stroms. The top silicon oxide layer has a thickness of
`approximately 5000 angstroms and is formed using the same
`processes described above for the bottom silicon oxide layer.
`The overall thickness of layer 44 is in the range of 7000 to
`20.000 angstroms.
`Third, layer 44 can be formed of an oxide formed by an
`electron cyclotron resonance (ECR) process. Fourth. layer
`44 can be formed of an oxide formed by a conventional
`tetraetl'rylorthosilicate (TEOS) process.
`As shown in FIG. 4. a fourth insulating layer 46 is formed
`over the third insulating layer 44. Layer 46 can be formed of
`silicon oxide or silicon nitride deposited by plasma
`enhanced chemical vapor deposition (PECVD). Layer 46
`has a thickness in the range of 2000 to 10,000 angstroms and
`preferably a thickness of 5000 angstroms.
`Referring to FIG. 5. an opening 48 over fuse 26 is formed
`with vertical sidewalls exposing portions of the second 42,
`third 44, and fourth 46 insulating layers. Opening 48 also has
`a bottom surface comprised of second insulating layer
`and/or the fuse 26. Opening 48 can extend down to fuse 26
`thus exposing the fuse 26. Moreover, Opening 48 can be
`formed using conventional photolithography and etching
`techniques, such as a reactive ion etch process using CHF3/
`CF4lSF6/Ar/He.
`Opening 48 can extent through part or all of layer 42 (see
`FIG. 5). The thickness t1 of the second insulating layer 42
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`overlying the fuse 26 is in the range of 0 to 10,000 angstroms
`and preferably approximately 5000 angstroms. The thick
`ness t1 should be small and tightly controlled to allow the
`laser irradiation to consistently penetrate the ?lm 42 to
`consistently melt the fuse without overheating and damaging
`the surrounding insulating layers 40, 42, 44, 46, and devices.
`Next, a protective dielectric ?lm 50, which is highly
`transparent to laser energy, is deposited over the fourth layer
`46, the exposed portion of the second 42, and third 46 layers
`in the opening 48 and the fuse 26 as shown in FIG. 6.
`Protective ?lm 50 can be formed of plasma enhance chemi
`cally deposited (PECV D) silicon nitride.
`The protective layer 50 is deposited using a plasma
`enhanced chemical vapor deposition (PECVD) process by
`reacting silane (SiH4) and ammonia (NH3)in a nitrogen
`plasma (PECVD) at a temperature of 200° to 450° C.. the
`ratio of SiH4 to NH3 from 1.3 to 1.6, a pressure range of 2
`to 10 torr., an electrode spacing of 560 to 600 mils and a
`radio frequency (rf) power setting of between 350 to 400
`watts. Layer 50 has a thickness in the range of 3000 to
`15,000 angstroms and more preferably a thickness of 7000
`angstroms. The silicon to nitrogen ratio in protective layer
`50 should be in the range of 1.2 to 1.6 and more preferably
`a ratio of 1.4.
`Using the above process, the transmittance of an laser
`beam through the protective layer 50 should be greater than
`50%. Preferably, the transmittance of the laser beam through
`the protective layer 50 should be greater than 50% at a laser
`irradiation wavelength in the range of 1037 to 1057 nanom
`eters. The laser used can be a Yumium-Yag laser at wave
`length in the range of 1037 to 1057 nanometers and a pulse
`less than 35 nanoseconds.
`In another embodiment of the present invention, protec
`tive layer 50 is applied after the laser trimming process.
`Also. two protective layers can be applied to ensure maxi
`mum protection, i.e., a protective layer 50 applied before the
`laser trimming operation and a second protective layer
`applied after the laser trimming operation.
`This invention has the advantages of reducing contami
`nation which enters through the exposed portion of the
`insulating layers 42, 44. 46 in the sidewalls 47 of the
`opening 48 over a fuse 26. The protective layer 50 covers the
`exposed portions of the insulating layers 42. 44. 46 over the
`fuse opening sidewalls 47 preventing contamination from
`entering. In addition to preventing contamination. the pro
`tective layer 50 of the present invention is highly transparent
`to laser irradiation and does not interfere with the laser
`trimming process.
`While the invention has been particularly shown and
`described with reference to the preferred embodiments
`thereof. it will be understood by those skilled in the art that
`various changes in form and details may be made without
`departing from the spirit and scope of the invention.
`What is claimed is:
`1. An integrated circuit having a patterned metal level
`formed on a ?rst layer of insulating material. at least a
`second layer of insulating material covering portions of said
`patterned metal level, wherein said pattern level contains at
`least one fusible link portion. an opening at least partially
`through the second layer over the fusible link. said opening
`having a bottom and sidewall surfaces, a protective layer of
`silicon nitride overlying the second layer. the bottom and
`sidewall surfaces of the opening. and the fusible link por
`tions; and
`characterized in that said protective layer of silicon nitride
`material has a ratio of silicon to nitrogen in the range
`
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`7
`from 1.2 to 1.6 and said protective layer having a
`transmittance to laser irradiation of greater than 50%.
`2. The integrated circuit of claim 1 wherein the ?rst
`insulating layer is silicon oxide having a thickness in the
`range from 2000 to 8000 angstroms.
`3. The integrated circuit of claim 1 wherein the second
`insulating layer is formed of borophosphosilicate glass hav
`ing a thickness in the range from 3000 to 15.000 angstroms.
`4. The integrated circuit of claim 1 wherein the protective
`layer is comprised of silicon nitride with a thickness in the
`range from 3000 to 15,000 A.
`5. The integrated circuit of claim 1 wherein the protective
`layer of silicon nitride has a transmittance of greater than
`50% for laser irradiation in the wavelengths in the range
`from 1037 to 1057 nanometers.
`6. The integrated circuit of claim 1 wherein the second
`layer is formed of borophosphosilicate glass.
`7. The integrated circuit of claim 1 wherein a third layer
`and a fourth layer of insulating material are formed over the
`second layer and the opening extends through both the third
`and fourth layers.
`8. The integrated circuit of claim 7 wherein the third
`insulating layer is a composite layer of silicon oxide, spin on
`glass, and silicon oxide. and said third insulating layer
`having an overall thickness between 7000 and 20.000 ang
`stroms.
`9. The integrated circuit of claim 7 wherein the third layer
`is a composite layer of spin on glass and silicon oxide.
`10. The integrated circuit of claim 7 wherein the fourth
`layer is formed of silicon nitride having a thickness in the
`range of 2000 to 10.000 angstroms.
`11. The integ'ated circuit of claim 7 wherein the fourth
`layer is formed of silicon oxide having a thickness between
`2000 and 10.000 angstroms.
`12. An laser irradiation transparent passivation protective
`layer covering a fusible link for a semiconductor integrated
`circuit device comprising:
`a ?rst insulating layer on a semiconductor substrate;
`a fusible link on said ?rst insulating layer;
`a second insulating layer overlying said fusible link and
`said ?rst insulating layer;
`an opening over the fusible link at least partially through
`the second layer. said opening having a bottom and
`sidewalls surfaces; and
`a protective layer composed of silicon nitride having a
`ratio of silicon to nitrogen in the range from 1:12 to
`121.6 and having a greater than 50% transmittance to
`laser irradiation in the wavelengths between 1037 and
`1057 nanometers. said protective layer having a thick
`ness in a range of between about 3000 and 15.000 A.
`and said protective layer covering said fusible link. said
`
`30
`
`35
`
`45
`
`5,729,041
`
`10
`
`20
`
`25
`
`8
`second insulating layer, and the bottom and sidewall
`surfaces of the opening.
`13. The laser irradiation transparent protective layer of
`claim 12 wherein the second insulating layer comprises
`more than one insulating layer.
`14. The laser irradiation transparent protective layer of
`claim 12 wherein the opening is completely through the
`second insulating layer and exposes a portion of the fuse.
`15. An integrated circuit having a patterned metal level
`formed on a ?rst layer of insulating material, at least a
`second layer of insulating material covering portions of said
`patterned metal level, said second layer of insulating mate
`rial is forrned of borophosphosilicate glass. wherein said
`pattern level contains at least one fusible link portion. an
`opening at least partially through the second layer over the
`fusible link. said opening having a bottom and sidewall
`surfaces, a protective layer of silicon nitride overlying the
`second layer. the bottom and sidewall surfaces of the
`opening. and the fusible link portions; and
`characterized in that said protective layer of silicon nitride
`material has a ratio of silicon to nitrogen in the range
`from 1.2 to 1.6 and said protective layer having a
`transmittance to laser irradiation of greater than 50%.
`16. The integrated circuit of claim 15 wherein the second
`layer of insulating material is formed of borophosphosilicate
`glass having a thickness in the range from 3000 to 15.000
`angstroms.
`17. An integrated circuit having a patterned metal level
`formed on a ?rst layer of insulating material. at least a
`second layer of insulating material covering portions of said
`patterned metal level. a third layer and a fourth layer of
`insulating material are formed over said second layer; said
`third layer is a composite layer of spin on glass and silicon
`oxide. wherein said pattern level contains at least one fusible
`link portion. an opening at least partially through the second
`layer over the fusible link and said opening extends through
`both said third and fourth layers. said opening having a
`bottom and sidewall surfaces. a protective layer of silicon
`nitride overlying the second layer, the bottom and sidewall
`surfaces of the opening. and the fusible link portions; and
`characterized in that said protective layer of silicon nitride
`material has a ratio of silicon to nitrogen in the range
`from 1.2 to 1.6 and said protective layer having a
`transmittance to laser irradiation of greater than 50%.
`18. The integrated circuit of claim 17 wherein the third
`insulating layer is a composite layer of silicon oxide. spin on
`glass, and silicon oxide. and said third insulating layer
`having an overall thickness between 7000 and 20.000 ang
`stroms.
`
`8
`
`