United States Patent [191
`Ting
`
`U S00530046IA
`[11] Patent Number:
`[45] Date of Patent:
`
`5,300,461
`Apr. 5, 1994
`
`[54] PROCESS FOR FABRICATING SEALED
`SEMICONDUCI‘ OR CHIP USING SILICON
`NITRIDE PASSIVATION FILM
`[75] Inventor: Chiu H. Ting, Saratoga, Calif.
`[73] Assignee:
`Intel Corporation, Santa Clara, Calif.
`[21] Appl. No.: - 8,469
`[22] Filed:
`Jan. 25, 1993
`
`[51] Int. Cl.5 ........................................... .. H01L 21/80
`[52] US. Cl. .................................. .. 437/227; 156/648;
`437/241
`[58] Field of Search ............. .. 437/226, 227, 228, 211,
`437/215, 241; 156/634, 648
`References Cited
`U.S. PATENT DOCUMENTS
`
`[56]
`
`5,024,970 6/1991 Mori .................................. .. 437/227
`FOREIGN PATENT DOCUMENTS
`
`55-027684 2/1980 Japan ................................. .. 437/227
`62-093949 4/1987 Japan
`.... .. 437/241
`l-238l26 9/1989 Japan .................................. .. 437/241
`2-308551 12/1990 Japan .
`
`OTHER PUBLICATIONS
`T. C. Hall et al., “Photonitride Passivating Coating for
`
`IC’s”, NASA Tech Briefs, vol. 5, No. 2, Summer 1980,
`pp. 231-232.
`Primary Examiner-Olik Chaudhuri
`Assistant Examiner-Kenneth E. Horton
`Attorney. Agent, or Finn-Blakely Sokoloff Taylor &
`Zafman
`ABSTRACT
`[57]
`Described is a structure and process for forming a her
`metically sealed chip. This hermetically sealed chip will
`greatly simplify packaging requirements and eventually
`lead to the realization of a “packageless chip”. The
`hermetic sealing is composed of two parts, an extremely
`thin passivation layer which is deposited over the entire
`chip top and side surfaces and a passivation layer which
`‘is deposited over the bonding pad surface. Preferably,
`SiN is deposited as a chip surface passivation layer and
`Ni is selectively deposited as a metal passivation layer.
`The extremely thin nitride layer will minimize the stress
`and the amount of hydrogen in the SiN ?lm and mini
`mize deleterious effects upon device performance
`caused by stress and hydrogen. The thickness of the
`metal passivation layer may be the same as that of the
`dielectric layer so as to give a planar surface or it may
`be thick enough so as to give a protruding metal passiv
`ation bump.
`
`11 Claims, 7 Drawing Sheets
`
`[72
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`IPR2015-01087 - Ex. 1023
`Micron Technology, Inc., et al., Petitioners
`1
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`1
`
`PROCESS FOR FABRICATING SEALED
`SEMICONDUCTOR CHIP USING SILICON
`NITRIDE PASSIVATION FILM
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`device characteristic is especially important under high
`?eld stress conditions and is often referred to as the hot
`electron effect. What is needed is a method for sealing
`semiconductor devices that will avoid the above
`described problems.
`-
`Prior art methods for producing both volatile and
`non-volatile memory products require the use of differ
`ent types of passivation materials for the different prod
`ucts due to limitations of the materials used. There are
`three dielectric materials which are in common use as
`semiconductor chip dielectric materials and which can
`be used for chip passivation. These materials include
`silicon dioxide (SiOg), silicon oxynitride (SiON) and
`silicon nitride (SiN). In non~vo1atile memory products
`SiON is typically used for a passivation layer. SiO; has
`poor moisture resistance. Therefore, due to its poor
`moisture resistance properties, current processes do not
`use SiO; for chip passivation. SiON is generally used for
`forming dielectric layers and for passivation of non
`volatile memory ‘products since it is UV transparent.
`Although SiON is a better moisture barrier than SiOZ, it
`gives a relatively poor moisture barrier. SiN, however,
`is an excellent moisture barrier. Thick layers of SiN are
`typically used in fabricating a number of semiconductor
`devices. But thick layers of SiN, as used in prior art
`processes are not transparent to UV light; therefore,
`SiN could not be used for non-volatile memory product
`fabrication. What is needed is a way to make a passiv
`ation layer from SiN which will allow for the passage of
`UV light so that non-volatile memory products can use
`SiN as a passivation material. This would greatly sim
`plify manufacturing processes as SiON processes and
`process machinery would no longer be required. Fur
`thermore, sealed-moisture resistant non-volatile mem
`ory products could then be fabricated.
`>
`Conventional VLSI fabrication methods use bonding
`pads to provide electrical connections between the chip
`and external devices such as the chip packages or multi
`chip substrates. Typically, bonding pads are made of
`Aluminum though any of a number of other conductive
`materials could be used. Bonding pads are formed by
`etching a portion of the passivating layer and the dielec
`tric layer so as to expose a portion of an interlevel metal
`layer which is typically composed of Al. This exposed
`portion of the interlevel metal layer de?nes the bonding
`pad. Since the etch step etches the passivation layer, the
`Al bonding pads are not protected by the passivation
`layer. Moisture and chlorine from the environment and
`the etching process are known to cause corrosion of the
`Al bonding pads when those pads are not placed in
`non-hermetic packages. A method is therefore required
`to protect the Al bonding pads.
`Conventional VLSI processes directly bond Au or Al
`wires to the aluminum bonding pad. Alternatively,
`Pb-Sn solder bumps are used to connect to the alumi
`num bonding pads. One of the problems with the use of
`Pb-Sn solder on Al bonding pads is that inter metallic
`compounds may be formed at the boundary of the
`Pb-Sn solder and the Al. These inter metallic compound
`are often formed due to the elevated temperatures
`which are used in chip packaging processes. To prevent '
`this formation of inter metallic compounds, an elaborate
`diffusion barrier structure consisting of a Cr-Cu-Au
`multilayer is often used between solder bump and Al
`bonding pad. This process is expensive and time con
`suming. The formation of inter metallic compounds can
`cause a poor electrical contact and can lead to contact
`
`FIELD OF THE INVENTION
`This invention relates to the ?eld of semiconductor
`devices and more speci?cally to a process forming a
`sealed semiconductor chip.
`PRIOR ART
`Prior art methods of sealing semiconductor devices
`involve the use of a thick layer of silicon nitride (SiN) to
`seal the dielectric layers of the semiconductor device.
`These layers are formed upon the Si substrate by meth
`ods well-known to those skilled in the art. These prior
`art methods typically seal the top surface of the dielec~
`tric layers by using a thick SiN layer. Thus, they do not
`cover the bonding pads. The bonding pads, therefore,
`are not protected. Additionally, the sides of the chip are
`not protected. Current VLSI semiconductor devices
`typically use hermetically sealed packages such as ce
`ramic pin-grid-array packages to protect semiconductor
`devices. The ceramic packages are very large, heavy,
`and costly and limit the operating speed of devices. Past
`effort in reducing the size and cost of IC packages have
`resulted in the introducing of a variety of new packag
`ing con?gurations such as: small outline package (SOP),
`very small outline package (V SOP), thin small outline
`package (T SOP), and very small quad ?at packs
`(V QFP), etc. This trend in developing new and smaller
`packages will continue. However, the best possible
`situation is to completely eliminate the package so that
`the cost, size and speed of the integrated circuits will be
`limited entirely by the chip itself. This “bare-chip”
`approach will require a “bullet-proof’ passivation on
`chips to protect them from harmful contaminants in the
`environment. This speci?cation describes the structures
`and processes that are needed to provide the required
`“bullet-proof’ chip passivation.
`For passivation layer applications, silicon nitride is
`generally deposited by using a PE-CVD process be
`cause thermal CVD processes require a temperature too
`high for aluminum (Al) metallization. However, unlike
`SiN deposited by thermal CVD process, SiN ?lms de~
`posited by PE-CVD process, have very high stress and
`high hydrogen content. The high hydrogen content in
`the ?lm, often more than 20%, causes the ?lm to be
`thermally unstable because it will release hydrogen
`during subsequent thermal cycles. Therefore, there has
`been much effort to improve the ?lm properties by
`optimizing deposition conditions such as deposition
`temperature, pressure, gas flow rate, plasma power, etc.
`What is needed is a process which will minimize the
`H-content in the deposited ?lms.
`Another disadvantage of prior art methods which
`involve the use of a thick SiN passivation layer is that
`the thick layer creates a high stress within the dielectric
`layers. Stress migration is caused in device intercon
`nects which leads to device degradation and failure.
`60
`The combination of high-stress and high H-content of
`thick nitride layers can cause void formation in the
`underlying Al lines which leads to stress migration
`failures. The released H can work all the way down to
`the device region to generate charge trapping centers in
`the gate oxide. These trapped charges will cause
`changes in the threshold voltage and decreases in the
`trans-conductance of the devices. The degradation in
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`erosion and eventual device failure. What is needed is a
`bonding pad passivation layer as described in the pres
`method for connecting bonding pads to leads which can
`ent invention not only protects the bonding pad from
`use the traditional Pb-Sn solder, and which will not
`corrosion and contamination but it also overcomes
`form inter metallic compounds.
`many of the problems associated with prior art bonding
`Other processes which are currently used to connect
`processes.
`leads to aluminum bonding pads are TAB processes.
`A method for chip surface passivation is also de
`First, additional barrier layers are formed over the Al
`scribed. A SiN passivation layer having a greatly re
`pad. Gold bumps are then formed on top of the addi
`duced thickness as opposed to thicknesses of current
`tional barrier layers. The gold bumps are then used to
`typical passivation layers is used. A‘very thin ?lm of
`bond the leads to the aluminum. The additional barrier
`SiN ?lm, having a thickness of approximately 500 ang
`layers, in the same manner as the Cr-Cu-Au multilayer,
`stroms is used for passivation layer. Alternatively, mul
`prevent the formation of inter metallic compounds. The
`tiple layers of thin SiN ?lms can be used by sandwich
`problem with the use of conventional diffusion barrier
`ing them in between thicker Si02 layers. The thin ?lm
`layers is that additional wafer processing steps are re
`overcomes many of the problems associated with prior
`quired. These processing steps on the already com
`art thick ?lms. This thin ?lm is highly resistant to mois
`pleted device wafer present a great risk of damaging the
`ture, thus giving very effective passivation. The thin
`chip. What is needed is a method for bonding leads to
`?lm described in the present invention has a signi?
`bonding pads which eliminates the formation of inter
`cantly reduced stress and H content as opposed to
`metallic compounds at the boundaries of the different
`thicker prior art ?lms.
`metals, and which is compatible with TAB, Pb-Sn sol
`The present method for forming a sealed chip incor
`der, and lead attachment methods.
`porates both bonding pad passivation and chip surface
`Current semiconductor processes use a sawing pro
`passivation. Though each method may practiced sepa
`cess to divide the Si substrate upon which dielectric
`rately, the incorporation of both methods allows for the
`layers have been formed into a number of chips. Present
`creation of a superior sealed chip. By using both meth
`VLSI processes currently include the deposition of a
`ods a superior seal is formed over the entire surface of
`thick passivation layer over the dielectric layer.
`the semiconductor chip. Furthermore, by using both
`Though to some extent this layer protects the top of the
`methods multiple layers of chip sealant may be depos
`chip, the sawing process opens the sides of the chip and
`ited so as to form chips having multiple sealing layers
`thereby exposes the chip to moisture and other contami
`for use in harsh environments.
`nants. What is needed is a passivation method for form
`A method for chip surface passivation is described for
`ing semiconductor devices in which the sawing process
`forming sealed, moisture resistant chips for non-volatile
`will not open the sides of the chip to moisture or other
`memory products. The passivation layer of these chips
`contaminants.
`will be formed by a SiN layer which will allow the
`penetration of UV light. The formation of a SiN ?lm
`which will allow the penetration of UV light is
`achieved through the deposition of a thin ?lm of SiN by
`depositing the ?lm at a high ion bombardment levels at
`low temperatures using a PE-CVD deposition method.
`The passivation layer covers not only the top of the
`semiconductor chip, but also, it covers the sides of the
`semiconductor chip and a portion of the silicon sub
`strate top surface. This is achieved by etching the de
`vice layers so as to form individual chips upon the sili
`con surface. Then the passivation layer is deposited so
`as to cover the top and sides of each chip as well as the
`exposed silicon surface. Since the silicon substrate is
`resistant to moisture, this forms a moisture-resistant
`coating over the entire chip surface.
`Semiconductor integrated circuits are ?rst formed on
`a silicon wafer by the successive formation of a number
`of device layers composed of conductive layers and
`dielectric layers. The process steps for forming inte
`grated circuits include the formation of a number of
`bonding pads. These bonding pads are typically formed
`of Aluminum or its alloys. Mask and etch steps are then
`performed which isolate individual integrated circuit
`devices formed upon the wafer surface. This is done by
`performing etch steps which completely etch the device
`layers so as to expose portions of the silicon surface.
`The etch steps thus form and de?ne a number of semi
`conductor chips upon the silicon layer. Next, a thin SiN
`?lm is deposited over the surface of each chip and the
`wafer surface. The passivation layer will form a seal
`over the entire chip surface including the top of the Si
`surface, the sides of the device layers and the bonding
`pads. Next, mask and etch steps are performed so as to
`expose a portion of the metal of the bonding pad. Bond
`ing pad passivation is then performed by selectively
`
`SUMMARY OF THE INVENTION
`The present invention describes a process for passiv
`ation of semiconductor devices to protect those devices
`from environmental moisture and contaminants. Si is
`impervious to moisture at typical device operating tem
`peratures. Therefore, it is not necessary to form a her
`metic seal over the Si substrate. Thus, it is only neces
`sary to passivate the exposed dielectric layers and the
`bonding pads.
`A novel bonding pad passivation method is described
`which incorporates the use of selectively deposited
`metal, such as electroless Ni or Ni alloy. Not only does
`this Ni or Ni alloy act as a passivation material, but it
`also acts as diffusion barrier against inter metallic com
`pound formation between Al and Au or Pb-Sn solder.
`Thus, the present passivation method eliminates the
`need for elaborate Cr-Cu-Au multilayers required by
`convention bonding processes.
`In the preferred embodiment of the present invention
`a bonding pad passivation layer is formed of Ni or Ni
`alloy. Pb solder bumps can then be directly formed on
`the Ni surface. For example, those solder bumps may be
`formed by simply dipping the Ni passivated chip or
`wafer directly into a pot of molten solder. The molten
`solder will automatically wet the Ni surface to form
`solder bumps; thus greatly simplifying the bonding pro
`60
`cess. The barrier properties of the passivation layer can
`also be advantageous when the wire bonding and TAB
`process are used. Gold bumps are conventionally used
`.to bond the tape and the wires to the Al pads. Gold
`bumps can be directly formed on the nickel surface. For
`65
`example, gold bumps may be directly deposited in the
`Ni surface by the use of a wire bonder, additional wafer
`processing steps are not required. Thus, the use of a Ni
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`depositing a layer of Ni or Ni alloy over the bonding
`pad. The metal passivation layer may be deposited so as
`to form a planar upper surface. However, a superior
`seal may be formed by depositing the bonding pad pas
`sivation layer so as to form protruding metal passivation
`layer bumps. By using protruding metal passivation
`bumps, a better seal may be formed over the opening
`containing the bonding pad.
`In a second embodiment of the present invention, the
`metal passivation layer is deposited prior to deposition
`of the SiN passivation layer. In this embodiment, the
`SiN passivation layer seals the entire surface of the chip,
`including the Si wafer surface and the metal passivation
`layer. A subsequent etch step exposes the passivation
`metal for bonding.
`A third embodiment of the present invention incorpo
`rates multiple SiN passivation layers separated by other
`layers. These other layers may be layers of dielectric.
`These multiple layers could be integrated with multiple
`layers of metal passivation to form a chip which has a
`superior seal for use in harsh environments.
`In each of the above described embodiments the
`chips must be separated from each other. This is typi
`cally done by a mechanical sawing process. In the pre
`ferred embodiment of the present invention the wafer is
`sawed so that only the silicon surface itself and the SiN
`passivation layer is sawed.- Therefore, the dielectric
`layers and conductive layers which overlie the Si sub
`strate are not exposed by the sawing process. The end
`result is a semiconductor chip which is sealed by the
`dielectric passivation layer on all exposed portions of
`the chip, except for the Si substrate. Since the passiv
`ation layer forms a seal upon the top Si surface and since
`the Si substrate is impervious to moisture at device
`operating temperatures, a completely hermetically
`sealed semiconductor chip is created.
`
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`vidual chips and after the selective deposition of a metal
`passivation layer over the bonding pads.
`FIG. 10 shows a cross-sectional view of the semicon
`ductor wafer of FIG. 9 after the deposition of a thin
`silicon nitride passivation layer.
`FIG. 11 shows an enlarged view of the left semicon
`ductor chip illustrated in FIG. 10 after the etch of the
`silicon nitride passivation layer.
`FIG. 12 shows a third embodiment which illustrates a
`semiconductor chip having multiple passivation layers
`FIG. 13 shows a fourth embodiment which illustrates
`a semiconductor chip having multiple passivation layers.
`DETAILED DESCRIPTION
`1. Apparatus And Process For Forming A Sealed Chip
`An invention is described for a sealed chip and a
`process for forming a sealed chip. The sealed chip will
`provided reliable protection for advanced VLSI chips
`without the need for expensive and complicated her
`metically sealed packages, and will reduce the cost,
`weight, and size of the ?nal product. The method and
`apparatus described is compatible with all standard
`assembly technologies such as wire bonding, solder
`bumping, and tape automated bonding (TAB). Further
`more, when used with solder bumps and tape automated
`bonding, the present invention can dramatically sim
`plify the assembly process.
`_
`In the following description, numerous speci?c de
`tails are set forth such as speci?c thicknesses, materials,
`and speci?c deposition processes, etc. in order to pro
`vided a thorough understanding of the present inven
`tion. It will be obvious, however, to one skilled in the
`art that the present invention can be practiced without
`these specific details. In other instances, well-known
`process steps have not been described in detail in order
`not to unnecessarily obscure the present invention.
`Presently, semiconductor integrated circuits are man
`ufactured by the deposition and etch of a number of
`layers upon a silicon (Si) wafer. For example, device
`regions are formed within the Si wafer. Layers of con
`ductive and non conductive material are then deposited
`over the device regions, masked and etched to form
`semiconductor devices. These devices are then con
`nected by the use of conductive layers. These conduc
`tive layers are typically metal layers which are depos
`ited, masked and etched to form interconnects. Subse
`quent layers are formed so as to de?ne additional de
`vices and interconnects. Though the present invention
`is described with reference to the use of metal layers,
`one with skill in the art would realize that a number of
`other conductive materials could be used to form con
`ductive layers. A top dielectric layer is then typically
`deposited over the top conductive layer to planarize
`and insulate the electrical devices and interconnects.
`FIG. 1 shows a typical cross-section of a semiconductor
`wafer which incorporates this technology. This ?gure
`illustrates the Si wafer 1 upon which dielectric layers 2,
`3 and 4 have been formed by methods well-known in
`the art. The ?gure shows three metal layers which have
`been deposited, masked, and etched to form metal lay
`ers 5-10. Metal layers 5-10 overlie device regions so as
`to connect the various devices and the subsequently
`deposited metal layers. A layer of dielectric is then
`deposited over the top conductive layer to planarize the
`upper surface and to prevent the leakage of electrical
`current through the passivation layer. FIG. 1 shows top
`dielectric layer 11 deposited over the semiconductor
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a cross-sectional view of a semiconductor
`wafer upon which various conductive layers and dielec
`tric layers have been formed.
`FIG. 2 is a cross-sectional view of a semiconductor
`wafer illustrating the prior art method for forming com
`puter chips.
`45
`FIG. 3 is a top view of a semiconductor wafer upon
`which conductive layers including interlevel metal lay
`ers, and dielectric layers have been formed and etched.
`FIG. 4 is a cross-sectional view of a semiconductor
`wafer along axis 500-500 of FIG. 3 upon which con
`ductive layers including interlevel metal layers, and
`dielectric layers have been formed and etched.
`FIG. 5 is a cross-sectional view of a semiconductor.
`wafer having the structure shown in FIG. 4 after depo
`sition of a SiN passivation layer.
`FIG. 6 is a cross-sectional view of a semiconductor
`wafer having the structure shown in FIG. 5 after the
`etch of the SiN passivation layer.
`FIG. 7 is an enlarged cross-sectional view of the left
`side of a semiconductor wafer having the structure
`shown in FIG. 6 after the selective deposition of a metal
`passivation layer.
`FIG. 8 is a cross-sectional view of a semiconductor
`wafer having the structure shown in FIG. 7 which
`illustrates the sawing step.
`FIG. 9 shows a cross—sectional view of a second em
`bodiment of a semiconductor wafer along axis 500-500
`of FIG. 3 after mask and etch steps have de?ned indi
`
`60
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`65
`
`50
`
`55
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`

`

`20
`
`25
`
`30
`
`5,300,461
`7
`surface. Typically, a large number of integrated circuit
`devices are formed upon any semiconductor wafer. For
`example, in this illustration, dielectric layers 2, 3, 4, and
`11 and metal layers 5, 6 and 7 would be part of an inte
`grated circuit device which is separate from a second
`integrated circuit device which comprises metal layers
`8, 9 and 10, the dielectric layers 2, 3 and 4, and 11.
`FIG. 2 shows the prior art method for formation of a
`' semiconductor chip. In this prior art method the inte
`grated circuit devices formed on the wafer surface are
`separated by a sawing process. This sawing process cuts
`the silicon substrate and all of the overlying layers to
`form a number of chips, each of which includes an
`integrated circuit device. FIG. 2 shows integrated cir
`cuit devices illustrated in FIG. 1 over which thick pas
`sivation layer 20 has been deposited. Current VLSI chip
`processes use a thick layer of sealant as a passivation
`layer. This thick layer is typically 1 pm or greater in
`thickness. An etch step is then performed to form open
`ings in the thick passivation layer and the top dielectric
`layer 11 which expose bonding pads. FIG. 2 shows
`bonding pads 21-24 de?ned by openings in top dielec
`tric layer 11 and thick passivation layer 20., Saw cuts 25
`and 26 isolate the integrated circuit device comprising
`dielectric layers 2, 3 and 4, metal layers 5, 6, and 7, and
`dielectric layer 11 so as to form computer chip 28. This
`computer chip may be connected to outside devices,
`power sources, etc. by contact made to bonding pads 21
`and 22. Saw cuts 26 and 27 isolate a second insulated
`circuit device comprising dielectric layers 2, 3 and 4,
`metal layers 8, 9, and 10, and dielectric layer 11 so as to
`form computer chip 29.
`Though the sawing step does isolate the device layers
`so as to form two separate chips, the sides of the chips
`will be rough, non-uniform, and susceptible to damage
`35
`due to moisture and other contaminants entering
`through the exposed side edges of the chip. Current
`methods for protecting the chip and hermetically seal
`ing the chip involve placing the chip into a package
`which performs the function of protecting and sealing
`40
`the sides of the chip. Hermetically sealed packages such
`as ceramic pin grid packages typically are used to pro
`tect the chips. These packages are large, bulky and
`expensive. An additional disadvantage associated with
`prior art process is the fact that the thick SiN passiv
`ation layer puts underlying layers under a high stress
`which causes stress migration in the interconnects. Fur
`thermore, the deposition of the thick layers of SiN
`forms a signi?cant amount of hydrogen (H) which
`causes device degradation.
`The present invention avoids many of these problems
`by isolating and passivating each chip before the sawing
`of the silicon wafer. FIG. 3 illustrates a semiconductor
`wafer upon which integrated circuit devices have been
`formed and an isolated by the methods of the present
`invention. Computer chips 30 and 31 are shown to be
`formed upon the silicon substrate 1. Each of the com
`puter chips which are formed on the silicon substrate 1
`will contain a large number of bonding pads such as
`bonding pads 11-14 which are formed on computer
`chip 30. Side surfaces 32, 33, 36 and 37 which are
`formed by the etch steps described below isolate the
`computer chip 30. Similarly, computer chip 31 is iso
`lated by side surfaces 34, 35, 38 and 39.
`First, an etch step is performed so as to isolate each of 65
`the integrated circuit devices. This step will etch each
`of the conductive layers 2-4 and the top dielectric layer
`11 so as to expose a portion of the surface of the Si
`
`8
`substrate 1. This etch need not be a separate etch step
`requiring an additional process step since the etch can
`be performed during typical wafer processing etch
`steps. Though the ?gure illustrates the use of a single
`etch, the preferred embodiment of the present invention
`would use a number of standard processing etch steps to
`de?ne the scribe lanes and side surfaces 34-39. Prefera
`bly, as each successive device layer is etched during
`standard chip processing, the scribe lanes and the sides
`of the chip are simultaneously etched. The etch step
`illustrated in FIG. 4 shows side surfaces 32, and 33
`which isolate the computer chip 30 and the integrated
`circuit device which is formed therein. The etch step
`has also formed side surfaces 34 and 35 which isolate the
`computer chip 31 and the integrated circuit device
`formed therein. This etch step or a separate etch step
`will form openings in the top dielectric layer 11 so as to
`expose and de?ne bonding pads. FIG. 4 shows bonding
`pads 41-44 formed by this etch. Of course, the side
`surfaces 34 and 35 need not be vertical. Though side
`surfaces 34 and 35 are shown to be vertical, they may
`also be sloped. In fact, the use of sloped side surfaces
`formed by a number of successive standard etch steps
`may give a more effective seal as improved step cover
`age may be obtained for the SiN layer.
`Next, a layer of passivation material is deposited over
`the wafer surface. FIG. 5 illustrates the structures
`shown in FIG. 4 after passivation layer 40 has been
`deposited over the entire wafer surface. In the preferred
`embodiment of the present invention, a very thin layer
`of SiN is used as a passivation layer to seal the computer
`chip. In the preferred embodiment of the present inven
`tion, this passivation layer is approximately 1000 ang
`stroms or less. Though the present invention uses SiN,
`other compatible materials which are moisture resistant
`may be used to‘form a sealed chip. Though the structure
`of the present invention may be formed by the use of
`other moisture resistant ?lms, the preferred embodi
`ment uses a thin ?lm made of SiN. This ?lm is used
`because of its excellent moisture resistant qualities and
`its good step coverage. Furthermore, the use of a thin
`SiN ?lm minimizes H-content and stress related prob
`lems.
`One object of the present invention is the formation
`of a sealed chip having a passivation layer which is
`moisture resistant and which is UV transparent. Prior
`art thick layers of silicon nitride are not transparent to
`UV light. Currently, non-volatile memories do not use
`PE-CVD nitride as a passivation layer because UV light
`with a wave length centered around 250 nm is used in
`EPROM for erasing and in FLASH memory for initial
`ization. For this reason SiON is typically used for a
`passivation layer in non-volatile memory products. PE
`CVD SiON is made UV transparent by properly adjust
`ing the O/N ratio. SiON is, however, not as good a
`passivation layer as SiN as it is less moisture resistant. It
`has been reported recently that the UV absorption in
`PE-CVD SiN is primarily due to its high l-l-content.
`More speci?cally, it is due to high concentration of
`Si-H bonds. Since Si-H bonds are weaker th