UTILITY
`SERIA
`NUMB
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`PATENT DATE
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`PATENT
`NUMBER
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`SERIAL NUMBER (cid:9)
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`FILING DATE
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`SUBCLASS
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`GROUP ART UNIT
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`Foreign priority claimed
`35 USC 119 conditions met
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`Verified and Acknowledged
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`Ex
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`AS
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`STATE OR
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`Assistant Examiner
`
`U.S. DEPT. OF COMM.! PAT. & TM—PTO-438L (Rev.12-94)
`
`Applications Examiner
`CLAIMS ALLOWED
`Total Claims
`Print Claim
`
`DRAWING
`Sheets Drwg. Figs. Drwg.
`
`Print Fig.
`
`VIIIMINIMIN
`
`Primary Examiner
`PREPARED FOR ISSUE '
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`WARNING: (cid:9) The information disclosed herein may be restricted. Unauthorized disclosure may be prohibited
`by the United .States Code Title 35, Sections 122, 181 and 368. (cid:9) Possession outside the U.S.
`Patent & Trademark Office is restricted to authorized employees and contractors only.
`
`Label
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`
`Form PTO-436A
`(Rev. 8/92)
`
`IPR2015-01087 - Ex. 1009
`Micron Technology, Inc., et al., Petitioners
`1
`
`

`
`U.S. File Wrapi per:
`,r-2
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`'12
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`File Wrapper Continuation of:
`09/c/9 (600 (cid:9)
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`pp 11,1 (cid:9)
`
`149
`
`(cid:9)
`

`
`PATENT APPLICATION SERIAL NO.
`
`Os/514800
`
`U.S. DEPARTMENT OF COMMERCE
`PATENT AND TRADEMARK OFFICE
`FEE RECORD SHEET
`
`250 BB 0?/08/,;5 06514HO
`1. (cid:9)
`71).00 Cr: 14S F4/6084
`
`PTO-1556
`(5/87)
`
`

`
`TBE1 Ça1ISŠIcÑ , OF PATENTS2.L..RADEMARKS
`WgShingtOn, D.C. (cid:9)
`20231
`-
`
`0 8/514 800
`1.10k.xet No. V_LS_cA_x_LR
`
`as
`
`11ZUE.
`Transmiaed herewith for filing is the Patent Application of:
`
`Inventor: )41,01e/ - (cid:9)
`W LAD / C14 a NI - c }-FERN.C-4-Rovi rrÑ61 c Nov I 6 1-41,04c)- MIN1,61
`- (cid:9)
`LEE; C: 1411,t E0Q, NAN C: 4-111h4
`s-rRuc_Tu FeE (cid:9)
`1-ElD Ft .t (cid:9)
`
`"P—E-PAX R
`
`For:
`
`Enclosed are:
`1-71 ;I (cid:9)
`sheets of drawing(s).
`571 An assignment of the invention to Aplewmac> . :114-11e$anliAlrallotslAL LE
`-
`bal*ernAlioNV
`A certified copy of a (cid:9)
` application.
`
`I CO 14 t)U-CTOt
`
`An associate power of attorney.
`
`The filing fee has been calculated as shown below:
`
`(Col. 1) (cid:9)
`
`(Col. 2)
`
`OTHER THAN A
`SMALL EVEITY
`
`FOR:
`
`BASIC FEE
`
`TOTAL CLAIMS
`
`1E5 -20=
`
`INDEP CLADS
`
`2 - 3
`1 MULTIPLE DFPENDENT CLAIM PRESENTED
`
`1
`
`x
`
`+22.0=
`
`* If the difference in Col. 1 is less than zero,
`enter "0" in Col. 2. (cid:9)
`
`SUB TCTAL
`
`ASSIGNMENT (4.6.00)
`
`TOTAL
`
`-770,
`
`Please charge my Deposit Account No. (cid:9)
`A duplicate copy of this sheet is enclosed.
`
` in the amount of $ (cid:9)
`
`
`
`The Commissioner is hereby authorized to charge payment of, the following fees
`associated with this co=ication or credit any overpayment to Deposit Account
`. A duplicate copy of this sheet is enclosed.
`No. (cid:9)
`
`Any additional filing fees required under 37 CFR 51.16.
`1 Any patent application processing fees under 37 CFR §1.17.
`Respectfully sUbmitted,
`a
`
`By, (cid:9)
`
`.4'EORO (cid:9)
`
`. SAILE
`
`j
`
`Registration No. 19572
`
`

`
`4-008
`
`RAISED FUSE STRUCTURE FOR LASER REPAIR
`
`E17,7
`BACKGROUND OF THE INVENTION
`
`(1) FIELD OF THE INVENTION
`
`The invention relates to the general field of semiconductor
`
`integrated circuits, more particularly to circuits that may be
`
`personalized, repaired or modified by means of fusible links.
`
`(2) DESCRIPTION OF THE PRIOR ART
`
`Semiconductor integrated circuits (ICs) that have optimum
`
`density and/or performance cannot, in general, be repaired or
`
`modified. (cid:9)
`
`There exists, however, a large class of ICs that are
`
`intended to be repairable and/or modifiable. (cid:9)
`
`In certain cases,
`
`no real circuit exists until the IC' has been personalized by
`
`breaking certain connections, thereby determining how the
`
`components are to be connected to one another.
`
`One method for realizing circuits of this type is to arrange
`
`

`
`VIS84-008
`
`for some of the connections between components to be capable of
`
`being permanently removed (opened) as desired. The portion of
`
`such a connection that is actually physically removed is referred
`
`to as a fusible link.
`
`In general, the method for removing a particular fusible
`
`link comprises heating it briefly, but with sufficient intensity
`
`so that it vaporizes without appreciably heating other circuitry
`
`in its. vicinity. Delivery of the heat pulse that is required to
`
`produce the selective vaporization of any particular fusible link
`
`is achieved in one of two ways. An X-Y addressing scheme may be,
`
`used to deliver a high current pulse to the link so that
`
`vaporization occurs as a result of Joule heating or a high energy
`
`beam of intense laser light may be directed at the surface of the
`
`fusible link for a short time.
`
`A common problem, associated with both methods of vaporizing
`
`fusible links, is that some, or all, of the debris that is a
`
`byproduct of said vaporization process recondenses on the surface
`
`of the IC and may cause short circuiting. This is commonly dealt
`
`with by coating the entire integrated circuit with a layer of
`
`insulation as a final step in the manufacturing process, thereby
`
`electrically isolating it from any conductive material that may
`
`recondense on it. Said final layer of insulation also covers the
`
`fusible links, thereby increasing the mass of material that must
`
`2
`
`

`
`VIS84 -008
`
`be vaporized whenever a particular link is to be blown.
`
`Ideally, all the heat energy that is directed at a
`
`particular fusible link will be used for effecting its
`
`vaporization. In practice, some of this energy will be conducted
`
`into the substrate, or main body of the integrated circuit, away
`
`from the fusible link. (cid:9)
`
`Thus it will not be available for the
`
`vaporization process and, additionally, it may have an
`
`undesirable effect on the integrated circuit itself. (cid:9)
`
`This
`
`phenomenon can lead to a narrowing of the process window that is
`
`available for heating the link -- too little energy and
`
`vaporization of the link is incomplete, too much energy and
`
`surrounding circuitry gets damaged.
`
`A number of issued patents address various aspects of these
`
`two problems. (cid:9)
`
`Takagama (U.S. Patent 4,536,949 AUG 1985) is
`
`concerned with electrical (as opposed to laser) fusing. (cid:9)
`
`The
`
`fusible link sits at the bottom of a deep trench on whose walls
`
`the products of vaporization are expected to condense, thereby
`
`keeping them away from other parts of the integrated circuit.
`
`Billig et'al. (U.S. Patent 5,025,300 JUN 1991) is concerned with
`
`laser fused links and is similar to Takagama in that the link
`
`lies at the bottom of a trench. (cid:9)
`
`Unlike Takagama, Billig also
`
`makes use of a final protective layer of insulation.
`
`

`
`VIS84-008
`
`Monotami et al. (U.S. Patent 5,241,212 AUG 1993) also place
`
`the fuse in a trench but the protective layer stops at the
`
`trench's top edge, thereby leaving the link itself exposed. The
`
`upper surface of the fusible link is level with the bottom of the
`
`trench. (cid:9)
`
`In an alternative, optional, embodiment, a layer of
`
`insulation 6-8,000 Angstrom units thick is deposited over the
`
`fuse. (cid:9)
`
`The fuse is heated through laser energy, most of which
`
`passes through this optional layer.
`
`An example of a fusible link structure of the type found in
`
`the prior art is shown in FIG. 1 as a schematic cross-section.
`
`The fusible link (layers 3 and 4) lies on silicon dioxide layer 2
`
`which has been formed on the surface of silicon substrate 1 which
`
`comprises the integrated circuit. (cid:9)
`
`The fusible link has been
`
`overcoated with passivation layers 5 and 6.
`
`Experiments on fusible link structures such as the one
`
`illustrated in FIG. 1 have shown that the range over which the
`
`applied laser energy may vary is quite narrow. For example, as
`
`shown in FIG. 3, over an energy range of from 0 to 2 microjules,
`
`the minimuM energy required to cause links to open up was found
`
`to be about 0.5 microjoules. (cid:9)
`
`However, between 0.5 and 1
`
`microjoule, the resistance of links that had been subjected to
`
`laser pulses was found to vary over a wide range, from short to
`
`open circuits. (cid:9)
`
`Between 1 and 1.5 mdcrojoules, links that had
`
`4
`
`

`
`VIS84-008
`
`been subjected to laser pulses were consistently found to have
`
`open circuited, as intended. (cid:9)
`
`However, in the range of from 1.5
`
`to 2 microjoules, a wide variation in link resistance, similar to
`
`what was seen for the 0.5 to 1 microjoule range, was again seen.
`
`In the latter case, the cause was identified as being the result
`
`of heat reaching the underlying silcon substrate in amounts
`
`suficient to melt some of the silicon, which then contributed to
`
`the recondensed debris.
`
`It should also be noted that, for laser heated links in
`
`general, the duration of the laser pulse will always be slightly
`
`longer than the minimum time needed to cause the link to explode.
`
`This is inevitable, given that the exact energy needed varies
`
`slightly from link to link. (cid:9)
`
`As a consequence, the underlying
`
`material on which the link rested prior to its explosion will be
`
`directly exposed to the laser for a short time.
`
`SUMMARY OF THE INVENTION
`
`It is an object of the present invention to provide a
`
`fusible link structure, opened via laser irradiation, said
`
`opening process to have no side effects, such as occasional short
`
`circuiting.
`
`5
`
`

`
`VIS84-008
`
`A further object of the present invention is to provide a
`
`fusible link that may be opened by means of laser irradiation
`
`over a wide range of laser energies.
`
`Yet another object of the present invention is to provide a
`
`probess for manufacturing a fusible link having these
`
`characteristics, said process to cost little or nothing more than
`
`the processes used to manufacture other types of fusible link.
`
`These objects have been achieved in a structure in which the
`
`fusible link is located on a pedestal that raises it above the
`
`surface - of the main body of the integrated circuit, thereby
`
`providing a measure of thermal isolation for the fuse when it is
`
`irradiated by the laser. (cid:9)
`
`A process for manufacturing this
`
`structure is described in which the link acts as its own self-
`
`aligned mask during the formation of said pedestal.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a schematic cross-section of a fusible link
`
`structure based on prior art.
`
`FIG. 2 is a schematic cross-section of a fusible link
`
`structure based on the present invention.
`
`6
`
`

`
`VIS84-008
`
`FIGs. 3 and 4 show the results of laser irradiation of the
`
`designs of FIGs. 1 and 2 respectively, over a range of incident
`
`laser energies.
`
`DESCRIPTION OF THE PREFERRED EMBODIMENTS
`
`We will now describe a typical embodiment of the present
`
`invention which overcomes the deficiencies in the prior art that
`
`were described above. Referring to FIG. 2, we show, in
`
`schematic cross-section, a pedestal 10, of silicon oxide, resting
`
`on layer 12 of the same material. (cid:9)
`
`Layer 12 lies on the surface
`
`of silicon substrate 11, which comprises the integrated circuit.
`
`While silicon oxide is the preferred material for pedeàtal 10,
`
`the invention will still operate successfully with any similar
`
`material that has relatively low thermal conductivity. (cid:9)
`
`For
`
`successful operation, the thickness of the pedestal may range
`
`from about 1,000 to 9,000 Angstrom units, about 5,000 Angstrom
`
`units being preferred. (cid:9)
`
`The thickness of insulating layer 12
`
`immediately beneath the pedestal is typically about 4,000
`
`.Angstrom units, but any thickness in the range of about 1,000 to
`
`10,000 Angstrom units would be satisfactory.
`
`The fusible link itself comprises two layers. (cid:9)
`
`Layer 13
`
`7
`
`

`
`VIS84-008
`
`comprises polycrystalline silicon, heavily doped to increase its
`
`conductivity. Typically, the dopant used was phosphorus at an
`
`implanted dose of about 5x1015 atoms/sq. cm. Although layer 13
`
`could have a thickness in the general range of from 100 to 2,000
`
`Angstrom units, we have typically used a value of about 500
`
`Angstrom units. Layer 14 comprises tungsten suicide, deposited
`
`through chemical vapor deposition, typically about 1,500 Angstrom
`
`units thick, although any thickness in the range of about 500 to
`
`3,000 Angstrom units would be satisfactory.
`
`In order to manufacture the structure of FIG. 2, layers 2,
`
`3, and, 4 (as shown in FIG. 1) were first deposited onto the $
`
`surface of the integrated circuit. Thereafter, the fusible link
`
`(comprising layers 3 and 4 in FIG. 1) was patterned, using
`
`conventional photolithographic techniques, into appropriate
`
`shapes that served to connect various parts of the integrated
`
`circuit that might, or might not, be severed at a later time, as
`
`needed. The patterned fuse links were now used as self-aligned
`
`masks while about 5,000 Angstrom units of layer 2 were etched
`
`away. (cid:9)
`
`This was followed by the deposition of passivating layers
`
`15 and 16; giving the finished structure the appearance shown in
`
`FIG. 2.
`
`Note that (in FIG. 2) layer 15 comprises about 2,000
`
`Angstrom units of boro-phosphosilicate glass, although any
`
`

`
`VIS84-008
`
`thickness in the range from 0 to about 7,000 Angstrom units would
`
`work, while layer 16 comprises about 6,500 Angstrom units of
`
`silicon nitride (deposited by means of Plasma Enhanced Chemical
`
`Vapor Deposition) although any thickness in the range from 0 to
`
`about 7,000 Angstrom units would still work.
`
`In order to evaluate the invention and, particularly, to
`
`compare it to the prior art, a structure embodying the present
`
`invention (as illustrated in FIG. 2) was compared with a
`
`structure of the type illustrated in FIG. 1. The thicknesses of
`
`the various layers involved was the same in both cases, the
`
`principal difference being the pedestal geometry of the present
`
`invention versus the planar geometry of the prior art example.
`
`The laser used for effecting the explosion of the fusible
`
`links was a 1047 nm Q-switched Nd-doped Yttrium Lanthanum
`
`Fluoride (YLF) laser. The laser energy was normally in the range
`
`between 0.8 and 1.2 microjoules with a spot diameter of 5 microns
`
`and a pulse width of 35 ns. To determine whether or not a given
`
`link had been successfully blown, an electrical continuity
`
`measurement was performed by applying a constant voltage across
`
`the blown fuse and then measuring the passing current. The fuse
`
`was considered to have been blown successfully (be in an open
`
`state) if the measured resistance was greater than 10 megohms.
`
`9
`
`

`
`VIS84-008
`
`The results of the above described experiments are
`
`illustrated in FIGs. 3 and 4. (cid:9)
`
`FIG. 3 is for the planar (prior
`
`art) structure. Four distinct regions are shown in the figure,
`
`each reflecting different explosion characteristics of the links.
`
`In the region of 0 to 0.5 microjoules, the resistance
`
`measurements always showed a shorted state, indicating that the
`
`incident laser energy was below the threshold level needed to
`
`evaporate the fusible link (and the passivating layers above it).
`
`In the region of 0.5 to 1.0 microjoules, a wide range of
`
`resistance values was observed. (cid:9)
`
`In this energy range the laser
`
`heating produced a liquid pressure high enough to fracture the
`
`passivating layers. However, due to strong optical absorption by
`
`both the silicide layer and the passivating layers, some of the
`
`ejected link material may be redeposited around the crater and
`
`lead to full or partial short circuiting.
`
`In the region of 1.0 to 1.5 microjoules the process worked
`
`as intended and an electrically open state was obtained for all
`
`cases. (cid:9)
`
`This implies that the applied energy was sufficient to
`
`fully vaporize the link and direct the debris away from the
`
`crater.
`
`In the region of 1.5 to 2.0 microjoules, the resistance was
`
`again found to vary over a substantial range, similar to that
`
`10
`
`

`
`VIS84-008
`
`observed for the 0.5 to 1.0 microjoules region. Cross-sectional
`
`micrographs showed that this was due to laser energy having
`
`caused the underlying silicon substrate to become heated to a
`
`sufficient degree for some of it to be evaporated and contribute
`
`to the debris.
`
`The above results illustrate that, with the planar design of
`
`the prior art, the process window for laser energy application is
`
`rather narrow. In contrast, consider the results illustrated in
`
`FIG. 4 which are for a fusible link structure based on the
`
`present invention. As can be seen, once the threshold energy of
`
`0.5 microjoules has been exceeded, all links, after laser induced
`
`explosion, were found to be fully open circuited, independent of
`
`the laser energy, to at least 2 microjoules. (cid:9)
`
`These results
`
`confirm that the pedestal design df the present invention serves
`
`to confine the laser induced heat to the immediate vicinity of
`
`the fusible link, thereby greatly minimizing the side-effects
`
`associated with the planar design.
`
`While the invention has been particularly shown and described
`
`with reference, to this preferred embodiment, it will be
`
`understood by those skilled in the art that various changes in
`
`form and details may be made without departing from the spirit
`
`and scope of the invention.
`
`What is claimed is:
`
`11
`
`

`
`(cid:9) (cid:9)
`
`10
`
`VIS84 -008
`
`1. A fusible link structure, that is part of a
`
`semiconductor integrated circuit, comprisi g:
`
`a semiconductor substrate, includ4ig said integrated
`
`circuit;
`
`a first insulating layer o said semiconductor
`
`substrate;
`
`a pedestal, having top d bottom surfaces and
`
`comprising the same material as aid first insulating layer,
`
`said bottom surface resting on said first insulating layer;
`
`a layer of fusible mat rial on the top surface of said
`
`pedestal, patterned into a Aine shape and connected to said
`
`integrated circuit; and
`
`a second insula (cid:9)
`
`laye that covers said fusible
`
`layer, said pedestal, (cid:9)
`
`• aid first insulating layer.
`
`15 (cid:9)
`
`2. (cid:9)
`
`The structure of claim 1 wherein said layer of fusible
`
`material further comprises a layer of polycrystalline
`
`silicon, in con act with the top surface of said pedestal,
`
`and a layer •f tungsten silicide over said layer of
`
`polycrystalli e silicon.
`
`20 (cid:9)
`
`3. (cid:9)
`
`The s ucture of claim 2 wherein the thickness of said
`
`layer of polycrystalline silicon is between about 100 and
`
`about 2,000 Angstrom units and the thickness of said layer
`
`of tu gsten suicide is between about 500 and about 3,000
`
`12
`
`

`
`VIS84 -008
`
`Angstrom units.
`
`4. The structure of claim 1 wherein sai4 second insulating
`
`layer further comprises a layer of boro-phosphosilicate
`
`glass in contact with said layer of usible material, said
`
`5 (cid:9)
`
`pedestal, and said first insulating layer, overcoated with
`
`a layer of silicon nitride.
`
`5. The structure of cl (cid:9)
`
`wherein the thickness of said
`
`layer of boro-phosphos (cid:9)
`
`te g ss is between 0 and about
`
`7,000 Angstrom units (cid:9)
`
`the thickness of said layer of'
`
`10 (cid:9)
`
`silicon nitride is betw (cid:9)
`
`0 and about 7,000 Angstrom units.
`
`6. The structure of claim 1 wherein the thickness of said
`
`first insulating layer is between about 1,000 and about
`
`10,000 Angstrom units.
`
`7. The st ucture of claim 1 wherein said first insulating
`
`15 (cid:9)
`
`layer com ises silicon oxide.
`
`8. (cid:9)
`
`T e structure of claim 1 wherein the thickness of the
`
`pede al is between about 1,000 and about 9,000 Angstrom
`
`uni
`
`9. (cid:9)
`
`A method for manufaciir
`
`
`a fusible link structure
`
`13
`
`

`
`VIS84-008
`
`comprising:
`
`providing a silicon int rated circuit;
`
`depositing a first i. ulating layer;
`
`depositing a f si (cid:9)
`
`link layer;
`
`5 (cid:9)
`
`patterning (cid:9)
`
`link layer into a shape that is
`
`suitable for it (cid:9)
`
`part of the integrated circuit;
`
`using sa patterned fusible link layer as a mask,
`
`removing p t of said first insulating layer, thereby
`
`forming (cid:9)
`
`10 (cid:9)
`
`layer (cid:9)
`
`es; and
`
`pedestal on which said patterned fusible link
`,4
`
`then coating the structure with a second insulating
`
`er.
`
`)tr. The method of claimX wherein said first insulating
`
`layer comprises silicon oxide.
`
`11. The method of c
`
`whereirqthe step of depositing
`
`said second insulatin
`
`further comprises depositing a
`
`layer of boro-phosphi7j licate glass and then depositing a
`
`layer of silicon nit ide.
`
`.1.e. The method of claim .9". wherein said second insulating
`
`20 layer is deposited to a thickness that is between 0 and
`
`about 14,000 Angstrom units.
`
`14
`
`

`
`tio
`
`VIS84 -008
`
`13. The method of c aim wherein the step of depositing a
`
`layer of fusible fri. further comprises depositing a
`
`layer of polycryst me silicon and then depositing a layer
`
`1 (cid:9)
`
`of tungsten sil ide.
`
`($7
`
`5 (cid:9)
`
`The method of claim )Y wherein the fusible link is
`
`deposited to a thickness that is between about 5,00 and
`
`about 5,000 Angstrom units.
`
`15. The method of claim 9 wherein the thickness of the part
`
`of said first insula (cid:9)
`
`la er that is removed in order to
`
`10 (cid:9)
`
`form a pedestal ise een about 1,000 and about 9,000
`
`Angstrom units.
`
`1 5
`
`

`
`VIS84 -008
`
`ABSTRACT
`
`A novel raised polycide fusible link structure is described.
`
`This structure enables a highly reliable laser-cutting process to
`
`be used in which the fuse can be easily and totally severed over
`
`a wide range of laser energy levels. The primary feature of the
`
`structure is that the fusible link is located on a pedestal that
`
`raises it above the surface of the main body of the integrated
`
`circuit, thereby providing a measure of thermal isolation for the
`
`fuse when it is irradiated by the laser. An efficient process
`
`for manufacturing the structure is also described.
`
`16
`
`

`
`DECLARATION A; DWER OF ATTORNEY FOR PATENT AP. ATION Dom& No.
`VIS 84-008
`
`As a below named inventor, I hereby declare that:
`My residence, post office address and citizenship are as stated below next to my name:
`I believe I am the original, first and sole inventor (if only one name is listed below) or an original, first and joint
`inventor (if plural names are listed below) of the subject matter which is claimed and for which a patent is sought on
`the invention entitled
`RAISED FUSE STRUCTURE FOR LASER REPAIR
`the specification of which (check one)•
`El is attached hereto.
`El was filed on
`as Application Serial No.
`and was amended on
`
`(if applicable)
`I hereby state that I have reviewed and understand the contents of the above identified specification, including the
`Claims, as amended by any amendment referred to above.
`I acknowledge the duty to disclose information which is material to the examination of this application in accordance
`with Title 37, Code of Federal Regulations, § 1.56(a).
`I hereby claim foreign priority benefits under Title 35, United States Code, § 119 of any foreign application(s) for
`patent or inventor's certificate listed below and have also identified below any foreign application for patent or
`inventor's certificate having a filing date before that of the application on which priority is claimed:
`Priority is Claimed:
`Prior Foreign Application(s)
`Dies
`
`EN°
`
`• (Number)
`
`(Number)
`
`(Country)
`
`(Country)
`
`(Day/Month/Year Filed)
`
`(Day/Month/Year Filed)
`
`EYes
`
`EN°
`
`[]Yes
`
`EINo
`
`(Day/Month/Year Filed)
`(Country)
`(Number)
`I hereby claiin the benefit under Title 35, United States Code, § 120 of any United States application(s) listed below
`and, insofar as the subject matter of each of the claims of this application is not disclosed in the prior United States
`application in the manner provided by the first paragraph of Title 35, United States Code, § 112, I acknowledge the
`duty to disclose material information as defmed in Title 37, Code of Federal Regulations, § 1.56(a) which occurred
`between the filing date of the prior application and the national or PCT international filing date of this
`application :
`
`(Application Serial No.)
`
`(Filing Date) (cid:9)
`
`(Status)(patented, pending, abandoned)
`
`I
`
`(Status)(patented, pending, abandoned)
`(Filing Date) (cid:9)
`(Application Serial No.) (cid:9)
`I hereby declare that all statements made herein of my own knowledge are true and that all statements made on
`information and belief are believed to be true; and further that these statements were made with the knowledge that
`willful false statements and the like so made are punishable by fine or imprisonment, or both, under Section 1001 of
`Title 18 of the United States Cade and that such willful false statements may jeopardize the validity of the application
`or any-patent issued thereon.
`POWER OF ATTORNEY: As a named inventor, I hereby appoint the following attorney(s) and/or agent(s) to
`prosecute this application and transact all business in the Patent and Trademark Office connected therewith. (list
`,tname & registration no.)
`(GEORGE O. SAME (Registration No. 19572)
`Send Correspondence to :
`ou hkeepsie, New York
`20 McInt
`• I
`Direct Telephone Calls to: (naip ‘ & telephone number) George 0. Saile
`Full name of sole or first invytor
`
`New York (914) 452-5863
`
`7 .
`colg gePti, (cid:9)
`- 7>4 1 ri
`No. 123 Lin-San Road, Kung-Cheng LaRuey-Tung, Yee-Lan County, Taiwan, R.O.C. 7-kvA
`
`Inventor' ignature
`
`Reside e (cid:9)
`
`Citizenship
`Taiwan, Republic of China
`Post Office Address
`No. 123 Lin-San Road, Kung-Cheng Li, Ruey-Tung, Yee-Lan County, Taiwan, R.O.C.
`
`

`
`DOCKET NO. VIS 84-008
`
`Full name of second joint-inve ttr, if any
`Chin -Chern
`ou
`gventor's sig ture
`Sec (cid:9)
`
`Residen
`No. 43-3 9th Lin, Da-Ping han-Wang Shiang, Miao-Li County, Taiwan, R.O.C.
`Citizenship
`
`6-41 • (cid:9)
`
`Post Office Address:
`No. 43-3 9th Lin, Da-Ping, Shan-Wang Shiang, Miao-Li County, Taiwan, R.O.C.
` .inventor, if any
`Full name of Third jot
`TingtChau (cid:9)
`
`Third Inventor's signature (cid:9)
`t
`
`ResideVe
`4F No.91-1 Chern-Kong Road, Sean ,Tzee-Shin Li,iNe-Hu Taipei County, Taiwan, R.O.C.
`Citizenship
`Taiwan, R.O.C.
`Post Office Address
`4F No.91-1 Chern-Kong Road, Seca' ,Tzee-Shin Li, Ne-Hu, Taipei County, Taiwan, R.O.C.
`Full name of fourth joint- ventor, if any
`VlinKoh
`Inventor' signature Lfe_41/4.)
`
`Fou
`
`11_6 0
`
`Residence
`No. 15 43rd Lane, Shuang-Hsi APao-Shan. Hsin Chu County, Taiwan, R.O.C.
`Citizenship
`Taiwan, R.O.C.
`Post Office Address
`No. 15 43rd Lane, Shuang-Hsi , Pao-Shan, Hsin Chu County, Taiwan, R.O.C.
`Full name of fifth jo. -inventor, if any
`Shin-Chikee
`Fifth Invent r's signature
`
`Date
`
`7.‘
`
`Date
`
`,s--
`
`Date
`
`(cid:9)??Z•te-11—
`
`Date
`
`/)(
`
`Residence
`6F No.20 126th Lane, Kuang-Ming Road, Ar-Chuang Li, Chu-Tun. Hsin Chu county, Taiwan, R.O.C.
`Citizenship
`Taiwan, R.O.C.
`Post Office Address
`6F No.20 126th Lane, Kuang-Ming Road, Ar-Chuang Li, Chu-Tung, Hsin Chu county, Taiwan, R.O.C.
`Full name of sixth joint-inv fitor, if any
`, Ci enhen (cid:9)
`Sixth Inventor's signature
`Ckte/et Uri avs-1_
`Residence
`No. 62 91st Lane, Tung-Mei Road,*n chu, Taiwan, R.O.C. (cid:9)
`Citizenship
`Taiwan, R.O.C.
`Post Office Address
`No. 62 91st Lane, Tung-Mei Road, Hsin chu, Taiwan, R.O.C.
`
`k9(
`
`Date
`
`(cid:9)
`(cid:9)
`

`
`2/q/so
`
`7-tv -tor.batd. — I 'DILI
`FIG.
`7 - Prior Art
`
`L
`
`01. (cid:9)CI.
`
`a •DIJ
`
`•-•
`
`
`
`

`
`8
`8
`
`2
`
`2
`
`8 (cid:9)
`8 (cid:9)
`
`8
`0
`0
`
`8
`0
`
`E (cid:9)
`10
`_C 10
`0
`8
`
`10
`
`Resistance
`
`6
`
`10
`
`4
`10
`2
`
`10
`
`10
`
`0 (cid:9)
`
`0
`
`I (cid:9)
`
`I
`
`1 (cid:9) I (cid:9)
`
`0
`I (cid:9) I (cid:9)
`
`t (cid:9)
`
`1 (cid:9)
`
`t (cid:9)
`
`t
`
`0.5 (cid:9)
`
`1
`1.5
`Laser Energy (uJ)
`
`FIG. 3
`
`0 (cid:9)
`0
`
`0 1 (cid:9)
`
`8 (cid:9)
`
`0
`0
`0
`
`I
`
`12
`10
`E 10
`10
`0
`8
`
`10
`
`6
`
`10
`
`MI
`
`4
`10
`2
`10
` •
`0
`
`10
`
`Resistance
`
`0 (cid:9)
`
`0.5 (cid:9)
`
`1.5
`Laser Energy (uJ)
`
`1 (cid:9)
`
`FIG. 4
`
`(cid:9)
`(cid:9)
`(cid:9)
`

`
`SERIAL NUMBER
`
`FILING DATE
`
`UNITED STAt DEPARTMENT OF COMMERCE
`Patent and Trademark Office
`Address: COMMISSIONER OF PATENTS AND TRADEMARKS
`Washington, D.C. 20231
`(cid:9) ATTORNEY DOCKET NOJ
`
`FIRST NAMED INVENTOR
`
`08/514,800 08/14/95 LOU
`
`GEORGE 0 SAILE
`20 MCINTOSH DRIVE
`POUGHKEEPSIE NY 12603
`
`B5M1/1024
`
`This is a communication from the examiner in charge of your application.
`COMMISSIONER OF PATENTS AND TRADEMARKS
`
`EXAMINER
`tARROLL,J
`
`2508
`DATE MAILED: •
`
`10/24195
`
`This application has been examined (cid:9) El Responsive to communication filed on
`
`(cid:9) El This action is made final.
`
`days from the date of this letter.
`month(s), (cid:9)
`A shortened statutory period for response to this action is set to expire (cid:9)
`Failure to respond within the period for response will cause the application to become abandoned. 35 U.S.C. 133
`
`Part I THE FOLLOWING ATTACHMENT(S) ARE PART OF THIS ACTION:
`1. El Notice of References Cited by Examiner, P10-892. (cid:9)
`3. El Notice of Art Cited by Applicant, P10-1449. (cid:9)
`5. El Information on How to Effect Drawing Changes, P10-1474. (cid:9)
`
`2. IC: Notice of Draftsman's Patent Drawing Review, P10-948.
`4. III Notice of Informal Patent Application, P10-152,
`6. El (cid:9)
`
`
`Part II SUMMARY OF ACTION
`
`Claims
`
`Of the above, claims (cid:9)
`
`2. El Claims
`3. ED Claims (cid:9)
`
`4. 0 Claims (cid:9)
`
`5.El Claims (cid:9)
`
`are pending in the application.
`
`are withdrawn from consideration.
`
`have been cancelled.
`
`are allowed.
`
`are rejected.
`
`are objected to.
`
`6,;Z:1 Claims \ (cid:9)
`c"-D
`(cid:9) are subject to restriction or election requirement.
`7. El This application has been filed with informal drawings under 37 C.F.R. 1.85 which are acceptable for examination purposes.
`
`8. DI Formal drawings are required In response to this Office action.
`9. El The corrected or substitute drawings have been received on (cid:9)
` Under 37 C.F.R. 1.84 these drawings
`are Clacceptable; 0 not acceptable (see explanation or Notice of Draftsman's Patent Drawing Review, PT0-948).
`
`10.
`
`The proposed additional or substitute sheet(s) of drawings, filed on (cid:9)
`examiner; 0 disapproved by the examiner (see explanation).
`
`. has (have) been 0 approved by the
`
`11. El The proposed drawing correction, filed (cid:9)
`, has been El approved; 0 disapproved (see explanation).
`12. E3 Acknowledgement is made of the claim for priority under 35 U.S.C. 119. The certified copy has 0 been received 0 not been received
`
` ; filed on (cid:9)
`0 been filed in parent application, serial no. (cid:9)
`
`13. El Since this application apppears to be in condition for allowance except for foraial matters, prosecution as to the merits is closed in
`accordance with the practice under Ex parte Quayle, 1935 C.D. 11; 453 0.G. 213.
`
`14. D Other
`
`PTOL-326 (Rev. 2/93)
`
`EXAMINER'S ACTION
`
`(cid:9)
`(cid:9)
`

`
`Serial Number: 08/514,800 (cid:9)
`Art Unit: 2508
`
`-2-
`
`Restriction to one of the following inventions is required
`under 35 U.S.C. § 121:
`
`I. Claims 1-8, drawn to a semiconductor device, classified
`in Class 257, subclass 529.
`II. Claims 9-15, drawn to a process of making a
`semiconductor device, classified in Class 437, subclass 15+.
`
`The inventions are distinct, each from the other because of
`the following reasons:
`Inventions II and I are related as process of making and
`product made. The inventions are distinct if either or both of
`the following can be shown: (1) that the process as claimed can
`be used to make other and materially different products or (2)
`that the product as claimed can be made by another and materially
`different process (MPEP § 806.05(f)). In the instant case,
`unpatentability of the group I invention would not necessarily
`imply unpatentability of the method of the group II invention,
`since the device of the group I invention could be made by
`processes materially different than that of the group II
`invention, for example, in claim 9, instead of patterning the
`fusible link, selectively form the same.
`Because these inventions are distinct for the reasons given
`above and, as shown by the above different classifications, the
`fields of search are not co-extensive and separate examination
`would be required, restriction for examination purposes as
`indicated is proper.
`Applicant is advised that the response to this requirement
`to be complete must include an election of the invention to be
`examined even though the requirement be traversed (37 C.F.R. §
`1.143).
`
`5 (cid:9)
`
`10 (cid:9)
`
`15 (cid:9)
`
`20 (cid:9)
`
`25 (cid:9)
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`
`Serial Number: 08/514,800 (cid:9)
`Art Unit: 2508
`
`-3-
`
`Applicant is reminded that upon the cancellation of claims
`to a non-elected invention, the inventorship must be amended in
`compliance with 37 C.F.R. § 1.48(b) if one or more of the
`currently named inventors is no longer an inventor of