(12) Ulllted States Patent
`Janssen et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,630,921 B2
`Oct. 7, 2003
`
`US006630921B2
`
`(54) COLUMN DRIVING CIRCUIT AND METHOD
`FOR DRIVING PIXELS IN A COLUMN ROW
`MATRIX
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`(75)
`
`.
`.
`Inventors. Pletseri. Janssfin, Scafipgougli, Ng k
`(
`)’
`“clan
`emus
`“’
`CW Or
`NY (US)
`
`’
`
`(73) Assignee: Koninklijke Philips Electronics N.V.,
`Eindhoven (NL)
`.
`.
`.
`.
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 182 days.
`
`.
`( * ) Notice:
`
`(21) APPL N05 09/8123489
`(22) Filed,
`Man 20, 2001
`
`(65)
`
`Prior Publication Data
`US 2002 0135557 A1 S
`. 26 2002
`ep
`/
`’
`Int. Cl.7 ................................................ .. G09G 3/36
`(51)
`
`. . . . . . . . . . . . . .
`(52) U.s. Cl.
`. . . . . . . . . . . . . . . .. 345/100
`(58) Field of Search .......................... .. 345/87, 92, 100,
`345/103, 95, 88, 89, 93-96, 98; 349/33,
`41, 42
`
`.................... .. 349/54
`4,781,438 A * 11/1988 Noguchi
`
`6310 628 B1 * 10/2001 Matsushita et al.
`..
`219/411
`7
`7
`6,424,328 B1 *
`7/2002 Ino et al.
`.................... .. 345/87
`
`* Cited by examiner
`
`Primary Examiner—Chanh Nguyen
`(74) Attorney, Agem, or Firm_Steven R, Bjren
`
`ABSTRACT
`(57)
`A column driving circuit and method for driving pixels in a
`column row matrix. Specifically, the present invention pro-
`vides a circuit and method that generally includes an input
`for receiving a signal, a multiplexing circuit for receiving the
`signal from the input, and a first and a second column line,
`wherein each column line alternates in receiving the signal
`.
`.
`.
`.
`.
`.
`.
`from the multiplexing circuit. By splitting the signal
`between two column lines, overall
`line capacitance is
`reduced, as are problems associated with delays in ramp
`retrace
`
`15 Claims, 6 Drawing Sheets
`
`7\J
`
`54
`
`DAC(n)
`MULTIPLEXEH
`
`82A | 82B
`
`60
`/
`
`70
`76
`
`DAC(n+1)
`MULTIPLEXER
`
`72
`
`78
`
`84A I 84B
`
`I
`
`I
`
`«94c
`Row(m-1)
`
`~51
`
`«-943
`
`O
`
`l 4
`
`945
`
`I
`7
`
`IIC5
`I 5013
`II- as
`es
`Q]!
`«-94A
`I 7
`
`DAC(n~1)
`MULHPLEXER
`
`68
`74
`
`102
`
` I
`i
`
`J:
`T
`
`4 941
`
`I
`‘-‘
`
`_
`
`a 94K
`
`I
`T
`
`« 941
`How(m+2)
`
`col (1!-HE
`
`Col(n-1)A
`
`Co1[n)B
`
`C0l(n)A
`
`Co1(n+1)B
`
`92
`
`Col (n+1)A
`
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`U.S. Patent
`
`Oct. 7, 2003
`
`Sheet 1 of 6
`
`US 6,630,921 B2
`
`DAC (0-1)
`
`20
`
`UAC(n)
`
`40A
`
`/
`
`14
`
`26
`
`16
`
`28
`
`22
`
`DAC (n+1)
`
`403
`
`./
`
`Tp (m-1)
`
`10
`
`/
`
`40C
`/
`
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`U.S. Patent
`
`Oct. 7, 2003
`
`Sheet 2 of 6
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`US 6,630,921 B2
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`Row (m-1)
`
`+— 40C
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`U.S. Patent
`
`Oct. 7, 2003
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`Sheet 3 of 6
`
`US 6,630,921 B2
`
`C770
`
`-
`EC’) E? ::
`
`MULTIPLEXER
`
`68
`
`*1-5
`
`64
`
`DAC(n)
`
`MULTEPLEXER
`
`70
`
`76
`
`66
`DAC (n+1)
`
`MULTIPLEXER
`
`72
`
`73
`
`60
`
`_/
`
`80A
`
`803
`
`348
`
`——_—:
`
`I
`
`I||-——|
`
`'1:
`
`1-;
`
`«-940
`
`T
`
`I22%3T8 3
`
`88
`
`4- 941
`
`Bow(NM)
`
`90
`
`+- 94L
`
`R0w(m+2)
`
` ——_CZI:
`
`
`
`100 D 95
`Q]
`98
`102
`
`Col(n1)B
`
`C0!(n)B
`
`Co|(n+1)B
`
`92
`
`Col (n 1)A
`
`Co! (0) A
`
`Co! (n+1) A
`
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`U.S. Patent
`
`Oct. 7, 2003
`
`Sheet 4 of 6
`
`US 6,630,921 B2
`
`DAC(n-1)
`
`MUUIPLEXER
`
`58
`
`74
`
`DAB (0)
`
`MULTIPLEXER
`
`70
`
`76
`
`DAC(n+1)
`
`72
`
`104
`
`_/
`
`MULTIPLEXER
`
`78
`
`808
`
`30A
`
`as |
`
`32A |
`
`823
`
`84A |
`
`848
`
`mm1)
`
`10?
`
`100
`
`88 I
`
`0
`
`90
`
`92
`
`COH —
`
`C0l{n-1)A
`
`<—94F
`R0w(m)
`
`+-105
`
`R0w(m+1)
`941
`
`<—94L
`
`Row(m+2)
`
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`U.S. Patent
`
`Oct. 7, 2003
`
`Sheet 5 of 6
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`US 6,630,921 B2
`
`DATA
`! F 52
`r— ''''''''''' — ' ‘~
`
`E
`i
`ANALOG om
`P ''''' --
`
`F'‘\.. 53
`1
`.,« 74
`
` \/ref./-112
`
`MULTIPLEXER
`
` Vref—’-W
`
`MULTIPLEXER
`
`
`
`SOACOLUMN A
`
`COLUMN 8808
`
`G . 6
`
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`U.S. Patent
`
`Oct. 7, 2003
`
`Sheet 6 of 6
`
`US 6,630,921 B2
`
`152/?
`
`154/?
`
`156/?
`
`150
`/
`
`MULTIPLEXER
`
`74
`
`MULTIPLEXER
`
`76
`
`MULTIPLEXER
`
`73
`
`82B
`
`84A
`
`<- 94C
`
`Row (m-1)
`
`
`88
`
`<~ 941
`
`Row(um)
`
`90
`
`«— 94L
`
`Row(rn+2)
`
`L
`
`1
`
`BOA I 803
`II-
`élfl
`
`82A
`
`96
`93 ~94/x
`
`102
`
`
`
`'
`
`Co! (n-1)B
`
`Col (n-1) A
`
`Col (n) B
`
`Col (0) A
`
`Col {n+1)B
`
`92
`
`Go! (n+1) A
`
`FIG. 7
`
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`
`US 6,630,921 B2
`
`1
`COLUMN DRIVING CIRCUIT AND METHOD
`FOR DRIVING PIXELS IN A COLUMN ROW
`MATRIX
`
`BACKGROUND OF THE INVENTION
`
`1. Technical Field
`
`The present invention generally relates to a column driv-
`ing circuit and method for driving pixels in a column row
`matrix. More particularly, the present invention relates to an
`improved circuit and method for reducing the capacitive
`load on the columns of the matrix to provide improved pixel
`driving.
`2. Background Art
`In video displays, matrices are commonly utilized in
`which pixels are oriented in a column row format. The
`column driving scheme currently employed to drive the
`pixels is based on a common analog ramp signal that is
`sampled by all columns in the display. Problems associated
`with this architecture include a high capacitive load that
`each column presents to the column buffer, where a buffer
`amplifier is used in every column. Moreover, as the address-
`ing frequency increases, as a result of a higher frame rate or
`a higher pixel count of the display, the fidelity of the sampled
`signal decreases.
`Another problem associated with the existing architecture
`is ramp retrace. In particular, the ramp signal in each column
`must retrace rapidly to an initial state in order to maximize
`the time available for sampling. Specifically, before the
`columns of the existing architecture can be driven with the
`analog signal, they must first be brought to an initial state or
`retraced. Thus, driving the pixels is at least a two step
`process in which each column must: (1) retrace to initial
`state; and (2) apply the analog signal. Since, a fast retrace
`requires large current capability of the driver(s), the asso-
`ciated large transients in the matrix could cause undesired
`effects, e.g., activating unselected rows.
`In view of the foregoing, there exists a need for a column
`driving circuit and method for reducing the capacitive load
`in the columns of the matrix. Moreover, a need exists for a
`column driving circuit and method that reduces the problems
`associated with ramp retrace.
`SUMMARY OF THE INVENTION
`
`invention addresses the problems of the
`The present
`existing architecture by providing an improved column
`driving circuit and method for driving pixels in a column
`row matrix. Specifically, the present invention provides a
`column driving circuit wherein each column is split into at
`least two column lines. Each column line communicates
`
`with/is joined to a unique subset of rows in the matrix. By
`splitting the columns into multiple column lines, the capaci-
`tance of each line is a fraction of that required by a single
`column. In addition, because each column is split into at
`least two column lines, a first column line can be retraced to
`the initial state while the second column line is being driven
`by the analog signal thus, reducing the delays associated
`with ramp retrace.
`According to a first aspect of the present invention, a
`column driving circuit for driving pixels in a column row
`matrix is provided. The circuit comprises: (1) a multiplexing
`circuit for receiving a signal; and (2) a first and a second
`column line, wherein the column lines receive the signal
`from the multiplexing circuit, and wherein the first column
`line is in communication with different rows of the matrix
`than the second column line.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`According to a second aspect of the present invention, a
`column driving circuit for driving pixels in a column row
`matrix is provided. The circuit comprises: (1) a DAC (digital
`to analog converter) for generating an analog signal
`in
`response to a digital input; (2) a multiplexing circuit for
`receiving the signal from the DAC; (3) a first and a second
`column line, wherein the column lines alternate in receiving
`the signal from the multiplexing circuit; and (4) wherein
`each column line includes at least one junction for commu-
`nicating with a unique subset of rows in the matrix.
`According to a third aspect of the present invention, a
`method for driving pixels in a column row matrix is pro-
`vided. The method comprises the steps of: (1) receiving a
`signal in a multiplexing circuit; (2) selectively sending the
`signal from the multiplexing circuit to a first and second
`column line; and (3) communicating the column lines with
`rows of the matrix to drive the pixels, wherein the first
`column line communicates with different rows than the
`second column line
`
`Therefore, the present invention provides a column driv-
`ing circuit and method for driving pixels in a column row
`matrix. The present invention reduces the problems associ-
`ated with high column capacitance and ramp retrace.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`These and other features and advantages of this invention
`will be more readily understood from the following detailed
`description of the various aspects of the invention taken in
`conjunction with the accompanying drawings in which:
`FIG. 1 depicts a first prior art column driving circuit;
`FIG. 2 depicts a second prior art column driving circuit;
`FIG. 3 depicts a column driving circuit in accordance with
`the present invention;
`FIG. 4 depicts a first alternative embodiment of a column
`driving circuit in accordance with the present invention;
`FIG. 5 depicts a multiplexing circuit in accordance with
`the present invention;
`FIG. 6 depicts an alternative embodiment of a multiplex-
`ing circuit in accordance with the present invention; and
`FIG. 7 depicts a second alternative embodiment of a
`column driving circuit in accordance with the present inven-
`tion.
`
`It is noted that the drawings of the invention are not
`necessarily to scale. The drawings are merely schematic
`representations, not intended to portray specific parameters
`of the invention. The drawings are intended to depict only
`typical embodiments of the invention, and therefore should
`not be considered as limiting the scope of the invention. In
`the drawings, like numbering represents like elements.
`DETAILED DESCRIPTION OF THE DRAWINGS
`
`As stated, the present invention comprises an improved
`column driving circuit and method for driving pixels in a
`column row matrix. Generally, the present invention splits
`each column of the matrix into a plurality (preferably two)
`column lines. Each column line communicates with, or is
`joined, to a unique subset of rows in the matrix. Accordingly,
`the different column lines of a single column communicate
`with different (e. g., alternating) rows. An analog ramp signal
`then is alternately applied to the column lines within each
`column. The resulting configuration reduces the capacitance
`on each column line. Moreover, as the analog signal is being
`applied to a first column line, a second column line can be
`retraced to an initial state. Therefore, there is negligible
`delay for a column line to retrace to the initial state.
`
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`US 6,630,921 B2
`
`4
`3
`includes input signals 62, 64, and 66, which are preferably
`Referring first to FIG. 1, a prior art column driving circuit
`digital signals. The signals are received in DACs 68, 70 and
`10 is depicted. The circuit is for driving pixels in a column
`72 where they are converted to analog signals. Once
`row matrix 11. As shown, the matrix comprises columns 24,
`converted, the signals are then communicated to multiplex-
`26, and 28 and rows 30, 32, 34, and 36. Digital input signals
`ing circuits 74, 76, and 78. The multiplexing circuits 74, 74,
`l
`l
`l
`.
`12, 14, and 16 are received by each column via digital to 5
`and 78 split each column into multiple column lines 80AfB,
`analog converter (DACs) lg’ 20’ and 22. Each DAC con_
`82A‘B’ aha 84ATB' Thhs’ lhslead of eaeh DAC ohtphthhg
`verts the digital signal to an analog signal, which is then used
`ah ahalog slghal lhlo a slhgle llhe (as shown lh FIGS‘ 1 ahd
`to drive a particular column within the matrix. Specifically,
`2), the signal is outputted over multiple lines.Although each
`the analog Signal exits each DAC 18’ 20’ and 22 and is
`received by columns 24, 26, and 28, respectively. Each 10 eelhlhh ls Shewh as belhg Splll lhle awe eelhlhh llhee’ ll
`column 24’ 26’ and 28 includes a junction 40A_L to each
`should be understood that any quantity of column lines
`row 30, 32, 34 and 36. Accordingly, each row controls one
`Could be lollhed (e‘g" 4’ 6’ 8’ .ele‘)'
`.
`junction of each column. Each junction 40A—L generally
`Byjsphlhhg eaeh eohhhhjlhlo two eohhhh hhes’ the
`comprises a pixel transistor 42, a capacitor 44, a pixel 46 and
`eapaehahee of eaeh eohhhh hhe ls approxhhately ohe'half
`a ground 48. It should be understood that the capacitor 44 15 that of each eohhhh of. ehehhs 10 ahd .50‘
`Whl he
`represents a capacitance associated With pixel 46.
`described in further detail below, ‘the multiplexing circuits
`Accordingly’ pixels 46 are not explicitly shown for each
`74, 76, and 78 alternate the respective analog signal between
`junction 40A—L. However, it should be understood that each
`the two eohhhh hhes lh eaeh pah‘ Thus’ fohexalhple’ Whhe
`junction 40A_L includes a pixel 46.
`one cnolumnlline
`hejceilxjles the anlalog siglnal, ltlhe corre-
`When a video display that includes matrix 11 is refreshed, 20 .SP°“ tlllg Get amll tllle
`B eere hot’ n aei all eil.l etplgeehl
`each pixel 46 must be driven. To accomplish this, each row
`lalfijagelgllaillleatlljenavelltlilezzzilaalewegagags eeoldlllalllrlldlgg taillerzilll
`will be individually activated for a brief period of time. This
`reducin
`the
`arasitic Ca acitancé £0} each Column nney
`allows llle analog elgllal lll eaell eelamll 24’ 26 and 28 le
`S ecifioeall
`as)shown in FIJG 3 each column line referabl i
`pass through the junctions 40A . L corresponding the acti-
`inhaiudes . y’
`t.
`94A_L t ’
`’
`.
`b
`t
`fp
`F y
`vated row and drive the pixels. For example, if row 30 is to 25
`Jane lens .
`0 a alllqae ea Se 0 . rows’
`or
`be refreshed, it will first be activated. The analog signals will
`"’.‘am.Pl‘°” °.°il“m“ llélees
`eziéi ahdi 84Ai*.‘“’ llérfigllhlhilge
`then pass from columns 24, 26, and 28 through junctions
`llleiaaglzilgwll lows
`all.
`t. ’ W ll: ee llmgls lllede 92 i;
`E
`to
`be
`:2
`repealed fol lows 32’ 34’ and 36'
`the effecets of the parasitic capacitance of each junction are
`As indicated above, however, this architecture presents 30 reduced
`many problems. In particular each column 24, 26, and 28 has
`AS farther Shown in FIG. 3 the junctions generally
`a lelallvely hlgh eapaehahee both from the llhes ahd ahy
`comprise transistor 96 capacitor a98 pixel 100 and ground
`un-activated pixel transistors, which requires more voltage,
`102. It Should be unde;Stood however that a pixel is Shown
`and results in reduced accuracy and bandwidth of the matrix.
`only in junction 94A for cla;jty purposes and an junctions
`Moreover’ before ahy eelhlhh 24’ 26’ ahd 28 eah leeelve the 35 include a
`ixel To refresh the dis la on which the column
`analog signal, it must first be retraced to an initial state. This
`row matrlax 61'
`is implemented pealch row is Selectively
`delay asseelaled Wllh lellaee reduces the lhaxllhhlh lllhe
`activated for a period of time which allows the analog signal
`avallable for Salhpllhg by the lows’ Whleh ls espeelally
`to pass from the column lines through the junctions corre-
`pleblelhalle lh larger lhallleee
`40 sponding to the activated row: and drive the pixels therein.
`FIG. 2 shows a second prior art column driving circuit 50.
`For example, if row 36 were activated, the analog Signals
`This circuit 50 includes similar elements as circuit 1t) and
`would pass from Cohhhh hhes 30A, 32A, and 34A, through
`dr1Ve5 C0lutI1H TPW matrlx 51- Speclficallya Clrcult 50
`junctions 94A—C, and drive pixels 100 (not shown in every
`receives digital signals 12, 14 and 16 in DACs 18, 20, and
`junction).
`22 ahd eohvehs the slghals from dlghal to ahalog‘ The 45
`Contrary to the teachings of circuits 10 and 50, as column
`analog signals are then passed to the columns 24, 26, and 28,
`lines 80A’ 82A’ and 84A are driving the pixels on row 86’
`which communicate with selectively activated rows 30, 32,
`column lines 80B’ 82B’ and 84B are being retraced to an
`34 ahd 36' lh elhbodhhehl of FIG‘ 2’ however’ eaeh eohhhh
`initial state. The switches in the multiplexing circuits 74, 76,
`communicates with pairs of rows instead of individual rows.
`and 78 (described below) are configured such that While one
`For example’ if row 30 ls to be refreshed’ it will hrsl be 50 column line 80A is receiving the analog signal, the corre-
`activated. The analog signal will then pass through junctions
`sponding colurnn line 80B is being retraced to the initial
`40A_C ahd drive the pixels therelh‘
`state (i.e., the analog signal is alternated between the column
`The Cifellit 50 Of FIG 2 P0ssesses the same dfaWbaCl<s as
`lines in each pair). Thus, when row 86 is later deactivated so
`CifC1lit 10. Specifically, eaCh C0l1lII1I1 24, 26, and 23 has a
`that row 88 can be activated, there is no delay in waiting for
`relatively high capacitance that requires more time to reach 55 retrace to occur (i.e., it has already occurred). As indicated
`the capacity. This increase in time to reach capacity results
`above, the elimination of this delay improves performance
`in fed1lCed accuracy and bandwidth Of
`the II1atriX.
`of the display. Accordingly, to refresh row 88, it would be
`Specifically, each un-activated transistor 42 has a parasitic
`activated, the analog signals would pass from column liries
`capacitance slows the time to drive the column. Moreover,
`80B, 82B, and 84B throngh junctions 94D_F, and drive the
`as indicated above, each column must be retraced to the 60 associated pixels 100 (not shown in every junction).
`initial state prior to communicating the analog signal
`Accordingly, splitting each column into two (or more)
`through the j1lI1Cti0I1s 40A-L. This fetraee Causes delay in
`column lines not only reduces the line capacitance and ramp
`the cycle and thus, reduces the maximum time available for
`retrace delay, but also reduces parasitic capacitance by
`sampling by the r0Ws.
`allowing each column line in a single pair to communicate
`Referring now to FIG. 3, a column driving circuit 60 for 65 With different FOWS Of the C0l1lH1h TOW H1atfiX 61-
`driving pixels in a column row matrix 61 in accordance with
`FIG. 4 shows an alternative embodiment of the present
`the present
`invention is shown. As depicted, circuit 60
`invention. Specifically, column driving circuit 104 drives the
`
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`
`US 6,630,921 B2
`
`6
`
`5
`pixels 100 in column row matrix 105. Although the com-
`transistor voltage
`(controlled by signals 114 and 116),
`ponents of circuit 104 are similar to that of circuit 60, the
`switches 112 (controlled by signals 118 and 120), and
`architecture thereof is distinct. In particular, digital signals
`column lines 80A and 80B. However, multiplexing circuit
`62, 62, and 66 are received in DACs 68, 70, and 72, where
`122 also includes hold signals 128 and 130 and “AND” gates
`they are converted to analog signals. From the DACs 68, 70,
`5 124 and 126. The hold signals 118 and 120 originate from
`.
`i
`the DAC 68, which in this embodiment is a “track and hold”
`ahd 72> the ahalog Slghals are Commhhlcated through Ih1h'
`DAC. By including a hold Signal’ the Sampling Switch is
`tiplexing circuits 74, 76, and 78, which splits each column
`opened at the moment sampling is to occur. The difference
`lhte lhhltlple (preferably two) eelhlhh llhes 80A_B’ 82A_B’
`between a “track and held” and “Sample and hold” is the
`and 84A—B. However, instead of the column lines of each
`10 duration the sampling switch is closed. Specifically in a
`hall eelhlhhhleatlhg Wlth alterhatlhg rows as Shewh lh FIG‘
`“Sample and hold” embodiment
`the Sampling Switch is
`3, the column lines of each pair communicate with pairs or
`closed for the shortest possible time. In “track and hold,” the
`adj aeeht Subsets Of lows‘ Thhe’ lows 86 ahd 88 would he
`switch is closed from the very beginning of each cycle until
`refreshed by a hret eehhhh hhe 80A’ 82A’ ahd 84A Whlle
`it opens at “hold.” Similar to the multiplexing circuit 74 of
`lows 90 ahd 92 would be refreshed by a Seeehd eelhlhh llhe
`80B’ 82B’ ahd 84B’ For example’ for row 86 was to be 15 FIG. 5, the multiplexing circuit 122 will alternate the analog
`refreshed’ lt would hlet be aetlVated' Theh’ the ahaleg
`signal between the column lines 80A and 80B. The column
`Slghale would. page from eelhlhhhhee 80A’ 82A’ ahd 84A
`line that is not receiving the analog signal will receive the
`through Jahetlehe 94A_C ahd drlve the plxele 100'
`reference voltage 112 for retracing to the initial state.
`AS lndleated above’ tne analog elgnale are alternated
`Referring now to FIG 7 it should be appreciatedacircuit
`between the column lines in each pair so that while one 20
`d.
`t
`th
`.
`’
`t.
`d
`t
`.
`DAC
`column line is receiving the signal, the corresponding col-
`aeeol.
`lng o . e pleeen .lnVen lo.n nee no. leqnlle a
`umn line can be retraced back to the initial state. Once row
`to dllve the hotels’ Speelneally’ ll analo.g Slgnals .152.’ 154’
`.
`.
`and 156 are provided directly to the multiplexing circuits 74,
`it would be deactivated and, for
`76 and 78 there is He need to utilize a DAC Thee eeiumn
`86 has been refreshed,
`instance, row 90 would be individually activated. Thus, the
`drfvin
`eigeuit 150 (used to drive
`ixeie ie eeiu’mn row
`analog elgnal would be leeelved by eolnlnn llnee 80B’ 82B’ 25 matrixg151) will receive in ut (analo I; si nals 152 154 and
`and 84B and Pass through junctions 94G‘l to drive the
`156 directl
`at multi
`lexirl) circuitsg74 e76 and is IVIulti-
`pixels therein. Because retrace occurred while the signal
`i
`.
`. y .t 74 716)
`dgs
`.11 th
`’
`i
`’t.
`i
`'
`i
`th
`e
`’ an
`passed through column lines 80A, 82A, and 84A, there is no
`p.eXlng ollenl S
`’
`.
`Wl
`en Se ee lve y app y
`delay in waiting for column lines 80B, 82B, and 84B to be
`elgnale .to eolnlnn llnee o0A_B’ o2A_B’ and. o4A_B by
`.
`.
`.
`alternating the signal between the two column lines of each
`retraced before dllvlng tne hotels’
`30 column Pixel driving will then occur as described above in
`Referring now to FIG. 5, a first embodiment of the
`Conjunction with FIGS. 3 and/or 4.
`.
`multiplexing circuit 74 is depicted. As shown, a digital
`.
`.
`.
`signal 62 is received and converted by DAC 68 to analog.
`The foregelhg deeehptleh of the preferred elhbedhhehte
`The multiplexing circuit 74 then receives the analog signal
`Of thle lhvehtleh. has beeh pleeehted for purposes ef.lllhS'
`from DAC 68. AS indicated above’ the multiplexing Circuit 35 trationtand description. It is not intended to be exhaustive or
`alternates the analog signal between column line 80A and
`to hhht the lhvehtleh.
`to the preelee forth dleeleeed’ .ahd
`80B. Moreover’ While one Column line is receiving the
`obviously,.many modifications and variations are possible.
`analog signal, the other will receive a reference voltage 112
`Such lhedlheatlehe ahd Varlatlehe that may he apparehttoa
`for simultaneous retracing to the initial state. These func-
`peleeh Skllled lh the art. are lhtehded to be lhelhded Wlthlh
`tions are provided by transistor signal switches 104 and 106 40 theeeepe of thle lhvehtleh as dehhed by the aeeelhpahylhg
`and transistor voltage switches 108 and 110. Specifically,
`elallhe‘
`.
`.
`.
`i
`.
`.
`.
`.
`.
`.
`when signal switch 104 is “on,” signal switch 106 is “off”
`What ls elahhe.d.lS'
`and the analog signal will pass through column line 80A.
`1‘ Aeelhlhh dhvlhg elrelht for drlvlhg plxele lh a eehhhh
`Moreover, when signal switch 104 is “on,” voltage switch
`low lhatllx’ C9mP“§1“gf
`.
`i
`i
`110 corresponding to column line 80B will also be “on.” 45
`a Ihhlhplexlhg Chchh for recelvlhg a Slghah
`This permits the reference voltage 112 to pass through
`a first and a second column line, wherein the column lines
`column line 80B to retrace column line 80B to the initial
`receive the signal from the multiplexing circuit, and
`state while column line 80A is receiving the analog signal.
`wherein the first column line is in communication With
`The switches 104, 106, 108, and 110 are controlled by
`different rows of the matrix than the second column
`signals 114, 116, 118, and 120, respectively. These signals 50
`line; and
`activate the transistors in each switch to connect the column
`wherein the multiplexing circuit comprises a plurality of
`lines to the analog signal or voltage.
`signal switches for alternating the signal between the
`Once the rows corresponding to column line 80A have
`first and second column lines, and a plurality of voltage
`been refreshed and are deactivated, the rows corresponding
`switches for alternating a retrace reference voltage
`to column line 80B can be activated for refreshing. As this 55
`between the first and second column lines.
`occurs, signal switch 104 and voltage switch 110 will be
`2. The circuit of claim 1, wherein the multiplexing circuit
`turned “off” while signal switch 106 and voltage switch 108
`receives the signal from a digital to analog converter (DAC).
`are turned “on.” This allows for the pixels of the rows
`3. The circuit of claim 1, wherein the multiplexing circuit
`corresponding to column line 80B to be driven with the
`further comprising
`analog signal while column line 80Ais retraced to the initial 50
`a hold signal for maintaining voltage in the first and
`state by reference voltage 112. As indicated above,
`this
`second column lines,
`architecture and method eliminate the delay and problems
`4, The circuit of claim 1, wherein when the first column
`aSSOCiat€d With ramp r€traC€.
`line is receiving the signal,
`the second column line is
`Referring now to FIG. 6, an alternative embodiment of the
`receiving the reference voltage.
`multiplexing circuit 122 is shown. Similar to FIG. 5, the 65
`5. The circuit of claim 1, wherein each column line
`multiplexing circuit 74 receives a digital signal 62 and
`includes at least one junction to a row in the matrix, and
`includes DAC 68, transistor signal switches 104 and 106
`wherein each junction comprises:
`
`SEC v. Surpass Tech, |PR2015—OO887
`SAMSUNG EX. 1025 — 10/11
`
`SEC v. Surpass Tech, IPR2015-00887
`SAMSUNG EX. 1025 - 10/11
`
`

`
`US 6,630,921 B2
`
`a transistor;
`
`a pixel; and
`a ground.
`6. Acolumn driving circuit for driving pixels in a column
`TOW matrix, C0H1Pri5iHg3
`a DAC for generanng an analog Signal in response to a
`dlgltal lnnut;
`.
`.
`.
`.
`.
`a Igliténlexlng Clrcult for recelvmg the Slgnal from the
`’
`.
`.
`.
`a first and a second column line, wherein the column lines
`alternate in receiving the signal from the multiplexing
`circuit, and wherein each column line includes at least
`one junction for communicating with a unique subset of
`rows in the matrix; and
`wherein the multiplexing circuit further comprises a plu-
`rality of signal switches for alternating the signal
`betweeh the first and SeC0hd C0111H1h lines, and 3
`plurality of voltage switches for alternating a retrace
`reference voltage between the first and second column
`lines.
`
`7. The circuit of claim 6, wherein the multiplexing circuit
`further comprises a hold signal for maintaining voltage in
`the column lines.
`
`8. The circuit of claim 6, wherein each junction com-
`prises:
`a transistor;
`a pixel; and
`a ground.
`9. The circuit of claim 6, wherein the column lines
`communicate with alternating rows.
`10. The circuit of claim 6, wherein each column line
`communicates with adjacent pairs of rows.
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`8
`11. The circuit of claim 6, wherein each junction joins one
`of the column lines to one of the rows.
`12. A method for driving pixels in a column row matrix,
`COII1pf1S1I1g the Steps Ofi
`receiving a signal in a multiplexing circuit;
`selectively sending the signal from the multiplexing cir-
`cuit to a first and second column line;
`communicating the column lines with rows of the matrix
`to drive the pixels. wherein the first column line com-
`municates with different rows than the Second Column
`1.
`.
`d
`me’ an
`wherein the multiplexing circuit further comprises a plu-
`rality of signal switches for alternating the signal
`betWeeI1 the first and SeC0hd C0111H1h hhes, and 3
`plurality of voltage signals for alternating a retrace
`reference voltage between the first and second column
`lines.
`13. The method of claim 12, wherein the column lines
`communicate with the rows through junctions, and wherein
`each junction joins one of the column lines to one of the
`rows.
`
`14. The method of claim 13, wherein each junction
`comprises:
`a transistor;
`a pixel; and
`a ground.
`15. The method of claim 12, wherein the multiplexing
`circuit receives the signal from a DAC.
`
`SEC v. Surpass Tech, |PR2015—OO887
`SAMSUNG EX. 1025 -11/11
`
`SEC v. Surpass Tech, IPR2015-00887
`SAMSUNG EX. 1025 - 11/11