(cid:49)(cid:40)(cid:55)(cid:36)(cid:51)(cid:51) EXHIBIT 1002
`
`PART (cid:22)
`
`
`
`PART (cid:22)
`
`
`
`“K)9UW3fl
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`PCFIUS90/0471 1
`
`-80-
`
`To commence the transfer of the next segment of the
`block of data to be transferred,
`the master drives
`DSO*
`low 739 and, after a predetermined period of
`time, drives Ds0* high 741.
`'.In response to the
`transition of Ds0* from high to low, respectively 739
`and 741, the slave latches the data being broadcast by
`the master over data lines D00 through D31, 743. The
`
`745, and
`in the form of a
`
`awaits receipt of a DTACK* signal
`high to-low transition, 747.
`The slave then drives DTACK* low, 749, and,
`after
`a predetermined period of time, drives DTACK* high,
`751.
`The data_1atched by the slave, 743,
`is written
`to the device selected to store the data and the
`device address is incremented 753.
`The slave waits
`for another transition of Ds0* from high to low 737.
`
`After all-
`
`the master will
`
`lines,
`address modifier
`line,
`IACK* line, LWORD*
`line and DSO*
`data lines,
`755.
`"The master will
`then wait for 5
`receipt of a
`DTACK* high to low transition 757.
`The slave will
`drive DTACK*
`low,
`759 and, after
`a predetermined
`period of time, drive DTACK* high 761.
`In response to
`the receipt of the DTACK* high to low transition, the
`master will drive As* high 763 and then release the
`As* line 765.
`
`Fig.
`parts
`is
`a
`flowchart
`through C,
`A
`8,
`illustrating the operations involved in accomplishing
`the fast
`transfer protocol BLOCK READ cycle.
`To
`initiate-a BLOCK READ cycle, the master broadcasts the
`memory address of the data to be transferred and the
`address modifier across the DTB bus 801.
`The master
`sussnnne sum 7
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`NetApp Ex. 1002, pg. 1201
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`\N()91/03788
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`PC!‘/US90l047 1 1
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`-81-
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`drives the LWoRD* signal_low and the IACK* signal high
`801.
`
`As noted previously, a special address modifier
`indicates to the slave module that the fast transfer
`
`‘protocol will be used to accomplish the BLOCK READ.
`The slave modules connected to the DTB receive the
`address and the address modifier broadcast by the
`
`master across the bus and receive LWORD* low and IACK*
`
`shortly after broadcasting the address and
`high 803.
`address modifier 801, the master drives the AS* signal
`low 805.
`807.
`
`The slave modules receive the AS* low signal
`
`Each slave individually determines whether it
`
`will participate in the data transfer by determining
`whether the broadcasted address is valid for the slave
`
`in question 809.
`
`If the address is not valid,
`
`the
`
`data transfer does not involve that particular slave
`
`and it ignores the remainder of
`
`the data transfer
`
`cycle.
`
`‘
`
`The master drives WRITE* high to indicate that the
`
`transfer cycle about to occur is a READ operation 811.
`The slave receives the WRITE* high signal 813 and,
`knowing that the data transfer operation is a READ
`operation, places the first segment of the data to be
`transferred on data lines D00 through D31 819.
`The
`master will wait until both DTACK* and BERR* are high
`
`818, which indicates that the previous slave is no
`longer driving the DTB.
`The raster then drives DSO* low 821 and, after a
`The »
`
`predete mined interval, drives DSO* high 823.
`master then awaits a high to low transition on the
`
`the
`8B,
`line 824.
`DTACK* signal
`slave then drives the DTACK* signal low 825 and, after
`a predetermined period of
`time, drives the DTAcK*
`signal high 827.
`
`shown in Fig.
`
`As
`
`In response to the transition of DTACK* from high
`to low, respectively 825 and 827,
`the master latches’
`the data being transmitted by the slave over data
`
`SUBSTITUTE SHEET
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`NetApp Ex. 1002, pg. 1202
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`
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`u«)9um3nw
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`PCT/US90l047ll
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`-82-
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`The data latched by the
`lines ubo through D31, 331.
`master, 831,
`is written to a device, which has been
`selected to store_ the data the device address
`is
`incremented 833.
`'
`
`The slave places the next segment of the data to be
`
`transferred on data lines D00 through D31, B29, and
`then waits for another transition of Ds0* from high to
`low 837.
`‘
`
`To commence the transfer of the next segment of the
`block of data to be transferred,
`the master drives
`
`low 839 and, after a predetermined period of
`DSO*
`time, drives DSO* high 841. The master then waits for
`the DTACK* line to transition from high to low, 843.
`_The slave drives DTACK*
`low, 845, and, after a
`predetermined period of time, drives DTACK* high, 847.
`In response to the transition of DTACK* from high to
`low, respectively 839 and 841,
`the master latches the
`
`data being transmitted by the slave over data lines
`D00 through D31, 845. The data latched by the master,
`845,
`is written to the device selected to store the
`and the device address
`data,
`851
`in Fig.
`8C,
`is
`incremented. The slave places the next segment of the
`data to be transferred on data lines D00 through D31,
`849.
`p
`The transfer of data will continue in the above-
`
`described manner until all of
`
`the data
`
`to be
`
`transferred from the slave to the master has been
`
`written into the device selected to store the data.
`
`After all of
`
`the data to he transferred has been
`the master will
`
`written into the storage device,
`lines,
`release the address lines, address modifier
`data_lines,
`the IhCK* line,
`the LWORD line and DSO*
`line 852. The master will then wait for receipt of a
`DTACK* high to low transition 853.
`The slave will
`drive DTACK* low 855 and, after a predetermined period
`.of time, drive DTACK* high 857.
`In response to the
`
`suflstnurz sum
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`NetApp Ex. 1002, pg. 1203
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`-33-
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`receipt of
`
`the DTACK* high to low transition,
`
`the
`
`master will drive AS* high 859 and release the AS*
`line 861.
`
`implement
`transfer protocol,
`a
`fast
`the
`To
`conventional 64 mA tri-state driver is substituted for
`
`the 48 mA open collector driver conventionally used in
`
`VME slave modules to drive DTACK*.
`
`Similarly,
`
`the
`
`conventional VMEbus data drivers are replaced with 64
`The latter
`
`mA tri—state drivers in SO-type packages.
`
`modification reduces the ground lead inductance of the
`itself
`thus,
`reduces
`actual driver package
`and,
`skew
`“ground bounce“ effects which contribute to
`
`between data,
`
`DSO* and DTACK*,
`
`In addition,
`
`signal
`
`return inductance along the bus backplane is reduced
`
`by using a connector system having a greater number of
`
`ground pins so as to minimize signal return and mated-
`
`pair pin inductance. One such connector system is the
`Model No. 420-8015-
`
`“High Density Plus” connector,
`
`OOO, manufactured by Teradyne Corporation.
`I
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`NetApp Ex. 1002, pg. 1204
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`wo 91/03788
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`A
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`'
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`‘
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`PCI‘/US90/04711"
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`The parity FIFOs 240, 260 and 270 (on the network
`
`.control1ers
`
`110),
`
`and
`
`544
`
`and
`
`554
`
`(on
`
`storage
`
`processors 114) are each implemented as an ASIC. All
`
`the parity FIFOs are identical. and are configured on
`power-up or-during normal operation for the particular
`function desired.
`The parity FIFO is designed to
`
`allow speed matching between buses of different speed,
`
`and to perform the parity generation and correction
`
`for the parallel SCSI drives.
`
`The FIFO comprises two bidirectional data ports,
`Port A and Port B, with 35 x 64 bits of RAM buffer
`between them. Port A is 8 bits wide and Port B is 32
`
`bits wide.
`
`The RAM buffer is divided into two parts,
`
`each 36 x 32 bits, designated RAM X and RAM Y.
`
`The
`
`the buffer
`two ports Vaccess different halves of
`alternating to the other half when available. When
`
`the chip is configured as a parallel parity chip (e.g.
`
`one of the~FIFOs 544 on SP 114a), all accesses on Part
`
`B are monitored and parity is accumulated in RAM X
`
`and RAM Y alternately.
`
`The chip also has a CPU interface, which may be 8
`
`or 16 bits wide.
`
`In 16 bit mode the Port A pins are
`
`used as the most significant data_hits of
`
`the CPU
`
`interface and are only actually used when reading or
`
`writing to the Fifo Data Register inside the chip.
`A REQ, ACK handshake is used for data transfer on
`
`The chip may be configured as
`both Ports A and.B.
`either a master or a slave on Port A in the sense
`
`that,
`
`in master_mode the Port A ACK / RDY output
`
`signifies that the chip is ready to transfer data on
`
`Port A, and the Port A REQ input specifies that the
`
`In slave made, however, the Port
`slave is responding.
`A RBQ input specifies that the master requires a data
`
`8!JB§I!TllTE SHEET
`
`NetApp Ex. 1002, pg. 1205
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`
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`WO 91/03788
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`PCTIUS90l0471 1
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`-55-
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`transfer, and the chip responds with Port A ACK / RDY
`
`The chip is a master on Port
`when data is available.
`E since it raises Port B REQ and waits for Port BACK
`
`to indicate completion of the data transfer.
`
`§lfiNAL_DE§§Bl2IIQN§
`
`Port A 0-7, P
`
`Port A is the 8 bit data port. Port A P, if used,
`is the odd parity bit for this port.
`
`A Req,
`
`A Ack/Rdy
`
`These two signals are used in the data transfer
`mode to control the handshake of data on Port A.
`
`u? Data 0-7, uP Data P, uPAdd o-2,
`
`cs
`
`These
`
`signals are used by a microprocessor
`
`to
`
`address the programmable registers within the chip.
`
`The odd parity signal uP Data P is only checked when
`data is written to the Fifo Data or Checksum Registers
`
`and microprocessor parity is enabled.
`
`Clk
`
`The clock input is used to generate some of the
`
`is expected to be in the lD—20 Mhz
`
`chip timing. It
`range.
`
`Read En, Write En
`
`During microprocessor accesses, while CS is true,
`the direction of
`the
`
`these
`
`signals
`
`determine
`
`microprocessor accesses.
`
`During data transfers in the
`
`these signals are data 'strobes used in
`WD mode
`conjunction with Port A Ack.
`'
`
`SUBSHTUTE SHEET
`
`NetApp Ex. 1002, pg. 1206
`
`
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`W0 91/03788
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`PCTIUS90/0471 1
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`-35-
`
`Port 3 60-07, 10-17, 20-27, 30-37,
`Port B is a 32 bit data port.
`
`0P—3P
`
`There is one odd
`
`parity bit for each byte.
`
`Port B OP is the parity of
`
`bits 00-07, PortB 1P is the parity of bits 10-17, Port-
`
`B 2P is the parity of bits 20-27, and Port 3 3P is the
`
`parity of bits 30-37.
`
`B select, B Reg, B Ack, Parity Sync, B Output Enable
`
`These signals are used in the data transfer mode to
`control the handshake of data on Port B. Port B Reg
`
`and Port B Ack are both gated with Port 3 Select.
`The Port B Ack signal is used to strobe the data on
`the Port B data lines.
`The parity sync signal is
`
`used to indicate to a chip configured as the parity
`
`chip to indicate that-the last words of data involved
`in the parity accumulation are on Port B.
`The Port P
`data lines will only be driven by the Fifo chip if all
`
`of the following conditions are met:
`a.
`the
`data transfer is from Port A to Port 8;
`
`b.
`
`c.
`d.
`
`Reset
`
`the
`
`Port 8 select signal is true;
`
`the Port B output enable signal is true; and
`the
`chip is not configured as the parity chip
`the Parity
`or it is in parity correct mode and
`.Sync signal is true.
`
`This signal resets all the registers within the
`
`chip and causes all bidirectional pins to be in a high
`impedance state}
`
`DEE§BIEI1QN_QE_QEEEAILQfl
`
`' ugrmaL_gpg;a:ign.
`isimple FIFO chip.
`RAM buffers
`in a
`
`Normally the chip acts as
`
`a
`
`A FIFO is simulated by using two
`
`simple ping-pong mode.
`
`It
`
`is
`
`that data is burst into
`intended, but not mandatory,
`or out of the FIFO on Port B. This is done by holding
`
`low and pulsing the Port B Ask
`Port B Sel signal
`signal. When transferring data from Port B to Port A,
`
`gusgrnute sum s
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`NetApp Ex. 1002, pg. 1207
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`-37..
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`data is first written into RAM X and when this is
`
`full,
`
`the data paths will be switched such that Port
`
`8 may start writing to RAM Y. Meanwhile the chip will
`begin emptying RAM X to Port A.
`When RAM Ylis full
`
`and RAM X empty the data paths will be switched again
`such that Port B may reload RAM X and
`Port A may
`
`empty RAM Y.
`
`V
`
` . This is the default mode and
`
`In this mode the
`the chip is reset to this condition.
`chip waits for a master
`such as one of
`the SCSI
`
`adapter chips 542 to raise Port A Request for data
`transfer.
`
`If data is available the Fifo chip will
`respond with Port A Ack/Rdy.
`
`_
`
`The chip may be configured to run
`.22z;_A_flQ_Mg§§.
`in the WD or Western Digital mode.
`In this mode the
`chip must be configured as a slave on Port A.
`It
`
`differs from the default slave mode in that the chip
`or Write
`responds with Read Enable
`Enable
`as
`appropriate together with Port A Ack/Rdy. This mode
`is intended to allow the chip to be interfaced to the
`
`Western Digital 33C93A SCSI chip or the NCR 53C9O SCSI
`chip.
`
`£grt_A_Ma§;gr;Mg§e. When the chip is configured as
`
`a master, it will raise Port A Ask/Rdy when it is
`ready for data transfer.
`
`This signal is expected to
`
`be tied to the Request input of a DMA controller which
`
`will respond with Port A Req when data is available.
`the
`
`In order to allow the DMA controller to burst,
`
`Port A Ack/Rdy signal will only be negated after every
`8 or 16 bytes transferred.
`
`In parallel write
`mode, the chip is configured to be the parity chip for
`a parallel transfer from Port 3 to Port A.-
`In this
`mode,
`
`when Port B select and Port 8 Request are
`asserted, data is written into RAM X or RAM Y each
`
`time the Part B Ack signal is received. For the first
`
`8_U_B_S_TlTUTE SHEET
`
`l
`
`NetApp Ex. 1002, pg. 1208
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`
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`WO 91/03788
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`PCT/US90l0471l
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`-33-
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`128 bytes data is simply copied into the
`block of
`selected RAM. The next 128 bytes driven on Part B will
`
`be exclusive-ORed with the first
`
`128 bytes.
`
`This
`
`procedure will be repeated for all drives such that
`The Parity
`the parity is accumulated in this chip.
`
`Sync signal should be asserted to the parallel chip
`
`together with the last block of
`
`128 bytes.
`
`This
`
`enables the chip to switch access to the other RAM and
`start accumulating a new 128 bytes of parity.
`'
` . This mode
`
`is set if all drives are being read and parity is to
`be checked.
`‘
`In this case the Parity Correct bit in
`the Data Transfer Configuration Register is not set.
`
`The parity chip will first read 128 bytes on Port A as
`in a normal read mode and then raise Port B Request.
`While
`it has
`this
`
`signal .asserted the chip will
`
`monitor the Port B Ack signals and exclusive-or the
`data on Port B with the data in its selected RAM. The
`
`Parity Sync should again be asserted with the last
`
`In this mode the chip will not
`block of 128 bytes.
`drive the Port B data lines but will check the output
`
`of its exclusive-or logic for zero.
`set at
`this time a parallel parity error will be
`
`If any bits are
`
`flagged.
`
`R2rL_E_2arallel_3aad_M9da_;_§2rra2t_Data.
`
`This
`
`mode is set by setting the Parity Correct bit in the
`
`In this case
`Data_Transfer Configuration Register.
`the chip will work exactly as in the check mode except
`
`that when Port B Output Enable, Port B Select and
`
`Parity Sync are true the data is driven onto the Port
`
`B data
`
`lines and a parallel parity check for zero is
`
`V not performed.
`In the normal mode it is expected that
`Eyt§_§wap.
`Port 3 bits 00-07 are the first byte, bits 10-17 the
`
`second byte, bits 20-21 the third byte, and bits 30-37
`
`the last byte of each word. The order of these bytes
`
`gunsmurzlysum
`
`NetApp Ex. 1002, pg. 1209
`
`
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`W0 91/03788
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`PCT/US90/04711
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`-39-
`
`may be changed by writing to the byte swap bits in the
`configuration register such that the byte address bits
`
`are inverted.
`
`The way the bytes are written and read
`
`also depend on whether the CPU interface is configured
`as 16 or 8 bits.
`The following table shows the byte
`alignments for the different possibilities for data
`transfer using the Port A Request
`/ “Acknowledge
`handshake:
`
`cpu
`I/F
`
`Invert
`Addr 1
`
`Invert
`Addr 0
`
`3
`
`False
`
`False
`
`False
`
`True
`
`True
`
`False
`
`True
`
`True
`
`False
`
`False
`
`False
`
`True
`
`True
`
`False
`
`True
`
`True
`
`Part B
`00-07
`
`Port A
`byte 0
`
`Port A
`byte 1
`
`Port A »
`byte 2
`
`Port A
`byte 3
`
`Port A
`byte 0
`
`uProc
`
`byte 0_
`Port A
`byte 1
`
`uProc
`byte 1
`
`Port 3
`10-17
`
`Port A
`byte 1
`
`Port A
`byte 0
`
`Port A
`byte 3
`
`Port A
`byte 2
`
`uProc
`byte 0
`
`Port A
`byte 0
`
`uProc
`byte1
`
`Port A
`byte 1
`
`Port 8
`20-27
`
`Port A
`byte 2
`
`Port A
`byte 3
`
`Port A
`byte 0
`
`Port A
`byte 1
`
`Port A
`byte 1
`
`uProc
`byte 1
`
`Port A
`byte 0
`
`uProc
`byte0
`
`Port B
`30-37
`
`Port A
`byte 1
`
`Port A
`byte 2
`
`Port A
`byte 1
`
`Port A
`byte 0
`
`uProc
`byte 1
`
`Port A
`byte 1
`
`uProc
`byte 0
`
`PortA
`byteo
`
`When the Fifo is accessed by reading or writing the
`Fifo Data Register through the microprocessor port in
`8 bit mode,
`the bytes are in the same order as the
`
`table above but the uProc data port is used instead of
`
`In 16 bit mode the table above applies.
`Port A.
`Q§g_Length_zransfe;§.
`If the data transfer is not
`
`a multiple
`
`of
`
`32 words,
`
`or
`
`128
`
`bytes ,
`
`the
`
`microprocessor must manipulate the internal registers
`of the chip to ensure all data is transferred. Port
`A Ack and Port B Req are normally not asserted until
`
`SUBSTITUTE SHEET
`
`NetApp Ex. 1002, pg. 1210
`
`
`
`W0 91/03788
`
`PC!‘IUS90/0471 1
`
`-90-
`
`all 32 words of the selected RAM are available. These
`signals may be forced by writing to the appropriate
`RAM status bits of the Data Transfer Status Register.
`
`When an odd length transfer has taken place the
`wait until
`both ports
`are
`microprocessor must
`
`It
`quiescent before manipulating any registers.
`should then reset both of the Enable Data Transfer
`
`bits for Port A and Port B in the Data Transfer
`
`Control Register.
`
`It must then determine by reading
`
`their Address Registers and the RAM Access Control
`
`Register whether RAM X or RAM Y holds the odd length
`data.
`It should then set the corresponding Address
`
`Register to a value of 20 hexadecimal, forcing the RAM
`full bit and setting the address to the first word.
`Finally the microprocessor should set the Enable Data_
`Transfer bits to allow the chip to complete the
`transfer.
`
`At this point the Fife chip will think that there
`
`are now a full 128 bytes of data in the RAM and will
`transfer 128 bytes if allowed to do so. The fact that
`some of
`these
`128 bytes are not valid must be
`
`‘recognized externally to the FIFO chip.
`
`BL
`
`f
`
`I T
`
`'
`
`'
`
`'
`
`r
`
`Register Address 0.
`
`This register is cleared by
`
`the reset signal.
`
`Bit
`
`0
`
`set if data transfers are to
`flD_Mgde.
`use
`the Western Digital .'WD33C93A
`protocol, otherwise
`the Adaptec
`6250
`protocol will be used.
`
`if this chip is to
`Set
`gazigy Chip.
`accumulate Port B parities.
`
`if the parity
` . set
`chip is to correct parallel parity on
`Port B.
`
`$L'BSTlT“TE W‘
`
`NetApp Ex. 1002, pg. 1211
`
`
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`W0 91/03788
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`PCTIU590/047-1 I «
`
`-91-
`
` . If set. the
`microprocessor data bits are combined
`with the Port A data bits to effectively
`produce a 16 bit Port. All accesses by
`the microprocessor as well as all data
`transferred using the Port A Request and
`Acknowledge handshake will
`transfer 16
`bits.
`
`to
` . ’ Set
`invert the least significant bit of Port
`A byte address.
`
`to
` . Set
`invert the most significant bit of Port
`A byte address.
`“
`
` - Set to enable the
`carry out of the 16 bit checksum adder to
`carry back into the least significant bit
`of the adder.
`
`to this bit will
`gggg-.. Writing a 1
`reset
`the other
`registers. This bit
`resets itself after a maximum of 2 clock
`cycles and will
`therefore normally be
`read as a 0. No other register should be
`written for a minimum of 4 clock cycles
`after writing to this bit.
`
`r
`
`‘
`
`R
`
`i
`
`Register Address 1.
`
`This register is cleared by
`
`the reset signal or by writing to the reset bit.
`
`Bit
`
`Bit
`
`Bit
`
`0 . Set to
`enable the Port A Req/Ack handshake.
`
`1
`
`2
`
` .» Set to
`enable the Port 3 Req/Ack handshake.
`
`If set, data transfer_
`2g;;_A_:g_2g:;_a.
`is from Port A to Port B.
`If reset, data
`transfer is from Port B to Port A.
`In
`order
`to avoid any glitches
`on
`the
`request
`lines,
`the state of
`this bit
`should not be altered at the same time as
`the enable data transfer bits 0 or
`1
`above.
`
`suasntufe sum
`
`NetApp Ex. 1002, pg. 1212
`
`
`
`wo 91/03788
`
`'
`
`~
`
`pcr/us9o/04711 -
`
`-92-
`
`Bit
`
`3 . set if parity
`is to be checked on the microprocessor
`interface.
`It will only be checked when
`writing to the Pifo Data Register or
`reading from the Fife Data or checksum
`Registers,
`or
`during
`a
`Port
`A
`Request/Acknowledge transfer in 16 hit
`mode.
`The chip will, however, always
`re-generate parity ensuring that correct
`parity is written to the RAM or read on
`the microprocessor interface.
`
` . Set if parity is
`to be checked on Port A.
`It is checked
`when accessing the Fife Data Register in
`16 bit mode,
`or during
`a Port
`A
`Request/Acknowledge transfer.
`The chip
`will, however, always re—generate parity
`ensuring that correct parity is written
`to the RAM or
`read on.
`the Port A
`interface.
`
`Port B
` . Set if
`If it is
`data has valid byte parities.
`generated
`not
`set, _byte parity is
`internally to the chip when writing to
`the RAMs.
`Byte parity is not checked
`when writing from Port B, but always
`checked when reading to Port B.
`
`Set to enable writing
`Qhegksug_£nahle.
`to the 16 bit checksum register.
`This
`register accumulates a 16 bit checksum
`for all RAM accesses, including accesses
`to the Fifo Data Register, as well as all
`writes to the checksum register.
`This
`bit must be reset before reading from the
`Checksum Register.
`
`Bit
`
`if Port A is to
`7 . Set
`operate in the master mode on Port A
`during the data transfer.
`
` m
`Register Address 2.
`This register is cleared by
`the reset signal or by writing to the reset bit.
`
`Bit
`
`0 . 8611 if BIIY bits
`are true in the RAM X, RAM Y, or Port A
`byte address registers.
`
`SUBSTITUTE SHEET
`
`NetApp Ex. 1002, pg. 1213
`
`
`
`“K)9U03flM
`
`PCT‘!US90/0471 I
`
`-93-
`
`if the
` . Set
`uProc Parity Enable bit
`is set and a
`parity
`error
`is
`detected
`on
`the
`microprocessor interface during any RAM
`access or write to the Checksum Register
`in 16 bit mode.
`
`Set if the Port A
`E9££_A_E§£iL!_E££Q:.
`Parity Enable bit
`is set and a parity
`error is detected on the Port A interface
`during any RAM access or write to the
`Checksum Register.
`
` . Set if
`the chip is configured as
`the‘ parity
`chip, is not in parity correct mode, and
`a non zero result is detected when the
`Parity Sync signal is true.
`It is also
`set whenever data is read out onto Port
`B and the data being read back through
`the
`bidirectional
`buffer
`does
`not
`compare.
`
`Set
`29;; B gytgs 0-3 Eggitx Erggz.
`whenever the data being read out of the
`RAMs on the Port B side has bad parity.
`
`Ram_A2225s_Q9ntr2l_B£9is:§r__iBsadLflrital
`
`Register Address 3. This register is cleared by
`
`the reset signal or-by writing to the reset bit. The
`
`Enable Data Transfer bits in the Data Transfer Control
`Register must be reset before attempting to write to
`
`this register, else the write will be ignored.
`Bit
`0 . This bit is the
`'
`least significant byte address bit.
`It
`is read directly bypassing any inversion
`done by the invert bit
`in the Data
`Transfer configuration Register.
`
`29;; A byte address 1. This bit is the
`most significant byte address bit.
`It is
`read directly bypassing any inversion
`done by the invert bit
`in the Data
`Transfer Configuration Register.
`
`3AM Z.
`Pgr; A fig
`accessing RAM Y,
`accessing RAM X .
`
`set if Port A is
`and reset
`if it
`is
`
`SUBSTITUTE SHEET
`
`NetApp Ex. 1002, pg. 1214
`
`
`
`W0 91/03788
`
`.
`
`PCT‘IU590/0471 I
`
`-
`
`-94-
`
`if Dart 3 is
`set
`29rr_JL_:g_JunL_x.‘
`accessing RAM Y,
`and reset
`if it is
`accessing RAM X .
`
`If the chip is configured to
`Lgng_fiu;§;.
`transfer data on Port A as a master, and
`this bit is reset,
`the chip will only
`negate Port A Ack/Rdy after every 8
`bytes, or 4 words in 16 bit made, have
`been transferred.
`If this bit is set,
`Port A Ack/Rdy will be negated every 16
`bytes, or 8 words in 16 bit mode.
`'
`
`Bits 5-7 N9:_Hasd.
`
`Ba” x E33.
`
`E
`
`1
`
`[
`
`3
`
`.
`
`I
`
`‘Register Address 4.
`
`This register is cleared by
`
`the reset signal or by writing to the reset bit.
`
`The
`
`Enable Data Transfer bits in the Data Transfer Control
`
`Register must be reset before attempting to write to
`
`this register, else the write will be ignored.
`Bits of-4
`RAM x word address
`Bit
`5
`RAM X full
`Bits 6-7
`Not Used
`
`BAH_X.AQQ£2§§_B§9iE£££_lE§§§£E£i£2l
`
`Register Address 5.
`
`This register is cleared by
`
`the reset signal or by writing to the reset bit. The
`Enable Data Transfer bits in the Data Transfer Control
`
`Register must_be reset before attempting to write to
`
`this register, else the write will be ignored.
`Bits 0-4
`RAM Y word address
`Bit
`5
`RAM Y full
`
`Bits 6-7
`
`Not Used
`
`
`
`Register Address 6. The Enable Data Transfer bits
`
`in the Data Transfer Control Register must be reset
`
`before attempting to write to this register, else the
`write will be ignored.
`The rort A to Port B bit in
`
`SUBSTITUTE SHEET
`
`NetApp Ex. 1002, pg. 1215
`
`
`
`wo 9_1/03788
`
`PC!‘IUS90/04711
`
`the Data Transfer Control register must also be set
`
`-95-
`
`the RAM
`If it is not,
`before writing this register.
`controls will be incremented but no data will be
`written to the RAM.
`
`For consistency,
`
`the Port A to
`
`PortB should be reset prior to reading this register.
`Bits 0-7 are Fifo Data.
`The microprocessor may
`
`- access the FIFO by reading or writing this register.
`
`The RAM control registers are updated as if the access
`
`was using Port A.
`
`If the chip is configured with a 16
`
`bit CPU Interface the most significant byte will use
`
`the Port A 0-7 data lines, and each Port A access will
`
`increment the Port A byte address by 2.
`
` 1m
`
`Register Address 7.
`
`This register is cleared by
`
`the reset signal or by writing to the reset hit.
`Bits
`The
`0-7
`are Checksum Data.
`chip will
`
`accumulate a 16 bit checksum for all Port A accesses.
`
`If the chip is configured with a 16 bit CPU interface,
`
`the most significant byte is read on the Port A 0-7
`If data is written directly
`to this
`
`data lines.
`
`register it is added to the current contents rather
`
`It is important to note that
`than overwriting them.
`the Checksum Enable bit in the Data.Transfer control
`
`Register must be set to write this register and reset
`to read it.
`
`EBQQRAQMING EHE FLEQ Qfllg
`
`In general the fifo chip is programmed by writing
`to the data
`transfer
`configuration and
`control
`
`registers to enable a data transfer, and by reading
`the data transfer status register at the end of the
`
`transfer to check the completion status. Usually the
`
`data transfer itself will
`
`take place with both the
`
`Port A and the Port 8 handshakes enabled, and in this
`
`case the data transfer itself should be done without
`
`SUBSTITUTE SHEET
`
`NetApp Ex. 1002, pg. 1216
`
`
`
`wo 9i/03738
`
`PCT/US90/04711“
`
`any other
`
`microprocessor.
`
`interaction .
`
`In
`
`some
`
`-95-
`
`applications, however, the Port A handshake may not be
`enabled,
`it will
`be
`for
`the
`
`necessary
`
`and
`
`microprocessor to fill or empty the fifo by repeatedly
`
`writing or reading the Fifo Data Register.
`
`Since the fifo chip has no knowledgeof any byte
`
`counts,
`
`there is no way of
`
`telling when any data
`
`transfer is complete by reading any register within
`this chip itself. Determination of whether the data
`
`transfer has been completed must therefore be done by
`some other circuitry outside this chip.
`
`The following C language routines illustrate how
`
`the parity FIFO chip may be programmed. The routines
`
`assume that both Port A and the microprocessor port
`
`are connected to the system microprocessor, and return
`
`a
`
`size code of
`
`16 bits, but
`
`that
`
`the hardware
`
`addresses the Fifo chip as long 32 bit registers.
`
`struct FlFO__regs {
`unsigned char ccnfig.a1,a2,a3 ;
`unsigned char control,b1,b2,b3;
`unsigned char status,c1,c2,c3;
`unsigned char ram access_controI,d1,d2,d3;
`unsigned char ram:X_addr.e1.e2,e3;
`unsigned char ram_Y__addr,f1,i2.f3;
`unsigned long data;
`I}1nsigned Int checksum.h1;
`
`#define FIFO1 ((struct FlF0__regs*) FIFO_BASE;ADDRESS)
`I #deflne FIFO RESET 0x80
`#define FlFO'16 BITS 0x08
`#define F|FO:CKRHY__WRAP 0X40
`#define F|F0_PORT A_ENABLE 0x01
`#define FlFO_PORT:B_ENABLE 0x02
`#deflne FlFO_PORT_ENABLES oxos
`#define F|FO__PORT A TO 3 0x04 -
`#define F|FO_CHEC1-(SUM-ENABLE 0X40
`#deflne FlFO_DATA__IN_RKM 0x01
`#dei_ine FlFO_FORCE_RAM_FULL 0x20
`
`#define PORT A__TO PORT B(fifo) ((fifo~> control) & 0x04)
`#de1;ne POR‘l’:A_BYTE_ADDRESS(fi'fo)’ ((fito->ram_access__oontrol) &
`0x03
`‘
`»
`#dsfine PORT A_TO_RAM Y(fifo)
`((fifo->ram_aocess_oontrol) &
`0x04)
`#define POR1':B_TO_RAM:Y(fifo)
`((fifo-> ram_aooess__oontrol) & 0x08)
`
`8_llB_8__TlTllTE sum
`
`NetApp Ex. 1002, pg. 1217
`
`
`
`WO 91/03788
`
`PCTIUS90/0471 I
`
`The following routine Initiates a Ftfo data transfer using two
`values passed to it.
`
`config_data
`
`This is the data to be written to the configuration register.
`
`control_data This is the data to be written to the Data Transfer Control
`Register.
`If the data transfer is to take place
`automatically using both the Port Aand Port B
`handshakes. both data transfer enables bits should be
`set in this parameter.
`fltflitifiittttttttttttiitttiltttttintfiittitdiiittiitittttftifil
`
`FlFO_inltiate_data_transfer(conflg__data, control_data)
`unsigned char config__data, oontroI_data;
`{
`
`.
`FlFO_FlESEl';
`
`/* Set
`
`/* Set
`
`FlFO1->oonfig = oonfig data |
`Configuration value & Reset ‘/
`FlFO1->control = control data & (~FlF0__PORT_ENABLES):
`everything but enaBles */
`FlFO1->control = control_data;
`enables */
`
`T
`
`/* Set data transfer
`
`} l
`
`it!*itiittiftitttR*flfi**k&*tflfi**fii*ifl*i*ti*Iii§iiii**iifiii!*
`The following routine forces the transfer of any odd bytes that
`have been left in the Fnfo at the end of a data transfer.
`It first disables both ports, then forces the Ram Full bits, and then
`re-enables the appropriate Port.
`ititiiiiiittiiiitiittkitf
`
`fittfltttflfifififflfitflkfil
`
`FlFO_force_odd_length__transfer0
`{
`
`«I
`
`»
`A
`V
`FlFO1->control &= ~FlF0_PORT_ENABLES: /* Disable Ports A & B
`I
`if (PORT A TO PORT_B(FlFO1)) {
`it‘(Pbn1’A TO_RAM__Y(FlFO1)) {
`FIFG1->ram_Y_addr = FlFO__FORCE_RAM_FULL; /*
`
`Set HAM Y full */
`
`} e
`
`} e
`
`lse {
`
`lse FIFO1->ram_X_addr = FlFO_FORCE_RAM_FULL:
`RAM X full */
`FlFO1->control |= FlFO_POFtT__B_ENABLE;
`Re-Enable Part B */
`
`/* _Set
`
`/*
`
`if (PORT B TO_RAM Y(FlFO1)) {
`FIF51-> ram_Y_addr = F|FO_FORCE_FlAM___FULL;
`
`/*
`
`Set RAM Y full */
`.
`}
`else FlF0t->ram_X_addr = FlFO_FORCE_RAM_FULL; /* Set
`RAM X fuu */
`
`EZSBSTITIETE SHEET
`
`NetApp Ex. 1002, pg. 1218
`
`
`
`WO 91/03788
`
`PCT/U590/04711
`
`-98-
`
`' FlFO1->control | = FlFO__PORT_A'__ENABLE;
`Re-Enable Port A */
`}
`
`/*
`
`} l
`
`ttiffttittfitttfitfittfitttififtititiiiii-ktitfititttiitttiii-itit
`The following routine returns how many odd bytes have been
`lett in the Fifo at the end of a data transfer.
`itkttttiittttiiii-tt*tti**i**k*§1"t'**i**i'**I'***iliftifktffltflfktl
`
`int FlF0_count_cdd_byles0
`
`int number odd_bytes:
`number_ccTd_bytes=0;
`if (FIFO1->status & FIFO DATA IN RAM)
`If (PORT_A TO_PURT_B-(FIF-01)) {
`num'ber odd bytes =
`(PORT_A_BYTE_ADDFlES§(FlF61)) :
`if (PORT_A_TO_RAM Y(FlFO1))
`nurnber__odd_Bytes + = (FIFO1->ram_Y_addr) *
`
`4 ;
`
`else numlaer_odd__bytes + = (FIFO1->ram_X_addr) * 4;
`.
`
`ii (PORT_B 'l'O_RAM Y(FlFO1))
`num'ber odd_Bytes = (FIFO1->ram_Y_addr) * 4 ;
`else number_o3d_bytes = (FIFO1->ram_X_addr) " 4 ;
`
`}
`else {
`
`}
`
`}
`return (number_odd_bytes);
`
`I
`
`} l
`
`***kif**i*****t**k***iift***t&**I*1'*t*Q1ti*fi'*t**tt**ti*fiit*
`The following routine tests the microprocessor lntertace of the
`It first writes and reads the first 6 registers.
`it then writes 1s. Os, and
`chip.
`an address pattern to the RAM, reading the data back and checking it.
`
`The test returns a bit significant error code where each bit
`represents the address of the registers that failed.
`
`Bit 0 = oontlg register tailed
`Bit 1 = control register failed
`Bit 2 = status register failed
`Bit 3 = ram access control register failed
`Bit 4 = ram X address register failed
`Bit 5 = ram Y address register failed
`Bit 6 = data register failed
`Bit 7 = checksum register failed
`i **&Rflfl***K%***fif*#fl!
`
`#deiine RAM_DEPTH 64
`
`/* number of long words in Fife Rarn‘ *1
`
`reg__expected_data[6] = {0x7F. OxFF. 0x00, 0x1F. 0x3F. Ox3F };
`
`8llli§_TlT|lTE slim
`
`NetApp Ex. 1002, pg. 1219
`
`
`
`W0 91/03788
`
`'
`
`PC!‘/US90/04711
`
`-99..
`
`char FlFO_uprocessor_interface_test0
`{
`
`unsigned long test data;
`char *register_addr_;
`Int I;
`char j,error,
`FIFO1->oonfig = FIFO_FlESEI';
`error=O;
`egister_addr =(char *) FIFO1;
`i=1:
`
`/* first test registers 0 thru 5 */
`
`for (i=0; i<6; i++) {
`/' write test data */
`*register__addr = oxFF;
`if (*register addr I= reg_expeoted__data[|]) error. I = J;
`*register_aHdr = 0;
`/* wnte Os to register */
`if (*register_addr) error I: j;
`'
`/* write test data again */
`*register_addr = 0xFF;
`it (*regIster_addr l= reg_expected_data[i]) error |= J;
`FIFO1->oonfig = FIFO RESEI;
`/* reset the chip */
`if (*regIster_addr) error"| = j; /_* register should be 0 */
`reg|ster_addr+ +;
`/* go to next register */
`]<<=n
`
`/" now test Ram data & checksum registers
`test is throughout Ram & then test as */
`
`tor (test_data = -1; test_data l= 1; test_data+ +)
`& Os */
`
`{
`
`/* test for 1s
`
`FIFO1->oonfig = FIFO RESET I FIFO 16_BITS :
`FIFO1->oontrol = FIFO" POFiT_A_TO_E;
`for G=0;i<RAM_DEPTHfi++)
`
`/* write data to RAM
`
`*/
`
`FIF01->data = test_data;
`FIFO1->oontroI = 0;
`for G=O;i<RAM_DEF’I'H;i+ +)
`If (FIFO1->data I= test_data) error |= j;
`
`check data */
`if (FIFO1->checksum) error |= 0x80;
`should = O */
`.
`}
`
`‘
`/* read &
`
`/* checksum
`
`/" new test Ram data with address pattern
`uses a different pattern for every byte "/
`
`/* address pattern start */
`test data=oxooo1o203;
`FIFO1->config = FlF0_RESET | FIFO_16_BITS |
`FIFO CARFiY_WFlAP;
`FIFO1->oontroI = FIFO POFIT_A_TO_B |
`FIFO CHECKSUM ENABLE?
`far (i=0;i<FlAII7T_DEPTH;i++) {
`FIFO1->data = test_data;
`
`.
`
`/' write address pattern */
`
`SUBSTITUTE SHEET
`
`NetApp Ex.
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