`
`PART (cid:21)
`
`
`
`-114-
`
`uP Data 0-7, uP Data P, uPAdd 0-2,
`
`CS
`
`These
`
`signals are used by a microprocessor
`
`to
`
`address
`
`the programmable registers within the 'chip.
`
`The odd parity signal uP Data P is only checked when
`data is written to the Fifo Data or Checksum Registers
`
`and microprocessor parity is enabled.
`
`elk
`
`The clock input
`
`is nsed to generate some of the
`
`chip timing. It
`
`is expected to_be in the 10-20 Mhz
`
`range.
`
`Read En, Write En
`
`During microprocessor accesses, while CS is true,
`
`these
`
`signals
`
`determine
`
`the direction of
`
`the
`
`microprocessor accesses. During data transfers in the
`WD made‘
`these
`signals
`are data
`strobes
`used
`in
`conjunction with Port A Ack.
`
`Port 3 00-07, 10-17, 20-27, 30-37, OP-3P
`
`Port B is a 32 bit data port.
`
`There is one odd
`
`parity bit for each byte. Port B OP is the parity of
`
`bits 00-O7, PortB 1P is the parity of bits 10-17, Port
`
`B 2P is the parity of bits 20-27, and Port B 3P is the
`
`parity of bits 30-37.
`
`Attorney Docket No. :AUSP'l209 _'
`WP1/WSW/AUSP/7209.001
`,
`
`a/24/39-7
`
`NetApp Ex. 1002, pg. 601
`
`
`
`-115-
`
`B select, 3 Req, B Ack, Parity Sync, B Output Enable
`
`These signals are used in the data transfer mode
`
`to control the handshake of data on Port 3. Port 3 Req
`
`and Part B Ack are both gated with Port 8 Select.
`
`‘The Port B Ack signal is used to strobe the data on the
`
`Port B data lines.
`
`The parity sync signal is used to
`
`indicate to a chip configured as the parity chip to
`
`indicate that
`
`the last words of data involved in the
`
`parity accumulation are on Port B.
`
`The gort B data
`
`lines will only be driven by the Fifo chip if all of
`
`the following conditions are met:
`
`"the data transfer is from Port A to Port 3;
`
`the Port 3 select signal is true;
`
`the Port B output enable signal is true; and
`
`the chip is not configured as the parity chip
`or
`it
`is in parity correct mode
`and ‘the
`Parity Sync signal is true.
`
`Reset
`
`This signal resets all
`
`the registers within the
`
`chip'and causes all bidirectional pins to be in a high
`
`impedance state.
`
`0
`
`o E
`
`on
`
`ug;maL_Qpg;a;ign.
`
`Normally the chip acts as a
`
`simple FIFO chip.
`
`A FIFO is simulated by using two RAM
`
`buffers in a simple ping—pong mode.
`
`It is intended,
`
`but not mandatory,
`
`that data is burst
`
`into or out of
`
`Attorney Docket No.:AUSP7209
`WP1/WSW/AUSP/7209.001
`
`8/24/89-7
`
`NetApp Ex. 1002, pg. 602
`
`
`
`C;
`
`-116-
`
`the FIFO on Port 8. This is done by holding Part B Sel
`
`signal
`
`low and pulsing the Part B Ack signal. When
`
`transferring data from Port B to Port A, data is first
`
`written into RAM X and when this is full,
`
`the data.
`
`paths will be
`
`switched such "that Port
`
`8 may start
`
`writing to RAM Y.
`
`_Meanwhile
`
`the chip willh begin
`
`emptying RAM X to Port A.
`
`when RAM Y is full and RAM
`
`if empty the data paths will be switched again such that
`
`Port B may reload RAM X and Port A may empty RAM Y.
`
` . This is the default mode and
`
`the chip is reset to this condition.
`
`In this mode the
`
`chip waits for a master such as one of the SCSI adapter
`
`chips 542 to raise Port A ‘Request for data transfer.
`
`If data is available the Fifo chip will
`
`respond with
`
`Port A Ack/Rdy.
`
`ggrt A WD Mode.
`
`The chip may be configured to
`
`run in the WD or Western Digital mode.
`
`In this mode
`
`the chip must be configured as a slave on Port A.
`
`It
`
`differs from the default slave mode
`
`in that
`
`the--chip
`
`responds with Read Enable or Write
`
`Enab1e_ as
`
`appropriate together with Port A Ack/Rdy. This mode is
`
`intended to allow the chip to he interfaced to the
`
`Western Digital 33C93A SCSI chip or the NCR 53090 SCSI
`
`chip.
`
`o
`
`Mas. e
`
`M
`
`.
`
`when the chip is configured
`
`as a master, it will -raise Port A Ack/Rdy when it is
`
`Attorney Docket No. :AUSP’I209
`W191/WSW/AUSP/7209.001
`
`'
`
`8/24/89-7
`
`NetApp Ex. 1002, pg. 603
`
`
`
`-111-
`
`ready for data transfer. This signal is expected to be
`
`tied to the Request
`
`input of a DMA controller which
`
`will
`
`respond with Port A Req when data is available.
`
`In order to allow the DMA controller to burst,
`
`the Port
`
`A Ack/Rdy signal will only be negated after every 8 or
`
`16 bytes transferred.
`
`29;; § ggggllgl wgigg Mode.
`
`In parallel write
`
`node,
`
`the chip is configured to be the parity chip for
`
`a parallel
`
`transfer from Port B to Port A.
`
`In this
`
`mode, when Port
`
`B Select
`
`and Port
`
`8 Request are
`
`asserted, data is written into RAM X or RAM’! each
`
`time the Part B Ack signal is received.
`
`For the first
`
`block of
`
`128 bytes data is simply copied into the
`
`selected RAM. The next 128 bytes driven on Port B will
`
`be exclusive-0Red with the first
`
`128 bytes.
`
`This
`
`procedure will be repeated for all drives such that the
`parity is accumulated in this chip.
`The Parity sync
`signal should be asserted to the parallel chip together
`
`with'the last block of
`
`128 bytes.
`
`This enables the
`
`chip to switch_ access
`
`to the other
`
`RAM and start
`
`accumulating a new 128 bytes of parity.
`
`gort B Parallel Read fiode — Check Data.
`
`This
`
`mode is set if all drives are being read and parity is
`
`to be cheched.
`
`In this case the Parity Correct bit in
`
`the Data Transfer Configuration Register
`
`is not set.
`
`The parity chip will first read 128 bytes on Port A as
`
`Attorney Docket No.:AUSP7209
`WP1/WSW/AUSP/7209.001
`
`8/24/89-7
`
`NetApp Ex. 1002, pg. 604
`
`
`
`C
`
`—1lB—
`
`in a-normal read mode and then raise Port B Request.
`
`While it has this signal asserted the chip will monitor
`
`the Port 8 Ask signals and exclusive—or
`
`the data on
`
`Port B with the data in its selected RAM.
`
`The Parity
`
`sync should again be asserted with the last block of
`
`128 bytes.
`
`In this mode the chip will not drive the
`
`Port B data lines but will check the output of
`
`its
`
`exclusive—or
`
`logic for zero.
`
`If any bits are set at
`
`this time a parallel parity error will be flagged.
`
`29;; 3 Eagallel ggad Mode — ggrregt Qata.
`
`This“
`
`mode
`
`is set by setting the harity Correct bit in the
`
`Data Transfer Configuration Register.
`
`In this case the
`
`chip will work exactly as in the check mode except that
`
`when Port B Output Enable, Port 8 Select and Parity
`
`sync are true the data is driven onto the Port 3 data
`
`lines and a parallel parity check for zero is not
`
`_performed..
`
`§ytg__§uap.
`
`In the normal. mode it is expected
`
`that‘Port B bits 00-07 are the first byte, bits 10-17
`
`the second byte, bits 20-27 the third byte, and bits
`
`30-37 the last byte of each word.
`
`The order of these
`
`bytes may be changed by writing to the byte swap bits
`
`in the
`
`configuration register
`
`such
`
`that
`
`the byte
`
`address bits are inverted.
`
`The yway
`
`the bytes are
`
`written and
`
`read also depend
`
`on whether
`
`the
`
`CPU
`
`interface is configured as 16 or 8 bits.
`
`The following
`
`Attorney Docket No.:AUSP7209
`WP1/WSW/AUSP/7209.001
`
`8/24/89-7
`
`NetApp Ex. 1002, pg. 605
`
`
`
`-119-
`
`table shows _the byte alignments
`
`for
`
`the different
`
`possibilities
`
`for data
`
`transfer using the Port
`
`A
`
`Request / Acknowledge handshake:
`
`CPU
`I/F
`
`Invert
`Addr 1
`
`Invert
`
`Port 8'
`
`Port n
`10-17
`
`byte 1
`
`byte 1
`
`byte 0
`
`byte 0
`
`. uProc
`byte 1
`
`Port A
`byte 1
`
`uProc
`byte 0
`
`Port A
`byte 0
`
`When the Fifo is accessed by reading or writing
`
`the Fifo Data Register through the microprocessor port
`
`in 8 bit mode,
`
`the bytes are in the same order as the
`
`‘table above but the uProc data port is used instead of
`
`Port A.
`
`In 16 bit mode the table above applies.
`
`d
`
`n
`
`h Tran er .
`
`If the data transfer
`
`is
`
`not
`
`a multiple
`
`of
`
`32
`
`fiords,
`
`or
`
`128 bytes,
`
`the
`
`microprocessor must manipulate the internal registers
`
`of the chip to ensure all data is transferred. Port A
`
`Ask and Port B Req are normally not asserted until all
`
`Attorney Docket No.:AUSP7209
`--W?1/WSW/AUSP/7209.001
`
`8/24/89-7
`
`NetApp Ex. 1002, pg. 606
`
`
`
`-120-
`
`32 words of
`
`the selected RAM are available.
`
`These
`
`signals may be forced by writing to the appropriate RAM
`
`status bits of the Data Transfer Status Register.
`
`when an odd length transfer has taken place the
`
`microprocessor must wait until both ports are quiescent
`
`before manipulating any registers.
`
`It
`
`should then
`
`reset both of the Enable Data Transfer bits for Port A
`
`and Port B.in the Data Transfer Control Register.
`
`It
`
`must then determine by reading their Address Registers
`
`and the RAM Access Control Register whether RAM x or
`
`RAM Y holds the odd length data.
`
`It should then set
`
`the corresponding Address Register
`to a value of
`20
`hexadecimal,
`forcing the RAM full bit and setting the
`
`address to the first word. Finally the microprocessor
`
`should set the Enable Data Transfer bits to allow the
`chip to complete the transfer.
`-
`
`At this point the 1-‘iffo chip will think "that there
`
`are now a full 128 bytes of data in the RAM and will
`
`transfer 128 bytes if allowed to do so.
`
`The fact that _
`
`some
`
`of
`
`these
`
`128 bytes
`
`are not valid must
`
`be
`
`recognized externally to the FIFO chip.
`
`Attorney Docket No.:AUSP7209
`WP1/WSW/AUSP/7209.001
`
`8/24/89-7
`
`NetApp Ex. 1002, pg. 607
`
`
`
`
`
`Register Address 0.
`
`This register is cleared by
`
`the reset signal.
`
`Bit
`
`0
`
`Set if data transfers are to
`WD Mggg.
`use
`the Western Digital WD33C93A
`protocol, otherwise
`the Adaptec
`6250
`protocol will be used.
`
`if this chip is to
`Set
`garitx Quip.
`accumulate Port B parities.
`
`the
`if
`set
`Parity Cggrec; Mode.
`parity chip is to correct ‘ parallel
`parity on Port 3.
`
`If set,
`.
`i
`i
`16
`CPU
`the microprocessor data bits
`are
`combined with the Port A data bits to
`effectively produce a 16 bit Port. All
`accesses by the microprocessor as well
`as all data transferred using the Port A
`Request and Acknowledge handshake will
`transfer 16 bits.
`
`Invert Port A b
`invert
`the
`least
`Port A byte address.
`
`to
`Set
`.
`e addre
`significant bit of
`
`to
`Set
`.
`Invert Port A byte address
`invert the most significant bit of Port
`A byte address.
`'
`
`Set to enable the
`Checkgum Carry Wrap.
`carry out of
`the 16 bit checksum adder
`to carry back into the least significant
`bit of the adder.
`
`to this bit will
`1
`geset. Writing a.
`registers. This bit
`reset
`the other
`resets
`itself after
`a maximum of
`2
`clock cycles and will therefore normally
`be
`read as
`a 0.
`No other
`register
`should be written for a minimum of
`4
`clock cycles after writing to this bit.
`
`Attorney Docket No.:AUSP1209
`WP1/WSW/AUSP/7209.001
`'
`
`.
`
`8/24/89—7
`
`NetApp Ex. 1002, pg. 608
`
`
`
`_
`
`.
`
`Register Address 1.
`
`This register is cleared by
`
`the reset signal or by writing to the reset bit.
`
`Bit
`
`Bit
`
`0 . Set to
`enable the Port A Reg/Ack handshake.
`
`Set to
`B.
`n
`r n
`Da
`b
`enable the Port B Reg/Ack handshake.
`
`set, data
`If
`.
`o
`or
`transfer is from Port A to Port B.
`If
`reset, data transfer is from Port B to
`Port A.
`In order to avoid any glitches
`on the request lines,
`the state of this
`bit
`should not be altered at-the same
`time as the enable data-transfer bits 0
`or 1 above.
`"
`
`uPrggg§§gr Parity Enable. Set if parity
`is to be checked on the microprocessor
`interface.
`It will only be checked when
`writing to the Fifo Data Register or
`reading from the Fifo Data or Checksum
`Registers,
`or during a Port
`A
`Request/Acknowledge‘
`transfer in 16 bit
`mode.
`The chip will, however, always
`re—generate parity ensuring that
`correct parity is written to the RAM or
`read on the microprocessor interface.
`
`Set if parity is
`.
`En
`A Pa
`to be checked on Port A.
`It is checked
`when accessing the Fifo Data Register in
`16 bit, mode,
`or during
`a Port —A-
`Request/Acknowledge transfer.
`The chip
`will, however, always re—generate parity
`ensuring that correct parity is written
`to the
`RAM or_ read on
`the Port A
`interface.
`
`Port B
`Set if
`29;; 5 Rarity Enable.
`If it is
`data has valid byte parities.
`generated
`not
`set,
`byte parity is
`internally to the chip when writing to
`the RAMs.
`Byte parity is not checked
`when writing from Port B, but always
`checked when reading to Port E.
`
`Attorney Docket No.:AUSP1209
`WPI/WSW/AUSP/7209.001
`
`8/24/89-7
`
`NetApp Ex. 1002, pg. 609
`
`
`
`-123-
`
`to enable writing
`Set
`§hggK§§m_§n§hLg.
`to the 16 bit checksum register.
`This
`register accumulates
`a 16 bit checksum
`for all
`RAM accesses,
`including
`accesses to the Fifo Data Register, as
`well
`as all writes
`to the
`checksum
`register. This bit must be reset before
`reading from the Checksum Register.
`
`if Port A is to
` . Set
`operate in the master mode on Port A
`during the data transfer.
`-
`
`Data
`
`r n fer
`
`a us Re '
`
`r
`
`e
`
`n1
`
`Register Address 2.
`
`This register is cleared by
`
`-
`
`the reset signal or by writing to the reset bit.
`
`Bit
`
`0
`
`- Data in RAM 3 or RAM Y. Set if any bits
`are true in the RAM X, RAM,Y, or Port A
`byte address registers.
`
`if the
`Set
`E or.
`P
`P rt
`Pr
`is set and a
`uProc Parity ‘Enable bit
`parity error.
`is detected on
`the
`microprocessor interface during any RAM
`access or write to the Checksum Register
`in 16 bit mode.
`-
`
`Set if the Port A
`Port A garity Errgg.
`Parity Enable bit is set and a parity
`error
`is detected on
`the Port
`A
`interface during any RAM access or write
`to the Checksum Register.
`
`set if
`.
`‘
`ri
`1
`P
`the parity
`the chip is configured as
`chip,
`is not in parity correct mode, and
`a non zero result is detected when the
`Parity Sync signal is true.
`It is also
`set whenever data is read out onto Port
`B and the data being read back through
`the bidirectional buffer
`does
`not
`compare.
`'
`
`Set
`.
`E
`ari
`0-
`e
`B
`B
`o
`whenever the data being read out of the
`RAMS on the Port B side has bad parity.
`
`Attorney Docket No.:AUsP7209
`WP1/WSW/AUSP/7209.001
`
`8/24/89-7
`
`NetApp Ex. 1002, pg. 610
`
`
`
`Bam_A222ss_Q9nLrel_Begis:sr__lBsadLflritel
`
`Register Address 3.
`
`This register is cleared by
`
`the reset signal or by writing to the reset bit.
`
`The
`
`Enable Data Transfer bits in the Data Transfer Control
`
`Register must be reset before attempting to write to
`
`this register, else the write will be ignored.
`
`Bit
`
`0
`
`£2rt_A_hxxs_address_Q- This bit is the
`least significant byte address bit.
`It
`is read directly bypassing any inversion
`done by the ‘invert bit
`in the Data
`Transfer Configuration Register.
`
`22rL_AtJu¢s_a§drsss_l- "This bit is the
`most significant byte address bit.
`It
`is read directly bypassing any inversion
`done
`by
`the invert bit
`in the Data
`Transfer Configuration-Register.
`
`Port A to RAM Y.
`accessing RAM Y,
`accessing RAM X .
`
`Y.
`o
`B
`P
`accessing RAM Y,
`accessing RAM X .
`
`.A
`Set if Port
`and reset
`if it
`
`set if Port B
`and reset
`if it
`
`is
`is
`
`‘
`
`If the chip is configured
`;gng_figr§§.
`to transfer data on Port A as a master,
`amd this bit
`is reset,
`the chip will
`only negate Port A Ack/Edy after every 8_
`bytes, or 4 words in 16 bit mode, have~
`been transferred.
`If this bit is set,
`Port A Ack/Rdy will be negated every 16
`bytes, or 8 words in 16 bit mode.
`
`Bits 5-7 ugg Used.
`
`dd
`
`i
`
`R ad Wri e
`
`Register Address 4.
`
`This register is cleared by
`
`the reset signal or by writing to the reset bit.
`
`The
`
`Enable Data Transfer bits in the Data Transfer Control
`
`Attorney Docket No.=Ausp72o9'
`WP1/WSW/AUSP/7209.001
`
`n
`
`8/24/89-7
`
`NetApp Ex. 1002, pg. 611
`
`
`
`-125-
`
`Register must be reset before attempting to write to
`
`this register, else the write will be ignored.
`
`Bits 0-4
`
`RAM X word address
`
`Bit
`
`5
`
`.
`
`RAM X full
`
`Bits 6-7
`
`Not Used
`
`r
`
`R
`
`'
`
`' e
`
`Register Address 5.
`
`This register is cleared by
`
`The
`the reset signal or by writing to the reset bit.
`Enable Data Transfer bits in the Data Transfer Control
`
`Register must be reset before attempting to write to
`
`this register, else the write will be ignored.‘
`
`Bits O-4
`
`RAM Y word address
`
`Bit
`
`5
`
`RAM i full
`
`Bits 6-7
`
`Not Used
`
`ata
`
`e iste '
`
`e d W ite
`
`Register Address 6.
`
`The Enable Data Transfer bits
`
`in the Data Transfer Control Register must be reset
`
`before attempting to write to this register, else the
`
`write will be ignored.
`
`The Port A to Port B bit in the
`
`Data Transfer Control register must also be set before
`
`writing this register.
`
`If it is not,
`
`the RAM controls
`
`will be incremented but no data will be written to the
`
`RAM.
`
`For consistency.
`
`the Port A to PortB should be
`
`reset prior to reading this register.
`
`Attorney Docket No.:AUSP7209
`WP1/WSW/AUSP/7209.001
`
`8/24/89-7
`
`NetApp Ex. 1002, pg. 612
`
`
`
`-126-
`
`Bits 0-7 are Fifo Data.
`
`The microprocessor may
`
`access the FIFO by reading or writing this register.
`
`The RAM control registers are updated as if the access
`
`was using Port A.
`
`If the chip is configured with a 16
`
`bit CPU Interface the most significant byte will use
`
`the.Port A 0-7 data lines, and each Port A access will
`
`increment the Port A byte address by 2.
`
`ggr; A Checkgum Register fkgadlflriggl
`
`Register Address 7.
`
`This register is cleared by
`
`the reset signal or by writing to the reset bit.
`
`Bits
`
`0-7
`
`are Checksum Data.
`
`The
`
`chip will
`
`accumulate a 16 bit checksum for all Port A accesses.
`
`If the chip is configured with a 16 bit CPU interface,
`
`the most significant byte is read on the Port A 0-7
`
`data lines.
`
`If data is written directly
`
`to this
`
`register it is added to the current contents rather
`than overwriting them. ‘It is important
`to_note that
`the Checksum Enable bit
`in the Data Transfer Control
`
`Register must be set to write this register and reset
`to read it.
`
`M
`
`O HIP
`
`In general
`
`the fifo chip is programmed by writing 4
`
`to the data
`
`transfer
`
`configuration and
`
`control
`
`registers to enable a data transfer,
`
`and by reading
`
`Attorney Docket No.:AUSP7209
`WP1/WSW/AUSP/7209.001
`
`8/24/89—7
`
`NetApp Ex. 1002, pg. 613
`
`
`
`-127-
`
`the data transfer status register at
`
`the end of
`
`the
`
`transfer to check the completion status. Usually the
`
`data transfer itself will take place with both the Port
`
`A and the Port B handshakes enabled, and in this case
`
`the data transfer itself should be done without any
`
`other microprocessor
`
`interaction.
`
`In
`
`some
`
`applications, however,
`
`the Port A handshake may not be
`
`enabled,
`
`and
`
`it will
`
`be necessary
`
`for
`
`the
`
`microprocessor to fill or empty the fifo by repeatedly
`
`writing or reading the Fifo Data Register.
`-
`since the fifo chip has no hnowledge of any byte
`
`counts;
`
`there is no way of‘
`
`telling when any data
`
`transfer is complete by reading any register within
`
`this chip itself.
`
`Determination of whether
`
`the data
`
`transfer has been completed must therefore be done by
`
`some other circuitry outside this chip.
`
`The following C language routines illustrate how
`
`the parity FIFO chip may be programmed.
`
`The routines
`
`assume that both Port A and the microprocessor port are
`
`connected to the system microprocessor, and return a
`
`size code of 16 bits,'but that the hardware addresses
`
`the Fifo chip as long 32 bit registers.
`
`Attorney Docket No. :AUSP7209
`WP1/WSW/AUSP/7209.001
`
`'
`
`a/24/39-7
`
`NetApp Ex. 1002, pg. 614
`
`
`
`atruct FIFO_regs (
`unsigned char config,al,a2,a3 ;
`unsigned char contro1,b1,b2,b3;
`unsigned char sratus,cl,c2,c3;
`unsigned char ram_access_control,dl,d2,d3;
`unsigned char ram_x_addr,e1;e2,e3;
`unsigned char ram_Y_addr,f1,f2,fJ;
`unsigned long data;
`unsigned int checksum,h1;
`I;
`
`#define FII.-‘O1-((struct
`
`l?IFO_regs*)
`
`I-‘IFO_BASE__ADDB.ESS)
`
`#define FIFO_flESET 0x80
`#define FII-‘O_l6_BI'l'S 0x08
`aderine FIFO_CARRY_WRAP 0x40
`#define I-‘Ill-‘O_POR‘l‘__A__ENABLE 0x01
`#define FIFO_PORT_B_ENABLE 0x02
`#define FIFO_PORT_ENABLES 0x03
`{marine I-‘IFD_PORT__A_TO_B 0x04
`#define FIFO_CHECKSUM_ENABLE 0x60
`fidefine FIFO__DA'1'A_IN_RAH 0x01
`gdefine 1=mo_ronca_v;An_1=uLL 0x20
`
`5. 0x04)
`)
`((fifo—> control
`aaetine PORT_A_'1'O_POR'1'_B(‘fifo)
`#define PORT_A_BYTE_ADDRESS(fifo) ((fife->ram_aceess_contro1) &
`0x03)
`_
`adetine PORI;fi;jO_§AM_Y(£ifo)
`-0x04)
`fidetine PORT_B_I0_RAM_Y(fifo)
`0x08)
`
`((fifo—) ram_access_eontro1 ) &
`
`((fifo-)ranL§ccess_pontrol ) &
`
`/itRttkkttfitflktflifiatfitttflkfiflkflttfifiktfl€ttfi$**#tt#tfitttttktttt
`The following routine initiates a Fifo data transfer using
`two values passed to it.
`'
`
`config_data
`
`This is the data to be written to the
`configuration register.
`
`contra1_data
`
`This is the data to be written to the Data
`Transfer Control Register.
`If the data'trans£er
`is to take place automatically using both the
`Port Aand Port 3 handshakes, hoth data transfer
`enables bits should be set in this parameter.
`fitttttttttttttttttfittttttttttttttttttfifittttfittz=:t::tt22:::/
`
`FIFO_initiate_data_transfer(config_data, contro1_data)
`unsigned char config_data, control_data;
`C
`
`FIFOI-)config = config_data I FIF0_RESET;
`Configuration value-& Reset */
`
`/‘ Set
`
`Attorney Docket No.:AUSP7209
`wr I/WSW/AUSP/7 209 . 00 1
`
`8/24/89-7
`
`NetApp Ex. 1002, pg. 615
`
`
`
`-129-
`
`FIFO1-)¢ontro1 - contro1_data G ('FIFO_PORT_ENABLES);
`"everything but enables */
`FIFO!->control = contro1_data ;
`enables */
`
`/* Set data transfer
`
`/* Set
`
`I /
`
`kifififitttfifikktktttfittktktfititttkttttktttkttRtttttfiktttttkttk
`The following routine forces the transfer of any odd bytes
`that have been left in the Fifo at the end of a data transfer.
`It first disables both parts,
`then forces the Ram Full bits, end'
`then re-enables the appropriate Port.
`afltatttktttattfikktkfit##3##stat:ktatt:t*tt*#:&:**&t&t*tk*k#t/
`
`EIFO_force_odd_1ength_transfer()
`(
`
`/* Disable Parts A 5: B */
`
`.
`FIFO!-)cont:o1 &= "FIFO___PORT__ENABLE.S;
`if (POR'1'_A__'.l'0_POR'I'_8(FIF0l))
`I
`1
`if (PORT__A_'1'O__RAH_Y(FIFOl))
`PIF01->ram_Y__addr = Eu-'o_1=oncz_n.u'1_1=uLL;' /* Set am Y
`
`full */
`
`)
`else FIFOI->r‘am_X_addr = FIFO__FORCE_RAM_FUI.L ;
`_
`X full */
`FI_l-‘O1->contro1 [= FIFO__PORT__B_ENA.BLE ;
`Port B *1
`
`/* Set RAM
`
`/"'~' Re-Enable
`
`/* Set
`
`/= Set RAM
`.
`
`}e
`
`~
`lse (
`I
`if (POR'1'__B_'1'0_RAM_Y(FI).-'01))
`FIF0l—>ram__Y_addr - FIFO__FORCE__RAH_FUI.L ;
`RAH Y full 3/
`
`1 e
`
`lse FIFOI-)raq_x_addr - FIFO_FORCE_RAM_FULL ;
`X full */
`
`FIFO1-)contro1 }= FIFO_PORT_A_ENABLE ;
`Port A */
`)
`
`/* Re-Enable
`
`I
`
`H
`
`/ttttttttttfitfifltttfitfiflfifitttfiakzflflfifitfiatfifltfikflfiflfifitfifififitflfifififi
`The following routine returns how many odd bytes have been
`left in the Fifo at the end of a data transter.
`fit##**#*fifit*tttk#fifittfltttfitkfik*tfl3k*kkfia#tfitfi**3fikt3¥:ttt3:]
`
`int FIF0_count_odd_pytes()
`{
`
`int numher_odd_bytes;
`number_pdd_byces=0;
`it (I-‘IP01->scatus a FIFO_DA'l'A__IN_RAH)
`i E (POR'1'_A_TO_POR'I.‘__B ( FI so 1 ) )
`(
`number_odd_bytes = (PORT_A_pYTE_ADDRESS(FIFOIJ)
`i E (POR'l.‘_A__‘1‘O__R.AH_Y ( F1 F0 1 ) )
`number_oqd_bytes += (FIF01—>ram_Y_pddr) = A ;
`
`(
`
`;
`
`Attorney Docket No.:AUSP7209
`WP1/WSW/AUSP/7209.001
`
`8/24/89-7
`
`NetApp Ex. 1002, pg. 616
`
`
`
`-130-
`
`else number_odd_bytes +- (FIFO1->ren_x_addr) * 4 ;
`
`lse {
`it (poaT_a_ro_3nM_Y(rIro1))
`number_pdd_bytes - (FIFO!-)ron;Y_nddr) * 4
`else number_odd_bytes = (FIF01~>rem_X_addr) * 6
`
`}e
`
`)
`
`eturn (numher_odd_bytes);
`
`I r
`
`:.-*.::=-r:-geese:-2.-:e::==-we-s-s-es:ktst:a--.::2-asea-:.-es:-e:='::-ea:-:.-::s:::::u::=e
`The following routine tests the microprocessor interface of
`the chip.
`It first writes and reads the first 6 registers.
`It
`then writes Is, 0s, and an address pattern to the RAM, reading the
`data back and checking it.
`
`) /
`
`The test returns a bit significant error code where each
`bit represents the address of the registers that failed.
`
`= config register failed
`Bit
`a control register failed
`Bit
`- status register failed
`Bit
`ram access control register failed,
`Bit
`ram X address register failed
`Bit
`= ran Y address register failed
`Bit
`= data register failed
`air
`Bit 7 = checksum register failed
`aeeeteaeeretaeexeeeeseassessesaeaaeaaseeaseeeeeetsea*e:s:r:/
`
`adefine RAH_DEPTH 64 -
`
`/* number of long words in Fife Ram */
`
`reg_expected_data[6] = ( 027?, OXFF, 0x00, 0x1F, 0x3F, 0x3? };
`
`char FIFo_uprocessor_interface_test()
`I
`
`unsigned long test_data;
`char *register_addr;
`int i;
`-
`char j,error;
`FIFOI->con£ig = FIFO_BESET;
`error=0;
`register_addr =(char *) FIFOI;
`j=1;
`
`/* first test registers 0 thru 5 */
`
`= reset the chip */
`
`for
`
`[
`i++)
`i<6;
`(i=0;
`/* write test data *1
`*register_addr n OxFF;
`it (=register_addr != reg_expected_data[il) error := j;
`*register_nddr - O;-
`/* write 0s to register */
`if (=register_addr) error l= j;
`
`Attorney Docket No.:AUSP7209
`HP1/WSW/AUSP/7209.001
`
`8/24/89-7
`
`NetApp Ex. 1002, pg. 617
`
`
`
`-131-
`
`/* write test data again *1
`*register_addr - 0xFF;
`if (*re3ister_addr In reg_expecced_data(i]) error 1- j;
`FIF01—>config = FIFO_RESET;
`/* reset the chip */
`it (*register;pddr) error := j; /* register should be 0 ‘I
`register_addr++;
`‘/* go to next register */
`j <<=l;
`
`/* now test Ran data & checksum registers
`test is throughout Ram & then test Os *1
`
`for (test_data = -1;
`for is G Os */
`
`test_data != 1;
`
`test_data++)
`
`.
`
`'
`
`.
`
`I-‘IFO_l6__BIT5
`F1!-‘O1->config = FII-‘O__RESET :
`FIFO!->contro1 = FIFO_PORT_A_TO_D;
`for (i=0;i<RAH_DEPTH;i++)
`FIFO1-)data = test_data;
`FIF01-)contro1 = 0;
`for (i-0;i<RAH_DEPTH;i++)
`it (FIFOI->data l= test_data) error := j;
`_
`5 check data */
`'
`if (FIFOI->checksum) error := 0x80;
`should = 0 */
`)
`
`/* write data to RAH */
`
`/* read
`
`= checksum
`
`4-.
`~ new test Ram data with address pattern
`uses a different pattern for_every byte */
`
`/* address pattern start */
`test_data=0x000l0203;
`FIFO1->config = FIFO_BES£T E FIFO_16_BITS 5 FIFO_CARRY_HRAP;
`F1 F0 1—)com: rol = F! E'0_POR'I‘_A_‘rO_B :- FI FO_CHECKSUM_ENA.BLE;
`for (i=0;i<RAH_DEPTH;i++)
`(
`‘
`FIFO1->data = test_data;
`test_data += 0x04040404;
`
`/* write address pattern */
`
`1 t
`
`* address pattern start */
`est_data=0x00010203;
`FIFO!->control = FIEO_pHEcKSUM_ENABLE;
`for (i=0;i<RAM_DEPTH;i++)
`[
`it (I-‘IP01->status l= FIFO_DA'rA__IN_RAM)
`error l= 0x04;
`/* should he data in ten */
`if (FIFO!->data != test_data) error I= j;
`/* read &
`check address pattern */
`test_data += 0x04040404;
`
`.
`]
`if (FIF01—>checksum != 0x0l02) error := 0x80;
`checksum of address pattern 3/
`FIFO1->conEig = FIF0_RESET : FIFO_l6_BIT :
`wrap */
`FIFO1->checksum = 0xFEFE;'
`
`/* test
`
`/* inhibit carry
`
`/* writing adds to checksun */
`
`Attorney Docket No.:AUSP7209
`HPI/WSW/AUSP/7209.001
`
`8/24/89-7
`
`NetApp Ex. 1002, pg. 618
`
`
`
`-132-
`
`if (FIFO!->checksum) error 5-=0x80;
`it (1-‘IF0l—>aI:aI:ua) error :- 0x04;
`return (error);
`J
`
`I" checksum should he 0 */
`/* status should be 0 */
`
`Attorney Docket No.:AUSP7209
`WP1/WSW/AUSP/7209.001
`
`8/24/89_—'I
`
`NetApp Ex. 1002, pg. 619
`
`
`
`CLAIMS
`
`095447/2
`
`1.
`
`Network server apparatus for use with a data
`
`network and a mass storage deyice, comprising:
`
`an interface processor unit coupleable to said
`
`network and to said mass storage device;
`
`a host processor unit capable of running remote
`
`procedures defined by a client node on said network;
`
`means
`in said interface processor unit
`for
`satisfying requests from said network to store data
`from said network on said mass storage device;
`
`means
`
`in said interface processor unit
`
`for
`
`satisfying requests from said network to retrieve data
`
`from said mass storage device to said network; and
`
`means
`
`in said interface processor unit
`
`for
`
`transmitting predefined categories of nessages
`
`from
`
`said network to said host processor unit for processing
`
`in said host processor unit, said transmitted messages
`
`including all
`
`requests by a network client
`
`to run '
`
`client-defined procedures
`
`on
`
`said network server
`
`apparatus.
`
`2.
`Apparatus according to claim 1, wherein said
`interface processor unit comprises:
`i
`a network control unit coupleable to said network;
`a data control unit coupleable to ‘said mass ‘
`storage device;_p
`“
`a buffer memory;
`
`Attorney Docket No. : I AUSPTZOWCF/GBR/USU
`usu/atspI7209.claims
`
`NetApp Ex. 1002, pg. 620
`
`
`
`095447/2
`
`means
`
`in
`
`said
`
`network
`
`control. unit
`
`for
`
`transmitting to said data control unit requests from
`
`said network to store specified storage data from said
`
`network on said mass storage device;
`
`means
`
`ins
`
`said
`
`network
`
`control
`
`unit
`
`for
`
`transmitting said specified storage data from said
`
`network to said buffer memory and from said buffer
`
`memory to said data.contro1 unit;
`means
`in
`said
`network
`
`control
`
`unit
`
`for"
`
`transmitting to said data control unit requests from
`
`said network to retrieve specified retrieval data from
`
`said mass storage device to said network;
`
`means
`
`in
`
`said
`
`network
`
`control
`
`unit
`
`for
`
`transmitting said specified retrieval data from said
`
`data control unit to said buffer memory and from said
`
`buffer memory to said network; and
`
`means
`
`in
`
`said
`
`network
`
`control
`
`unit
`
`for
`
`transmitting said. predefined categories of messages
`
`from said network to said host processing unit for-
`
`processing by said host processing unit.
`
`3.
`
`Apparatus according to claim 2, wherein said
`
`data control unit comprises:
`
`a storage processor unit coupleable to said mass
`
`storage device;
`
`.a file processor unit;
`
`means on said file processor unit; for translating
`
`said file system level storage requests
`
`from said
`
`Attorney Docket No.: Auswzovncr/can/usu
`usu/ausp/7209.claims
`
`-134-
`
`NetApp Ex. 1002, pg. 621
`
`
`
`095447/3
`
`network into requests
`
`to store data at
`
`specified
`
`physical storage locations in said mass storage device;.
`
`means on said file processor unit for instructing
`
`said storage processor unit
`
`to write data from said
`
`buffer memory into said specified physical storage
`
`locations in said mass storage device;
`
`means on said file processor unit for translating
`
`file system level retrieval requests from said network
`
`into requests to retrieve datarfrom specified physical
`
`retrieval locations in said mass storage device;
`
`means on said file processor unit for instructing
`
`said storage processor unit to retrieve data from said
`specified physical retrieval
`locations in said mass
`
`storage device to said buffer memory if said data from
`
`said specified physical
`
`locations is not already in
`
`said buffer memory; and
`
`means
`
`in
`
`said .storage
`
`processor unit
`
`for
`
`transmitting data between said buffer memory and said
`
`mass storage device.
`
`4,
`
`-Network server apparatus for use with a data
`
`network and a mass storage device, comprising:
`
`a network control unit coupleable to said network;
`
`a data ‘control unit
`
`coupleable to said mass
`
`storage device;
`
`a buffer memory;
`
`means for transmitting from said network control
`
`unit
`
`to said data control unit
`
`requests from said
`
`Attorney Docket Ilo.: AUSP7209llcF/GBRIHSV
`wsuIauspI72D9.claim
`
`-135-
`
`NetApp Ex. 1002, pg. 622
`
`
`
`095447/2
`
`network to. store specified storage data from said
`
`network on said mass storage device;
`
`means for transmitting said specified storage data
`
`by DMA from said network control unit
`
`to said buffer
`
`memory and by DMA from said buffer memory to said data
`
`control unit;
`
`means for transmitting from said network control
`
`unit
`
`to said data control unit
`
`requests front said
`
`network to retrieve specified retrieval data from said
`
`mass storage device to said network; and
`
`means
`
`for transmitting said specified retrieval
`
`data by DMA from said data control unit to said buffer
`
`nemory and by DMA from said buffer memory to said
`
`network control unit.
`
`.
`
`5.
`
`Apparatus according to claim 1,
`
`for use
`
`further with a buffer memory, and wherein said requests
`
`from said network to store and retrieve data include
`
`file system level
`
`storage and retrieval
`
`requests
`
`respectively, and wherein said interface processor unit
`
`comprises:
`
`a storage processor unit coupleable to said mass
`
`storage device;
`
`a file processor unit;
`means on said file processor unit for translating
`
`said file system level storage requests into requests
`to store data at specified physical storage locations
`
`in said mass storage device;
`
`-136-
`
`Attorney Docket Ilo.: AU$P7209|lCF/GER/USU
`USU/ausplTZ0?.claims
`
`NetApp Ex. 1002, pg. 623
`
`
`
`095447/4
`
`means on said file processor unit for instructing
`
`said storage processor unit
`
`to write data from said.
`
`buffer memory into said specified physical storage
`
`locations in said mass storage device;
`
`means on said file processor unit for translating
`
`said file system level retrievatilerequests into requests
`
`to retrieve data from specified physical
`
`retrievab1e
`
`locations in said mass storage ‘device;
`
`means on said file processor unit for instructing
`
`said storage processor unit to retrieve data from said
`
`specified physical
`
`retrievablelocations in said mass
`
`storage device to said buffer memory if said data from
`
`said specified physical
`
`locations is not already in
`
`said buffer memory; and
`
`means
`
`in
`
`said
`
`storage
`
`processor
`
`unit
`
`for
`
`transmitting data between said buffer memory and said
`
`mass storage device .
`
`NetApp Ex. 1002, pg. 624
`
`
`
`095447/_2> '
`Networkserver apparatus for use with a data
`
`I
`
`6.
`
`network, comprising:
`
`a network controller coupleable to said network to
`
`receive incoming information packets over said network.
`
`said incoming information packets ‘. including certain
`
`packets which contain part or all of a request to Said
`server apparatus, said request being in either a first
`
`or a second class of requests to said server apparatus;
`
`a first additional processor,-
`
`an interchange bus different from said network
`
`coupled between said network controller and said first
`
`additional processor;
`
`means in said network controller for detecting and
`
`satisfying requests in said first‘ class of
`
`requests
`
`contained in said certain incoming information packets,
`
`said network controller lacking means in said network
`
`controller for satisfying requests in said second class
`
`of requests;
`
`means in said network controller for detecting and
`
`