ARM250 Data Sheet
`
`ARM250 - Integrated Controller
`
`The ARM250 is a complete computer system on a chip - comprising a 32-bit RISC processor, a memory
`controller with DRAM interface, a bit-mapped video controller and an I/0 controller. It is suitable for a
`wide range of cost-sensitive embedded control, portable and consumer games applications - particularly
`(but not only) those which require a video display.
`
`The device is designed to drive up to 4 Mbytes of DRAM directly at 12 MHz, and at these speeds can sustain
`about 10 MIPS (peak).
`
`~~~">.~">."«~
`
`ARMRISC
`Processor
`
`Memory
`Controller
`
`,.
`
`..... ·."5-........... • ... ~N.":i-, "'
`
`,,
`
`l/0
`Controller
`
`Peripheral
`Controller
`
`Video
`Controller
`
`Ci ARM 32 bit RISC core
`
`Ci Memory Controller
`
`Ci Video Controller
`Ci F1exible 1/0 ControHer
`Ci Reduced system cost
`a 10 MIPS (peak)@ 12 MHz
`Ci
`Small footprint 160 PQFP package
`Ci Low power consumption
`
`Example- Video games console
`
`ARM
`250
`
`Applications
`
`• Portable Computers
`
`• Desktop Computers
`
`• Games Consoles
`
`• Palmtop Computers
`
`• Low cost X terminals
`
`-J Order !his document r--------- ARM
`
`Advanced RISC Mlclllnes
`
`- - - -
`
`I
`
`ARMOOIOO:JOA
`
`.
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`SCEA Ex. 1054 Page 1
`
`

`
`Overview
`
`Otange Log
`
`Issue
`
`Dale
`
`By
`
`Otange
`
`A
`
`11 Aug92 Sf/PM
`
`Transferred to Frame DTP
`
`@Copyright Advanced RISC Machines (ARM) Ltd, 1992. All rights reserved
`
`Netlher lhe whole nor any pout ol the Wormatlon contained ln. or the p-oduct desaibecl Ln. this IJW\Ual may be adapted oc nproduced In any materW
`form except wilh lhe pnor written pennission of lhe oopynght holder.
`
`The product described in this manual is subjl!d to continuous developments and improvements. All partlcu1us of lhe product and its use contained in
`llus datasheet ·~ g.ven by ARM 111 good fallh. However, all wammties implied or expressed, tndudmg but not limited to implied warnnties or
`mer<:hanto~blllty, or fitness for purpose.~ excluded
`
`"1'ha datlll>hect IS mtmded only to assist lhe reader In lhe use of the product. ARM Ltd shall not be llable lor any loss or damage arising from lhe u'l4! of
`any lnfonnatlon In thiS datashect, or any error or omission In such Wonnation, or any incorrect use of lhe product.
`
`Doc No : ARM 0[)( 0030A
`Issued : Aug 1992
`
`2
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`SCEA Ex. 1054 Page 2
`
`

`
`ARM250 Data Sheet
`
`1. Overview
`The ARM250 is a highly integrated microcontroller based on a 32 bit RISC processor. In addition to the cen(cid:173)
`tral processor the ARM250 includes :
`a Memory Controller with direct interface to DRAM and ROM and support for memory mapping and pro(cid:173)
`tection.
`a Vuleo controller for bit-mapped display with integral palette. On-chip video and sound DACs allow inter(cid:173)
`facing to video monitors with minimal external circuitry ..
`an I/0 controller interfaces to a wide range of standard peripheral chips. Provides timers, serial port, parallel
`port and a range of interrupt and configuration inputs.
`·
`The 1/0 subsystem contains some on-chip functions such as timers, and in addition can directly drive
`industry standard peripheral chips. The video subsystem is capable of a wide variety of display modes up
`to Super VGA resolutions (600 X 800 pixels), as well as adding impressive sound capability
`The device is based on 4 standard chips from the ARM RISC chip set- ARM2aS, MEMCla, VIDC and IOC.
`In order to reduce the size of this datasheet, the datasheets for these parts are not duplicated here as they
`retain identical functionality (but with improved performance) within ARM250. The relevant datasheets,
`available on request from Advanced RISC Machines Ltd, are as follows :
`
`• ARM2aS Datasheet
`• MEMCla Datasheet
`• VIDC Datashcet
`• IOC Da tasheet
`
`The main blocks in ARM250 are the processor (ARM2aS), memory controller (MEMO, video controller
`(VIDO, input/output controller (TOC) and l/0 extension block (lOEB). The first four of these blocks are
`based on standard chips {rom the ARM RlSC chip set. Some extra logic, known as lOEB, is used in the 1/0
`system and is documented in this datasheet.
`A simplified block diagram appears in Figure 1. A list of relevant documentation is given later in this
`datashcet and a detailed block diagram of ARM250 appears at the end of this chapter.
`
`1.1 Processor
`The processor (ARM2aS) is an implementation of the Advanced RlSC Machines' ARM processor which is a
`general purpose 32-bit single-chip microprocessor. The architecture is based on Reduced Instruction Set
`Computer (RISC) principles and provides a high instruction throughput and an excellent real-time inter(cid:173)
`rupt response from a small silicon area.
`
`Pipelining is employed so that all parts of the processing and memory systems can operate continuously.
`Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is
`being fetched from memory.
`The ARM instruction set has proved to be a good target for compilers of high-levellanguages. Where
`required for critical code segments, assembly code programming is also straightforward, unlike some RISC
`processors which depend on sophisticated compiler technology to manage complicated instruction inter-
`
`3
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`SCEA Ex. 1054 Page 3
`
`

`
`Overview
`
`- ··
`
`.... (101
`
`-
`
`AAM2aS
`
`32 bit ARM processor
`
`MEMC
`
`Memoty Controllw
`
`OIIAM-{tOI
`
`~· ~~~~~~~~~miili[lliillEI~~
`llw(Sl) ~
`a-n
`~
`
`IOC
`
`Input/Output Controller
`
`VI DC
`
`Video Controllw
`
`- jq
`
`"-v.,...
`"'_.,....
`.....
`
`P.U..,_
`
`W> o. ........ ,
`
`Fig 1 :Simplified Block Diagram
`
`dependencies.
`ARM Ltd provides a complete cross development toolkit for the ARM, consisting of the tools and documen(cid:173)
`tation needed to develop software for ARM-based systems, including simulation and debug tools which
`allow ARM targeted software to be debugged and evaluated in more familar, fully hosted, software devel(cid:173)
`opment environments.
`
`1.2 Memory Controller
`The memory controller (MEMC> acts as the interface between the ARM processor, the video controller, the
`1/0 controller, read-only memories and dynamic memory devices, providing all the critical system timing
`signals and partitioning the memory map.
`ARM250 is designed principally for use with two types of memory- read-only memory (ROM) and
`dynamic RAM (DRAM). In both cases, a 32 bit data bus is used to transfer memory data. A 20 bit address
`bus is used to supply addresses for ROMs and for 1/0 port memory mapping. Internally, a 26 bit address
`bus is used but only 20 bits are brought out to pins. To interface to up to 4 megabytes of DRAM, ARM250
`provides multiplexed addresses and row and column strobes which drive the DRAM chips directly.
`The memory controller also contains a Logical to Physical Address Translator which maps the physical
`memory into a 32MByte logical add ress space (with three levels of protection) allowing virtual memory and
`multi-tasking operations to be implemented. Fast "page-mode" DRAM accesses are used to maximise mem(cid:173)
`ory bandwidth.
`
`4
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`SCEA Ex. 1054 Page 4
`
`

`
`ARM250 Data Sheet
`
`The memory controller provides a Direct Memory Access (DMA) system for the video controller. It contains
`pointer registers to 3 separate RAM buffers which it automatically transfers to the video controller when
`required.
`
`1.3 Video Controller
`The video controller (VIDC) uses buffers in RAM to generate a video display with a hardware cursor and
`stereo sound. The memory controller is responsible for coordinating transfers from these buffers to the
`video controller by DMA. The video controller requests data from the memory when required, and holds it
`in one of three internal buffers before using it. Data from the internal buffers is serialised and then presented
`to a digital to analogue converter (DAC). There are DACs for both sound and video, allowing driving of
`video monitors and audio systems with minimal external buffering. The video data also passes through a
`colour look-up palette before being output.
`Three forms of video synchronisation pulses are generated with programmable timing and polarity. The
`video dock may be selected from a variety of sources and appears on pins to allow the video to be ''gen(cid:173)
`Jocked" to an external signal.
`DMA transfers move video, cursor and sound data in blocks of four 32-bit words, aJiowing efficient use of
`page-mode DRAM without locking up the system data bus for long periods. The vid<;<> controller is pro(cid:173)
`grammable, offering a very wide choice of display formats. The pixel rate can be selected from a range of
`sources and pTOgrammable prescaling applied. Video data can be serialised to either 8,4, 2, or 1 bit per pixel.
`The horizontal timing parameters can be controlled to units of 2 pixels, and the vertical timing parameters
`can be controlled to units of a raster. The colour look-up palette which drives the three on-chip video DACs
`is 13 bits wide, offering a choice of 4096 colours or an external video source.
`The hardware cursor is 32 pixels wide and may be any number of rasters high. It can be positioned any(cid:173)
`where on the screen. Three simultaneous colours (again from a choice of 4096) are supported, and any pixel
`can be defined as transparent, making it possible to define cursors of many shapes.
`The sound system incorporates an exponential DAC and stereo image table for the generation of high qual(cid:173)
`ity sound. Up to 8 channels arc supported, each with a separate stereo position.
`
`1.4 1/0 Controller
`The 1/0 controller is based on a chip known as IOC together with some additional logic, known as lOEB,
`which is used to provide additional functionality. The 1/0 system is based around an 8 bit [/0 bus which
`connected to the main data bus by latches which allow the memory and l/0 systems to operate asynchro(cid:173)
`nously. This bus can be upgraded to 16 bits with the addition of two external latches.
`
`The J /0 controJler contains three 16 bit timers which are clocked at 2 MHz. Two of the timers are general
`purpose and may be used to provide timed interrupts. The third provides the dock for the serial interface
`which provides a UART-Iike interface for asynchronous serial data at baud rates up to 31250.
`The memory controller defines part of the memory map as containing memory mapped f/0 devices and
`the 1/0 controller controls accesses made in this area of memory. It provides four different cycle times for
`use with peripheral devices of varying speeds. The 1/0 part of the memory map is further divided by
`address decoding to prov•de a number of pins which are active in various parts of the 1/0 space. One of
`these areas is designed for interfacing directly to one of the highly integrated PC combination chips which
`provides interfaces to hard and Ooppy discs, parallel printer port, etc. It is also possible to bypass the J/0
`controller for certain I /0 accesses so that the cycle timing is determined by external logic.
`
`5
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`·I
`
`SCEA Ex. 1054 Page 5
`
`

`
`Overview
`
`The l/0 controller also coordinates interrupts for the whole system. There are a number of external inter(cid:173)
`rupt pins, both edge and level triggered, and internal interrupts from the memory and video controllers,
`timers and serial interface. These interrupts can be selectively masked in the I /0 controller and are routed
`to one of two interrupt inputs on the processor. These two interrupts differ only in priority; one is meant for
`use in low latency situations, the other where interrupt latency is less critica1. There are also a number of
`pins which form 1/0 ports, readable and I or wri teablc by the processor. These may be used to read external
`status and control external logic.
`
`1.5 System Clocks
`There are a number of clocking options for ARM250. The basic clock is a 72 MHz input which is internally
`divided down to 24 and 36 MHz. These form two of the three possible video clock frequencies. The chip
`also has a pair of pins which form an oscillator with an external crystal in the range 1 to 26 MHz (typically
`25.175 MHz) which is used to form the third video dock source. The 24 MHz signal is further divided to
`generate 12 and 8 MHz signals. These are both available on output pins and the 8MHz signal also forms the
`clock for the 1/0 system. The 36 MHz signal is divided by three in the memory controller to make a 12 MHz
`clock for the processor and memory system.
`It is possible to bypass the 36 MHz signal to the memory controller and drive the processor and memory
`system with an external clock at a higher speed. For example, a 48 MHz clock would result in the processor
`being clocked at 16 MHz. This would result in a system capable of over 7 MIPS using standard DRAMs.
`The video clocks of 24, 25 and 36 MHz provide for industry standard video displays up to SVGA resolution.
`
`6
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`SCEA Ex. 1054 Page 6
`
`

`
`.,._
`OJ
`OJ
`...c:
`C/}
`J9
`fU
`0
`0
`ll'l
`
`~ <
`
`d(3UI)
`
`le(21:2] I
`
`pmw
`
`.. ,.,
`
`Npo~
`
`c(3~)
`Hllnll'
`
`Hll(3)
`Nllnll'
`Nplrq
`Npllq
`Ninde
`drq
`N.tlq
`
`..
`
`dbe
`
`Nromc. Nraa Ncaa($~) ,.(i :O)
`
`dkvld
`
`:~ ~ "'-'' HCAI(~:oJ IUif:O)
`
`110
`AtOIIT
`V'AoD
`~'W MEMC
`111/W
`IAI~IO
`uo
`A( IS :OJ
`
`iiSitOAJ(
`IMOAJ(
`IMCW
`nnx
`IMOIIO
`NSNDIIO
`~*~SYNC
`
`QQII
`RUC:U
`ltO!IO
`~
`NOOT
`NIIIIO ~
`
`·.
`
`-~••II
`
`. t c(J:oJ
`
`j+ 4 R .. d ~
`l
`
`Bultw
`
`_, Wrile
`Bull•
`
`1
`
`011
`IICUI
`AIOIIT
`m
`
`ARM2aS -
`
`111/W
`IIMR50
`uo
`A(ZS~
`
`.
`
`OOUllst;Of
`I:IINIUO) IIIID€1
`
`Nl~O 1¥10
`
`I Addreaa Laid! } - - -
`
`'"'
`
`l i
`
`111'011 NIIST NIL(I) 111110
`
`IWIO
`1111/W
`CS.I(U~'Ill:oj.AIU)
`Q(UI)
`
`C(llO)
`
`L; C!•l
`
`ldL(t)
`llli.P)
`-~1
`Hill$)
`1111.10)
`
`""
`
`FMIOI
`NFL
`
`lltL
`NL(II
`1131,1
`liEF PI
`NIDRO
`NIOOT
`IIWIE
`
`IIWE
`NAI r--
`NS(I) f-
`
`Na[2) Nra ...... Nwbe bd{7:0)1oclk Hwbl
`
`Nlorq Nlogt Nrbl
`
`Hti)e
`
`IOC
`
`CUC2 U l KOUT
`
`1
`
`clk2 kin kout
`
`r-.
`
`ondvu
`andvdd
`alnk Ndoc ~•c vlchu
`
`I
`•
`
`liNK ~VO/oO RIOAC VIS¥ VSSt VOOt
`
`VIDC
`
`NWIOAK
`IMDAK
`IMCW
`fLYIX
`IMDIIO
`NSHDRO
`
`~YNC
`r-- IIV/CSYNC
`QQII
`
`!pi :OJ
`
`Hill
`
`u:tl·
`l.QI.
`IIQi.
`
`IIQH.
`
`ROUT
`COUT
`lOUT
`
`HSU'
`
`Nlch
`lch
`Ntch
`rch
`
`rout
`gout
`bout
`
`Naup
`
`CSYNC _.
`--+ GEN
`
`ceync
`
`CI.OCK ~
`c:ll<72
`GEN ~
`ay.clk
`
`osc
`
`c:lk251n
`c:lk25oul
`
`1
`
`litw Nul •I'll odil• tdiU mlcl(l:O -
`-
`
`llll .lf.ll.&l
`
`Htlll
`d(7l0)
`
`lOEB
`
`lpln•
`lit{, I
`
`....
`
`lh<q
`NIOQI
`
`.. lalt
`Hfto<q
`
`~·
`L....-.,.
`IN sync
`~ Nhtyn<:
`llwlll
`
`mld[3:0)
`plnCJ
`pint ~
`""'' Hjlyl
`Npel
`Njoyl
`Njoy2
`....
`-
`"'
`.....
`
`Nf•r•
`
`ooth
`
`lodia<k
`
`IIIII
`
`.orh
`eorv
`
`tc
`Ndoek
`NMn
`Nlor
`Nlow
`
`cO.kb
`vld<lll
`
`clklcb
`vldclk
`
`-
`
`-
`
`-
`
`- - - - - - - - -
`
`- ~4 - - -
`
`~-- - ....
`
`SCEA Ex. 1054 Page 7
`
`

`
`Pin Descriptions
`
`2. Pin Descriptions
`ARM250 has a mixture of analogue and digital inputs and outputs. The analogue inputs (lA) and outputs
`(OA) are associated with DACs in VIDC and a full description of their use and characteristics is provided
`in the VIDC data sheet.
`All digital outputs are CMOS drivers and all digital inputs have either CMOS (I C), 1TL <m or Schmitt (IS)
`input thresholds depending on their intended use. The output drivers have a range of current driving capa(cid:173)
`bilities. The weakest drivers can source or sink 4mA (04), the majority of outputs have 8mA capability (08)
`and two outputs can provide 16mA (016). Some of the 8mAdrivers are slew-limited (058) to reduce instan(cid:173)
`taneous current requirements when many outputs are changing. Some outputs are open-drain (004,008),
`that is they only ever sink current.
`
`Name I Type I
`
`Description
`
`Nre
`
`kin
`
`kout
`
`clk72
`
`08
`
`IC
`
`04
`
`IC
`
`Ntest
`
`IC
`
`110 Read Enable.An active low output strobe which is used to control periph(cid:173)
`eral read accesses. It is driven by the IOC output NRE
`
`Keyboard In. Serial input to the IOC keyboard input (KIN).
`
`Keyboard Out. Serial output from the IOC keyboard output (KOUD.
`
`Clock 72MHz. This input provides the main clock for ARM250. It should be a
`7l MHz square wave of 50% duty cycle(+/- 5%). It is divided down internally
`to 24 and 36 MHz and these frequencies are used in various parts of the device.
`
`Test A test input which should be high for normal operation. This pin has an
`internal pull-up resistor and so may be left unconnected. Driving this input low
`will put the chip into a test mode and this should not be done while the device
`is in use.
`
`Nrst
`
`IS/008 Reset. This bidirectional pin may be driven low as an input to reset ARM250.1t
`is internally connected to the reset inputs of ARM2aS, MEMC, IOC and lOEB.
`The output is driven low whenever the power-on reset pin (Npor) is low and
`the pin wi11 normally have an external pull-up resistor fitted.
`
`Npor
`
`sysclk
`
`IS
`
`IC
`
`Power-on Reset. This active low input causes the Nrst pin to go low and so
`reset ARM250. It is also connected to the NPOR input of IOC.
`
`System Clock. This input is optionally used to drive the MEMC dock input
`(CKIN). If the pin is held permanently high, the MEMC clock is derived from
`the internal 36 MHz source. If a square wave is applied to the pin with a fre(cid:173)
`quency greater than 4 MHz (ie dk72 divided by 18) then this signal is used as
`the MEMC dock. It is anticipated that the frequency used will be greater than
`36 MHz to make the processor and memory run faster than they would other(cid:173)
`wise. This pin has an internal pull-up resistor and can be left unconnected if
`desired.
`
`8
`
`·.
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`I
`I
`I
`
`SCEA Ex. 1054 Page 8
`
`

`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`'I
`I
`
`ARM250 Data Sheet
`
`~ame I Type I
`
`Description
`
`clk25out
`
`04
`
`clk25in
`
`JC
`
`Clock25 Out. This pin forms one of a pair (with dk25in) which fonn the basis
`of a crystal oscillator circuit. A resistor, two capacitors and a crystaJ are required
`to complete the circuit which will operate in the range 1 to 26 MHz.
`
`Clock25In. This pin forms an osciJlator circuit with clk2Soul If the oscillator
`function is not required, it may be driven by an external CMOS level signal.
`Internally, it is connected to the video dock selector circuit in lOEB.
`
`mid ( 3 : 0 J
`
`IS
`
`Configuration Inputs. These four pins provide four status inputs which may be
`read by the ARM processor. They are connected to a register in lOEB.
`
`clkkb
`
`eorh
`
`eorv
`
`04
`
`016
`
`016
`
`Njoy ( 1]
`
`04
`
`Keyboard Clock. This output is a 12 MHz square wave (ie clk72 divided by 6).
`
`Horizontal Sync. This signal is the horizontal sync output of V1DC (NHSYNQ
`which has been passed through a programmable inversion in lOEB.
`
`Vertical/Combined Sync. This signal is the vertical/ combined sync output of
`VIOC (NV /CSYNC) which has been passed through a programmable inversion
`in lOEB.
`
`Joystick enable 1. This active low signal is an address decode (in the 1/0
`address space) p roduced by lOEB. It decodes an area which is effectively a sin(cid:173)
`gle word. See the section on lOEB address decoding for more details.
`
`Njoy [2]
`
`04
`
`Joystick enable 2. Similar to Njoy[l] but decodes a different address.
`
`Nras
`
`058
`
`Row Address Strobe. This is the NRAS signal from MEMC. It is used to clock a
`row address into DRAM devices.
`
`Ncas [3: 0) 058
`
`Column Address Strobes. These four signals are the NCAS{3:0} outputs of
`MEMC They are used to clock a column address into DRAM devices.
`
`058
`
`ra [ 9: 0 J
`
`RAM Addresses. These ten signals are the RA[9:0) outputs of MEMC They pro(cid:173)
`vide the row and column addresses for DRAM devices.
`~--------1-------4-----
`04
`d.be
`Data Bus Enable. This output is active high while the ARM processor is driving
`the external data bus. It is the MEMC DBE signal and may be used with an exter(cid:173)
`nal inverter to provide the (active low) write enable signal for DRAM devices.
`
`d [ 31: 0 J
`
`IT /058 Data Bus. These 32 bidirectional pins form the main data bus. They are active
`while the ARM is performing memory and 1/0 accesses and when DMA oper(cid:173)
`ations are in progress to move data from external RAM to VIDC.
`
`Nromcs
`
`04
`
`ROM Select This active low output is the MEMC NROMCS signal. It is low
`while the processor is accessing that part of the memory map which is allocated
`to ROM.
`
`9
`
`SCEA Ex. 1054 Page 9
`
`

`
`Pin Descriptions
`
`Name I Type I
`
`Description
`
`prnw
`
`058
`
`la[21:2]
`
`OS8
`
`pintr
`
`IT
`
`Naen
`
`04
`
`Nior
`
`04
`
`Niow
`
`Ndack
`
`04
`
`tc
`
`04
`
`Read/not Write. This output is the ARM2aS NR/W signal which has been
`latched and inverted. It is intended as a read/write signal for peripheral devices
`and a high level indicates a read cycle.
`
`Latched Addresses. These outputs are a subset of the ARM2aS address lines
`which have been latched by the PHI output of MEMC. They are valid through(cid:173)
`out each memory access and a re intended for use with ROM memories, 1/0
`devices and external address decoding.
`
`Printer Interrupt. This level sensitive input is used to generate an intenupt
`input to IOC when a rising edge is applied. See the section on lOEB for more
`details.
`PC Address Enable. This active low output is generated by lOEB when a PC I/
`0 access is performed in a certain address range. See the section on lOEB for
`more details.
`
`PC IJO Read. This active low output is generated by lOEB when a P€ l/0 read
`access is performed in a certain address range. See the section on lOEB for more
`details.
`
`PC 110 Write. This active low output is generated by lOEB when a PC 1/0 write
`access is performed in a certain address range. See the section on lOEB for more
`details.
`
`PC Data Acknowledge. This active low output is generated by lOEB when a PC
`I/0 access is performed in a certain address range. See the section on lOEB for
`more details.
`PC Terminal Count. This active high output is generated by IOEB when a PC I/
`0 access is performed in a certain address range. See the section on lOEB for
`more details.
`
`rsdac
`
`IA
`
`Sound DAC Reference Current. This input is a reference current input for the
`VIDC sound DAC. It is connected to the YIDC RSDAC input.
`
`sndvss
`
`sndvdd
`
`lch
`
`Nlch
`
`p
`
`p
`
`OA
`
`OA
`
`Sound VSS. This pin is the g round supply to the sound DAC in VIDC (VIDC
`pin VSSs). It must be externally connected to YSS.
`
`Sound VDD. This pin is the power supply for the sound DAC in VIDC (VIDC
`pin VDDs). It must be at the same potential as VDD and decoupled to sndvss.
`
`Left Channel Sound. This is one of a pair of outputs (with Nlch) forming the
`left channel sound output from VTDC (VIDC output LCH+).
`
`Inverse Left Channel Sound. This is one of a pair of outputs (with lch) forming
`the left channel sound output from VIDC (VIDC output LCH-).
`
`10
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`SCEA Ex. 1054 Page 10
`
`

`
`I
`I
`I
`I
`I
`I
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`ARM250 Data Sheet
`
`Name I Type I
`
`Description
`
`rch
`
`Nrch
`
`rvdac
`
`vidvss
`
`rout
`
`gout
`
`bout
`
`sink
`
`Nsup
`
`vidcclk
`
`OA
`
`OA
`
`lA
`
`p
`
`OA
`
`OA
`
`OA
`
`IT.
`
`04
`
`04
`
`clkvid
`
`IC
`
`Right Channel Sound. This is one of a pair of outputs (with Nrch) forming the
`right channel sound output from VIDC (VTDC output RCH+).
`
`Inverse Right Channel Sound. This is one of a pair of outputs (with rch) form(cid:173)
`ing the right channel sound output from VIDC (VIDC output RCH-).
`
`Video Reference Current. This input is a reference current input for the VIDC
`video DAC. It is connected to the VIDC RVDAC input.
`
`Video VSS. This pin is the ground supply to the video DAC in VIDC (VIDC pin
`VSSv). It must be externally connected to VSS.
`
`Red Video. This is the red output from the VIDC video DACs (VIDC output
`ROUT).
`
`Green Video. This is the green output from the VIDC video DACs (VIDC out(cid:173)
`put GOUT).
`Blue Video. This is the blue output from the vroc video DACs (VIDC output
`BOUT).
`
`Sink. Active high input to the VIDC external synchronisation input (SINK).
`
`Supremacy Bit. Active low output from the VIDC supremacy output (NSUP)
`
`Video Cloclc Out. This output comes from the video clock selector in lOEB. In
`most applications it wilt be connected directly to dkvid (pin 124).
`
`Video Clock ln. This input drives the VTDC clock input (CKIN). Note that this
`input has CMOS thresholds whereas the corresponding input on VJDC has TTL
`thresholds.
`
`csync
`
`04
`
`Compensated Sync. This output is a modified form of the vertical/combined
`sync output of VlDC. It is described in detail later in this datasheet.
`
`Nindex
`
`drq
`
`Npirq
`
`Npfiq
`
`IT
`
`IT
`
`IT
`
`IT
`
`IF Interrupt. This (falling) edge sensitive interrupt input is connected to an IOC
`interrupt input (NIF). It generates a slow interrupt (IRQ) when active.
`
`FHO Interrupt. This active high interrupt input is connected to an IOC interrupt
`input (FH[O)). It generates a fast interrupt (FIQ) when active.
`
`rLS Interrupt. This active low interrupt input is connected to an IOC interrupt
`input (NIL[S]). It generates a slow interrupt (IRQ) when active.
`
`ILO Interrupt. This active low interrupt input is connected to an IOC interrupt
`input (NIL[O)). It can be programmed to generate a slow interrupt (IRQ) and/ or
`a fast interrupt (FIQ) when active.
`
`Nfintr
`
`IT
`
`IL4 Interrupt. This active low interrupt input is connected to an IOC interrupt
`input (NIL[4]). It generates a slow interrupt (TRQ) when active.
`
`11
`
`SCEA Ex. 1054 Page 11
`
`

`
`Pin Descriptions
`
`Name I Type I
`
`Description
`
`Nsintr
`
`IT /004
`
`IT
`
`08
`
`08
`
`IT/
`ODS
`
`08
`
`IT
`
`08
`
`08
`
`bd[7:0]
`
`IT/08
`
`Nefiq
`
`clk2
`
`c[3:0]
`
`Niorq
`
`Niogt
`
`Npsl
`
`Nil [3]
`
`Ns(2)
`
`ioclk
`
`Nwbe
`
`Nrbe
`
`Nwbl
`
`12
`
`IT/004
`
`JJO Port. These bidirectional pins behave like the IOC pins C[3:0].
`
`IL2/C4lnterrupt. The input side of this pin is connected to both the C(4] control
`register input and the NIU2l interrupt input of IOC It may be used to generate
`slow and/or fast interrupts. The output side is controlled by the C(4] bit in the
`IOC control register.
`
`FL interrupt This active low interrupt input is connected to an IOC interrupt
`input (NFL). It generates a fast interrupt (FIQ) when active.
`
`Peripheral Clock. This output is a 2MHz square wave generated by IOC (CLK2
`output) which divides the 1/0 clock by 4.
`
`I/0 Request This active low output indicates that an 1/0 access is requested. It
`is generated by lOEB and derived from the NIORQ output of MEMC
`I/0 Grant As an input, this bidirectional pin is driven low to indicate that an II
`0 device has finished an access cycle which was started by the Niorq signal. It
`drives an input to lOEB which passes a modified form back to the MEMC
`NIOGT input. As an output, it is driven low when the IOC NIOGT output is low.
`
`Peripheral Select 1. This active low output is an address decode generated by
`lOEB. It is decribed in detail later.
`
`IL3 Interrupt This active low interrupt input is connected to an IOC interrupt
`input (NIU3]). It generates a slow interrupt (IRQ) when active.
`
`Peripheral Select 2. This active low output is an address decode generated by
`IOC (NS[2J output).
`
`I/0 Clock. This output is an 8MHz square wave generated by lOEB. It is the ref(cid:173)
`erence clock for the 1/0 system and is derived from the clk72 input by dividing
`by9.
`
`l /0 Data Bus. These bidirectional pins form the 1/0 data bus. lntemally, they
`are connected to lOEB and IOC and also to the main ARM data bus via latches.
`The 1/0 system is described in more detail later.
`
`Write Buffer Enable. This output comes from the IOC NWBE output. It is used
`to enable an optional extemallatch which expands the 1/0 bus from 8 to 16 bits.
`
`04
`
`Read Buffer Enable. This output comes from lOEB. It is used to enable an
`optional external Latch which expands the £/0 bus from 8 to 16 bits.
`
`Write Buffer Latch. This output comes from IOEB. It is used to control an
`optional external latch which expands the 1/0 bus from 8 to 16 bits.
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`SCEA Ex. 1054 Page 12
`
`

`
`ARM250 Data Sheet
`
`Name I Type I
`
`Description
`
`Nrbl
`
`IT /008 Read Buffer Latch. The active low output of this bidirectional pin is controlled
`by lOEB and IOC. The input controls the internal read latch on the I/0 data bus.
`Its function is described in more detail later.
`
`Nwe
`
`08
`
`1/0 Write Enable. An active low output strobe which is used to time peripheral
`write accesses. It is driven by the IOC output NWE.
`
`The following pins provide power to the device. Note that there are also specialised power pins for the ana(cid:173)
`logue circuitry which are individually listed above.
`
`vss -9, 18, 28, 49, 67, 89, 107, 126, 146
`VDD - 10, 29, 50, 68, 90, 108,127, 147
`
`13
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`·'
`
`SCEA Ex. 1054 Page 13
`
`

`
`Block Level Wiring
`
`3. Block Level Wiring
`This section describes the way in which the main blocks of ARM250 are wired. It should be read with ref(cid:173)
`erence to the block level diagram shown earlier in this document and the appropriate data sheets.
`
`3.1 IOC wiring
`
`Signal I
`
`Connects
`
`I
`
`Comment
`
`REF8M
`
`IOEB/ioclk, ioclk pin
`
`Main 1/0 clock input
`
`CLK8
`
`CLK2
`
`NBL
`
`<none>
`
`clk2 pin
`
`Nrbl pin
`
`0[7:0)
`
`I/O data bus
`
`NIORQ
`
`NIOGT
`
`IOEB/Niorq
`
`Niogt pin
`
`not used
`
`Peripheral timing clock (2 MHz)
`
`Read buffer latch output
`
`I/O data bus
`
`1/0 request input
`
`I/0 grant output
`
`T(l:O]
`
`Addr latch (1a[20:19])
`
`Cycle type select inputs
`
`NR/W
`
`NSEXT
`
`Addr latch
`
`<none>
`
`NS[7:6]
`
`<none>
`
`NS[S)
`
`IOEB/Ns[S]
`
`NS(4:3]
`
`<none>
`
`NS[2]
`
`NS [ 1]
`
`8[2:0]
`cs
`A[ 6 :2]
`
`NRBE
`
`NWBE
`
`NRE
`
`NWE
`
`Ns[2] pin
`
`<none>
`
`Addr latch (la[18:16])
`
`Addr latch (Ja[21J)
`
`Addr latch (laf6:2J)
`
`<none>
`
`Nwbepin
`
`Nre pin
`
`Nwe pin
`
`14
`
`Read/write input (latched ARM/NR/W)
`
`not used
`
`not used
`
`Peripheral select output (bank 5)
`
`not used
`
`Peripheral select output (bank 2)
`
`not used
`
`Bank select inputs
`
`Chip select input
`
`Register select inputs
`
`not used
`
`Write buffer enable output
`
`Read enable output
`
`Write enable output
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`SCEA Ex. 1054 Page 14
`
`

`
`ARM250 Data Sheet
`
`Connects
`
`I
`
`Comment
`
`Signal I
`
`NRST
`
`NPOR
`
`Nrst pin
`
`Nporpin
`
`NIL(7)
`
`tied HIGH
`
`NIL ( 6)
`
`IOEB/Ipintr
`
`NIL(5)
`
`Npirq pin
`
`NIL(4]
`
`Nfintr pin
`
`NIL£3]
`
`Nil3 pin
`
`NIL(2)
`
`Nsintr pin
`
`NIF
`
`IR
`
`FH(l)
`
`FH(O)
`
`C(S)
`c [ 4)
`
`tied LOW
`
`drq pin
`
`input tied LOW
`
`Nsintrpin
`
`C[3:0)
`
`c(3:0) pins
`
`NIRQ
`
`NFIQ
`
`BAUD
`
`KIN
`
`KOUT
`
`ARM/NIRQ
`
`ARM/NFIQ
`
`<none>
`
`kin pin
`
`kout pin
`
`NIL(l)
`
`MEMC/NSlRQ
`
`NIL(O)
`
`Npfiqpin
`
`Nindex pin
`
`MEMC/FLYBK, VIOC/FLYBK
`
`Interrupt input
`
`Reset input
`
`Power-on reset input
`
`Interrupt input
`
`Interrupt input
`
`Interrupt input
`
`Interrupt input
`
`Interrupt input (see also C4)
`
`Interrupt input
`
`Interrupt input
`
`Interrupt input
`
`Interrupt input
`
`not used
`
`I/0 port (see also NIL2)
`
`I/0 port
`
`Slow interrupt output
`
`Fast interrupt output
`
`not used
`
`Keyboard (serial) input
`
`Keyboard (serial) output
`
`15
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`.I
`
`SCEA Ex. 1054 Page 15
`
`

`
`Block Level Wiring
`
`3.2 MEMC wiring
`I
`
`Signal
`
`Connects
`
`I
`
`Comment
`
`A[25:0]
`
`ARM/A[25:0), Addr latch
`
`Address bus inputs
`
`ARM/NR/W, Addr latch
`
`Read/write input
`
`ARM/NB/W
`
`ARM!NMREQ
`
`ARM/SEQ
`
`ARM/NTRANS
`
`Address latch
`
`ARM!MCLK
`
`Byte/word input
`
`Memory request input
`
`Sequential access input
`
`Supervisor mode input
`
`Phase 1 clock
`
`Phase2cloclc
`
`ARM/DBE, dbe pin
`
`Data bus enable output
`
`NR/W
`
`NB/W
`
`NMREQ
`
`SEQ
`
`SPVMD
`
`PHl
`
`PH2
`
`DBE
`
`ABORT
`
`NIORO
`
`NIOGT
`
`CKIN
`
`REFCK
`
`RESET
`
`ARM/ABORT
`
`IOEB/Nfiorq
`
`IOEB/Nfiogt
`
`Clock generator
`
`lOEB
`
`Nrst pin
`
`RA[9:0)
`
`r.t[9:0] pins
`
`NRAS
`
`Nms pin
`
`Abort input
`
`1/0 request output
`
`1/0 grant input
`
`Main memory/processor clock input
`
`Reference clock output
`
`Reset input (inverted)
`
`RAM address outputs
`
`RAM row address strobe output
`
`NCAS[3:0)
`
`Ncas{3:0] pins
`
`RAM column address strobe outputs
`
`NROMCS
`
`Nromcs pin
`
`ROM select output
`
`VlDC/NVIDW
`
`Video controller write output
`
`VIDC/FL YBK, IOC/IR
`
`Flyback input
`
`V IDC/NHSYNC,IOEB/Nhsyoc Hom.omal sync input
`
`VIDC/NVIDRQ
`
`VIDC/NVIDAK
`
`VIDC/NSNDAK
`
`VIDC/NSNDRQ
`
`IOC/NIL[l]
`
`Video data request input
`
`Video data acknowledge output
`
`Sound data request input
`
`Sound data acknowledge output
`
`Sound interrupt output
`
`NVIDW
`
`FLYBK
`
`NHSYNC
`
`NV I ORO
`
`NV I OAK
`
`NSNORQ
`
`NSNDAK
`
`NSIRQ
`
`16
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`SCE