ISSCC94 I SESSION 13 I NEURAL NETWORKS AND IMAGE SENSORS I PAPER TP 13.5
`
`TP 13.5: A CMOS Area image Sensor
`with Pixel-Level AfD Conversion
`Boyd Fowler, Abbas El Gamal, David X. D. Yang
`
`Infomation Systems Lab., Electrical Engineering Dept., Stanford University, CA
`
`Charge-coupled devices (CCD) are at present the most widely
`used technology for implementing area image sensors. How-
`ever, they suffer from low yields, consume too much power, and
`are plagued with SNR limitations due to the shifting and
`detection of analog charge packets, and the fact that data is
`communicated off chip in analog form [l].
`
`Several alternatives to CCD area image sensors use standard
`CMOS technology. Self scanned photodiode arrays are used to
`produce both binary and gray-scale image sensors [l, 21. Bipo-
`lar junction phototransistor arrays, and charge injection ar-
`rays are used [3, 41. However, these alternatives can suffer
`from low resolution due to limited pixel observation time,
`limited SNR due to analog sensing, and, as with CCDs, data is
`communicated off chip in analog form.
`
`This paper describes an area image sensor that can potentially
`circumvent the limitations of CCDs and their alternatives.It
`uses a standard CMOS process and can therefore be manufac-
`tured with high yield. Digital circuitry for control and signal
`processingcan be integrated with the sensor. Moreover, CMOS
`technology advances such as scaling and extra layers of metal
`can be used to improve pixel density and sensor performance.
`The analog image data is immediately converted to digital at
`each pixel using a one-bit sigma-delta modulator [51. The use
`of sigma-delta modulation allows the data-conversion circuitry
`to be simple and insensitive to process variations [51. A global
`"shutter" provides variable light input attenuation to achieve
`wide dynamic range [21. Data is communicated off chip in a
`digital form, eliminating the SNR degradation of analog data
`communication. (Figure 1)
`
`To demonstrate the viability of the approach, an area image
`sensor chip is fabricated in a 1.2pm CMOS technology. A
`functional block diagram of the chip is given in Figure 2. It
`consists of an array of 64x64 pixel blocks, a clock driver, a 6:64
`POW address decoder, 64 latched sense amplifiers, and 16 4:P
`column multiplexers. The chip also contains data compression
`circuitry not described in this paper. A die micrograph is given
`in Figure 3 and a summary of the main characteristics of the
`chip are listed in Table 1.
`
`A circuit schematic of the function implemented at each pixel
`is given in Figure 1. The phototransistor is a vertical bipolar
`pnp transistor. The emitter is formed using source-drain p"
`diffusion, the base is the n-well surrounding the emitter and
`the collector is the p-substrate. The n-well is exposed to light,
`while the rest of the circuitry is covered with the second level
`of metal to reduce the chance of photon-induced latch-up.
`Physical construction and operation ofbipolar phototransistors
`are described in References 7 and 6. Control of the input
`photocurrent is by setting the duty cycle (the ratio between the
`on and off times) of the shutter input SHU'ITER - the higher
`the duty cycle, the larger the input photocurrent. Current from
`the phototransistor is integrated on C1 and quantized using a
`regenerative latch clocked via PHI2. The quantized value is
`converted into a current using a l b D/A converter and fed back
`to the input capacitor C1. The duty cycle of PHI1 and the
`voltage VBIASl control the magnitude of the feedback signal
`Delta. PHI1 and PHI2 constitute a two-phase nonoverlapping
`
`clock. At the completion of each two-phase dock cycle 21 siirgle
`bit is produced. The bit is read by enabling the word lhc
`WORD. If the bit is high the precharged bit line BIT is puilcd
`down and sensed by a simple single-ended sense amplifier.
`
`The operation of the area image sensor chip is as follows: after
`an image is focused on the chip the sigma-delta modulators are
`reset via the global RESET signal. SHU"ER is then globally
`set to maximize image SNR without saturating the data ron-
`version circuitry. Next the sigma-delta modulators are glo-
`bally clocked at a rate Fa above the image frame rate ZF,. This
`is necessary since a sigma-delta modulator reduces quantiza-
`tionerror at the cost ofextra data. At the endofeach clock cycle
`the outputs of the sigma-delta modulators form a 64x64 array
`ofbits referredto as a"bit plane." Each bit planeis read out row
`by row. The image is fully capturedusing a number of bit planes
`determined by the target SNR. Using the theoretical analysis
`in Reference 5, the number of bit planes L needed versus SNR
`is given by
`SNR = 910g,L - 5.2dB.
`
`The maximum achievable SNR is measured at 61dB. SNR
`degradation due to charge injection of digital circuitry close to
`analog sensors is negligible since the frequency of operation is
`very low (1kHz) and the circuitry consumes less than 20nA per
`pixel.
`
`Figure 4 shows the output from a single-pixel sigma-delta
`modulator.
`
`Thedigitized pixelvaluesarereconstructed usingadecimation
`filter [51. Depending on the application, this reconstruction
`may be implemented in software, using special-purpose hard-
`ware external to the sensor, or integrated with the sensor. In
`a low-resolution application where no local reconstruction is
`needed, e.g. video phone or surveillance camera, the sensor
`digital output is compressed and immediately transmitted.
`Reconstruction is at the receiving end using general- or spe-
`cial-purpose hardware. If the image is to be displayed or
`processed locally one or more decimation filters are integrated
`with the sensor and an external RAM is used. Pixel values
`stored in RAM are recursively updated by reading into the
`sensor, updating their values using the decimation filters and
`the new bits from the corresponding sigma-delta modulators,
`and storing the new values back into the RAM. This scheme
`appears feasible even for a sensor with as many as 1M pixels
`operating at 30 frames per second at 8b-per-pixel resolution.
`
`The sensor can achieve a dynamic range (ratio of maximum
`non-saturating photocurrent to dark current) potentially
`greater than 93dB. This is because the magnitude of the
`photocurrent can be vaned by a factor of 1000, or 60dB, and the
`maximum measured SNR is approximately 33dB with the
`SHUTTER duty cycle set at loo%, the framc samplingrate set
`at 30H.z. and the oversampling ratio set at 64.
`
`print, and the image
`Figure 5 shows a scan from a 35"
`obtained by the sensor when contact exposed to the 35"
`negative. The sensor estimated total power ofless than 1mW is
`significantly lower than that of other types of image sensors.
`
`Acknowledgments
`
`The authors thank B. P. Wong and D. How for test-bed
`contributions, M. Godfrey, B. Wooley, and L. Hesselink for
`support and encouragement, and MOSIS for fabrication.
`
`Magna 2074
`TRW v. Magna
`IPR2015-00436
`
`

`
`ISSCC94 /THURSDAY, FEBRUARY 17,1994 / SUNSET / 3:45 PM
`
`ill
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`VBI,\SZt-----
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`Figure 1: Pixel schematic.
`
`Two Pharc Cluck l n p i i u
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`Clock IhtrerY
`
`64 x 64 lmsge Scnwr Core
`
`a
`
`a
`
`0
`
`a
`
`a
`
`U
`
`L
`
`
`
`I
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`16 bil Output Data
`Figure 2: Image sensor chip functional block diagram.
`Figure 3: See page 344.
`
`0 0 0 1 0 0 0 2 0 0 0 3 0 0 0 4 0 0 0 5 0006 0 0 0 7 0 0 0 8 0 0 0 9
`Seconds
`
`I
`0 0 1
`
`-2'
`0
`
`6 !
`
`0
`
`0001 0 002 0 0 0 3 0 0 0 4 0005 0006 0007 0008 0 009 0 01
`
`Seconds
`
`I l l
`
`Figure 5: 300dpi scan of print from negative
`(top). 64x64 image by sensor using
`35"
`negative contact exposure (bot.).
`
`CMOS technology
`Die area
`Pixel area
`Transistoridpixel
`Phototransistor area
`Package
`Supply
`Maximum SNR
`Dynamic range
`Dissipation wlo pads
`Measurement T
`
`1.2pm 2-metal, 1-poly, n-well
`6.5~5.0"~
`60x60pm2
`22
`105pm2
`84-pin PGA
`5 v
`61dB
`93dB
`<lmW
`23°C
`
`Table 1: 64x64 area image sensor characteristics.
`
`References
`[l] Image Sensing Products 199211993, EG&G Reticon, Sunnyvale
`,CA, 1992.
`[21 Denyer, P. B., et al., "On-Chip CMOS Sensors for VLSI Imaging
`Systems," VLSI 91, Aug., 1991.
`[31 Michon, G. J., and H. IC Burke, "Charge Injection Imaging," ISSCC
`Digest of Technical Papers, pp. 138-139, Feb., 1973.
`[41 Tanaka, N., et al., "A310k Pixel Bipolar Imager (BASIS)," ISSCC
`Digest of Technical Papers, pp. 96-97, Feb., 1989.
`[5] Candy, J. C., "A Use of Double Integration in Delta Sigma
`Modulation," IEEE Trans. Comm., vol. 33, no. 3, pp. 249-258, March,
`1985.
`[61 Mead, C., "A Sensitive Electronic Percepter," Chapel Hill Confer-
`ence on VLSI, 1985.
`[71 Tanaka, N., et al., "A Novel Bipolar Imaging Device with Self-Noise
`
`Jan., Reduction 1989. Capability," IEEE Trans. Elec. Dev., vol. 36, no. 1, pp. 31-38,
`
`Figure 4 Single-pixel sigma-delta modulator output
`from HP54601A. PHU (top), pixel output (bottom).
`
`[81 Akiyama, I, et al, "A 1280x980 Pixel CCD Image Sensor," ISSCC
`Digest of Technical Papers, pp. 96-97, Feb., 1986.