CMOS Passive Pixel Imager Design Techniques
`
`by
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`Iliana L. Fujimori
`
`M.Eng. in Electrical Engineering and Computer Science,
`Massachusetts Institute of Technology,
`June 1997
`
`B.S. in Electrical Engineering and Computer Science,
`Massachusetts Institute of Technology,
`June 1997
`
`Submitted to the Department of Electrical Engineering and Computer Science
`in partial fulfillment of the requirements for the degree of
`
`Doctor of Philosophy in Electrical Engineering and Computer Science
`
`at the
`
`MASSACHUSETTS INSTITUTE OF TECHNOLOGY
`
`February 2002
`
`@Iliana L. Fujimori, 2002. All rights reserved.
`
`BARKER
`
`MASSACHUSEtTS INSTITUTE
`MASSACHUSETTS INSTITUTE
`OF TECHNOLOGY
`
`APR 1 6 2002
`
`LIBRARIES
`
`Author ...........
`
`Certified by.
`
`Department of Electrical Engifeering and Computer Science
`February 1, 2002
`
`Charles G. Sodini
`Professor of Electrical Engineering
`Thesis Supervisor
`
`A ccepted by .................
`
`Arthur C. Smith
`Chairman, Department Committee on Graduate Students
`
`...................
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`
`2
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`

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`CMOS Passive Pixel Imager Design Techniques
`by
`
`Iliana L. Fujimori
`
`Submitted to the Department of Electrical Engineering and Computer Science
`on February 1, 2002, in partial fulfillment of the
`requirements for the degree of
`Doctor of Philosophy in Electrical Engineering and Computer Science
`
`Abstract
`CMOS technology provides an attractive alternative to the currently dominant CCD tech-
`nology for implementing low-power, low-cost imagers with high levels of integration. Two
`pixel configurations are possible in CMOS technology: active and passive. The active pixel
`requires a minimum of three transistors to convert light to voltage. The passive pixel, on the
`other hand, consists of a single transistor, and its output is in the form of charge. Column-
`parallel opamps are used to amplify the charge to a voltage output. The main advantage of
`the passive pixel is a higher fill factor in a given pixel geometry. This advantage becomes
`increasingly important as we scale to smaller pixel sizes. The higher fill factor comes at a
`high cost as the charge output on the high impedance node of the column line is susceptible
`to disturbances, namely a parasitic current and temporal noise. The goal of this thesis is
`to determine the source and effects of the disturbances on the image sensor characteristics
`and the repercussions for scaling to high-density arrays.
`A signal-dependent parasitic current composed of optically-generated carrier diffusion,
`blooming and subthreshold currents contaminates the pixel output. This parasitic current
`is detrimental to the imager because a few bright pixels can affect the rest of the pixels
`on the column line, resulting in bright vertical stripes on the image. A correlated-double
`sampling circuit in a differential architecture is used to remove the effects of the parasitic
`current. Column fixed-pattern noise is maintained below 1.5% for the linear illumination
`range of the imager.
`A noise analysis reveals the opamp read noise is the dominant source of temporal noise.
`The effects of the sample-and-hold readout circuit on the output-referred opamp read noise
`are modeled and closely match the measured noise. The output read noise power is directly
`proportional to the vertical resolution of the imager and inversely proportional to the pixel
`area, resulting in a strong dependence between noise and pixel density.
`This co-dependence is further analyzed in a scaling model where the fill factor, noise
`and dynamic range are observed for varying pixel size and vertical resolution over three
`fabrication technologies. The fill factor decreases with pixel size, and is highest for the
`technology with the smallest feature size, 0.18pm. The noise increases with decreasing
`pixel size and increasing vertical resolution and has the best performance in the 0.18pm
`technology. The dynamic range decreases with pixel density, but has a strong dependence
`on the power supply voltage of the technology.
`
`Thesis Supervisor: Charles G. Sodini
`Title: Professor of Electrical Engineering
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`3
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`4
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`Acknowledgments
`
`After ten and a half years at MIT, I feel indebted to a multitude of extraordinary individuals.
`
`This page is by no means complete, as it allows me to thank only a small fraction of those
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`who helped shape my decade at the 'tute.
`
`I would first like to thank my advisor and mentor, Prof. Charlie Sodini, for his guidance
`
`and support during the length of this project. His advice and encouragement proved more
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`valuable than any CAD program in the world! I also wish to acknowledge my thesis readers,
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`Prof. Harry Lee and Marc Loinaz, for taking the time to read my thesis. Their many
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`suggestions and challenging questions helped shape this thesis.
`
`Many thanks go to my contemporaries of the Sodini group, Ching-Chun Wang, Pablo
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`Acosta-Serafini, and Don Hitko, for listening, humoring, commiserating, and going to Tosci's
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`at a moment's notice.
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`I am also thankful to the rest of the Sodini/Lee groups for their
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`support and friendship: Ayman Shabra, Kush Gulati, Dan McMahill, Susan Dacy, Mark
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`Spaeth, Mark Peng, and Andy Wang.
`
`I am thankful to Pat Varley for showing me the ropes around the MIT procurement
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`system. I thank Marilyn.Pierce and Monica Bell for their friendly reminders about depart-
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`mental requirements and deadlines. Many thanks go to Myron (Fletch) Freeman and Mike
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`Hobbs for all their help with computer emergencies.
`
`I thank my grad school buddies for making this academic experience a little less aca-
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`demic: Samara Firebaugh, Alice Wang, Joel Voldman, Jeanie Cherng and Debb Hodges-
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`Pabon. I also wish to thank all my 6.012 students (Spring 97 and Fall 99) for inspiring me
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`to seek a career in teaching someday.
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`I am extremely grateful to my fiance Zony Chen for his love and support, especially
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`during the final stages of this thesis. He played a crucial role in the conclusion of this thesis
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`by cooking for me, driving me to school and staying up with me to ensure I met deadlines.
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`Most of all I thank my parents, Pedro and Elizabeth Fujimori, for all the sacrifices they
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`made to get me to this point in life. Our journey to America was worth it all!
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`The author was funded by an NSF fellowship, and a Lucent Technologies and GRPW
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`fellowship. This project was funded by DARPA contract DAAL-01-95-K-3526 and the MIT
`
`Center for Integrated Circuits and Systems.
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`5
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`Dedication
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`I dedicate this thesis to Uchan and Twooey.
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`Contents
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`1 Introduction
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`1.1 M otivation
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`1.2 Thesis Organization
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`2 Passive Pixel
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`2.1 Background
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`2.3.1 Quantum efficiency .
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`2.4 Pixel Readout - From electrons to V(
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`2.4.1 Output circuit reset
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`Imager Performance
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`2.8 Passive vs. Active Pixels .
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`3 Parasitic Current
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`3.1 Sources of parasitic current
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`3.2 Effects of parasitic current .
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`3.3 Removal of parasitic current .
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`3.4 Results.
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`4 Noise in Passive Pixels
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`4.1 Temporal noise sources .
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`4.2 Opamp read noise
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`4.3.1 Pixel reset noise
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`4.4.1 Pixel dark current shot noise
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`4.6 Temporal noise measurements.....
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`4.6.1 Output noise spectrum.....
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`4.6.4 Varying Cout
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`4.7 Fixed-pattern noise .
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`4.7.1 Pixel fixed pattern noise .
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`4.8 Performance comparison .
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`5 Scaling of passive pixels
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`5.1 Scaling parameters
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`5.1.3 Technology
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`5.2 Effects of scaling
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`6 Conclusions
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`6.1 Thesis Contributions .
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`6.2 Future Work
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`108
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`A Appendix A - Implementation of Diff.
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`Architecture with
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`A.0.2 CDS Design .
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`A.0.3 Programmable Analog Buffers
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`A .0.4 Analog M ux . .
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`115
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`A.0.5 Row Decoder
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`12
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`List of Figures
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`2-1
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`2-4
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`Cross-section of passive pixel with N-well to P-substrate photodiode.
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`Single-Ended Passive Pixel Readout Circuit and Clock Phases.....
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`Pixel output for different ratios of
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`Reset phase with opamp offset voltage ..
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`2-12
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`Passive Pixel Cross Section with N-diffusion to P-substrate photodiode.
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`Passive Pixel Cross Section with N-well to P-substrate photodiode.
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`2-14
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`Passive Pixel Cross Section with P-diffusion to N-well photodiode.
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`2-15
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`Opamp transfer function ..
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`Layout of passive pixel with N-well to P-substrate photodiode.....
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`Layout of active pixel with N-well to P-substrate photodiode.
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`3-1
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`3-6 Layout mismatch of differential architecture to accentuate effects of parasitic current.
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`3-7 Effects of diffused carriers on pixel output with no pixels selected, pixel on column
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`2 selected and pixel on column 1 selected.
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`3-8 Differential Passive Pixel Architecture. .
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`3-9 Correlated Double Sampling Circuit. .
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`3-11 Sample image taken with passive pixel imager with CDS.
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`3-12 Imager Die Photo.
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`Auto-zero readout.
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`Sample-and-hold noise model in time doma
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`sample-and-hold noise model in frequency (
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`Auto-zero and loop gain transfer function.
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`Output-referred opamp read noise.....
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`4-12
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`4-18
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`Output noise power for different values of Cout.
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`4-20
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`4-21
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`5-2
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`Pixel fill factor as a function of pixel pitch.....
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`Noise components as function of pixel pitch. .
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`Output noise as function of pixel pitch.
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`Output noise as function of pixel pitch.
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`Output noise as function of spatial resolution.
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`Output noise as function of spatial resolution.
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`Dynamic range as function of pixel pitch.
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`100
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`5-10
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`A-i Block diagram of differential passive pixel imager with CDS circuit.
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`A-2 Signal path of analog passive pixel imager with CDS circuit .
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`A-3 Passive pixel layout with N-well photodiode
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`A-4 Section of passive pixel array .
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`A-5 CDS Schematic Diagram.
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`A-6 Programmable Analog Buffers. .
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`A-7 Analog multiplexer.
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`A-8 Row select decoder and driver circuit.
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`15
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`1616
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`

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`List of Tables
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`3.1 Passive Pixel Imager Characteristics.
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`61
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`4.1 Passive pixel noise power for single-ended output with single readout and differential
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`output with double readout.
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`4.2 Sources and effects of column FPN for passive pixel.
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`4.3 Performance comparison of passive pixel, APS and CCD. * Quoted value for green
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`light was multiplied by factor of three to approximate monochrome responsivity.
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`5.1 Design features for 0.6pm, 0.35pm, and 0.6Lm .
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`17
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`

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`1818
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`

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`Chapter 1
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`Introduction
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`1.1 Motivation
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`The increased demand for affordable consumer digital cameras has led camera manufactur-
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`ers to look beyond the mature, but costly, Charge-Coupled Devices (CCD) technology to
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`alternative methods in solid-state imaging, such as CMOS image sensors [1],
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`[2]. CMOS
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`imagers can be integrated with analog and digital functional blocks in a standard CMOS
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`process leading to significant cost reductions [3]. Additional benefits include random access
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`readout and low power consumption [4].
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`In addition to low cost and low power, the consumer digital camera market demands
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`high spatial resolution [5] in order to match the quality of high-definition images produced
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`with film cameras. Since the cost of an imager is directly proportional to silicon area, the
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`combination of low cost and high resolution specifications can be achieved with a high-
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`density imager containing more pixels per unit area. The reduction in pixel area, however,
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`results in lower fill factor, or ratio of photodiode to pixel area for a given technology. Most
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`CCD and CMOS imagers currently use microlenses to improve the collection efficiency of
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`shrinking pixels. While they provide a temporary solution, microlenses are costly and their
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`efficiency is beginning to reach limits for small pixels [6].
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`Recent efforts to achieve high fill factors in small pixel area have focused on reducing
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`the number of transistors and contacts per pixel [7],
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`[8]. Active pixel sensors (APS) using
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`capacitively coupled bipolar transistors are also a viable option for high density arrays [9],
`but require a costly BiCMOS process and suffer from fixed-pattern noise (FPN) values as
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`high as 10% [10].
`
`19
`
`

`
`The CMOS passive pixel presents a promising alternative to the active pixel for achieving
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`a high fill factor in small pixel geometries. Similar to the history of the single-transistor
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`DRAM cell [11], the passive pixel has the potential to make high-density imaging arrays
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`available at a lower cost. For a given technology and fill factor, the passive pixel can achieve
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`a higher pixel density. Conversely, for a given technology and pixel density, the passive pixel
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`yields a larger fill factor. Consisting of a single transistor for readout and row select, the
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`passive pixel has the added advantage of a lower pixel FPN and a linear transfer function.
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`Fill factors as high as 80 % have been reported for a CIF format passive pixel imager [12].
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`The advantages of using a passive pixel for its higher fill factor come at a high cost.
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`Since charge-to-voltage conversion does not occur within the pixel, the charge signal becomes
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`extremely sensitive to disturbances on the column line. Additional implants and fabrication
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`steps can be used to reduce these disturbances [13],
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`[14], but the increase in cost and
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`complexity does not justify the use of a passive pixel imager. The goal of this thesis is to
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`identify the source/s of the disturbances, quantify its effects and determine the limitations
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`it poses on scaling to high-density arrays.
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`One of the disturbances manifests itself in the form of a leakage current, or parasitic
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`current, at each column line. Three mechanisms are identified as the causes of this current:
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`optically-generated carrier diffusion, blooming and subthreshold currents. The effects of
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`this current are catastrophic to the output signal as a few bright pixels can contaminate
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`the output of all pixels on the column line, leading to bright vertical streaks in the image.
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`Column FPN measurements demonstrate a correlated double-sampling (CDS) circuit in a
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`differential architecture is effective in removing the effects of the parasitic current.
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`An additional problem that limits the signal-to-noise ratio (SNR) of passive pixels for
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`large imaging arrays is the temporal noise. In this thesis, the temporal noise is decomposed
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`into the basic components: read noise, reset noise and dark current shot noise. Measure-
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`ments indicate that the opamp read noise is the main contributor to the noise. The read
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`noise of the amplifier, which is not present in active pixels, is amplified by the loop gain of
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`the output circuit,
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`Cf b
`is the feedback capacitance. Since Cline is proportional to the number of rows per column
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`, where Cline is the parasitic capacitance of the column line and Cfb
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`and Cfb is designed to match the pixel capacitance, the closed-loop gain which amplifies
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`the column amplifier noise is unusually high for passive pixel output circuits, i.e. > 50, and
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`therefore limits the SNR for low light levels and the dynamic range of the imager.
`
`20
`
`

`
`The severity of the temporal noise becomes obvious when scaling to higher density
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`arrays. An increase in the number of rows leads to an increase in the loop gain through
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`the line capacitance. A smaller pixel size further exacerbates the problem by decreasing
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`the feedback capacitance and thus increasing the loop gain. The scaling of both parameters
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`therefore result in higher noise. Designing in a smaller fabrication technology (i.e. 0.18pm)
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`can alleviate the noise problems by increasing the pixel capacitance through a higher fill
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`factor, and decreasing the line capacitance with smaller row select transistors. The lower
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`power supply voltage, however, significantly reduces the dynamic range.
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`1.2 Thesis Organization
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`Chapter 2 provides a brief background on the passive pixel and a derivation of the expression
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`relating photons and output voltage. The passive pixel structure and amplifier specifications
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`are also discussed. A comparison between the active vs. passive pixels is given.
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`Chapter 3 introduces the sources of parasitic current and illustrates its effects on the
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`pixel output. A CDS circuit in a differential architecture is then presented. FPN measure-
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`ments quantify the efficiency of the CDS circuit and an image demonstrates the effects of
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`the parasitic current have been completely removed.
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`The temporal and FPN sources are listed in Chapter 4. The effect of each noise source
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`on the output voltage is explained and noise measurements are presented for a number of
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`circuit parameters.
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`The limits of the passive pixel when scaling for high-density arrays are illustrated in
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`Chapter 5. The effects of decreasing pixel size and increasing vertical resolution on the pixel
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`fill factor, temporal noise and dynamic range are observed for three fabrication technologies.
`
`Chapter 6 concludes this thesis with a list of contributions and ideas for future work.
`
`21
`
`

`
`2222
`
`

`
`Chapter 2
`
`Passive Pixel
`
`This chapter begins with a background of previous work done on the passive pixel. A
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`typical CMOS passive pixel architecture is then presented. The pixel operation is divided
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`into two parts: light-to-charge conversion, and charge-to-voltage amplification. The final
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`result is an expression between the photon flux and the output voltage. Second order
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`effects, such as image lag, finite opamp gain and opamp offset voltage, are also considered.
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`The implementation of a CMOS passive pixel is described in Sec. 2.6. Advantages and
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`disadvantages of three different photodiode implementations are discussed. An explanation
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`of the effects of pixel and parasitic line capacitance on opamp specifications is also presented.
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`A comparison between the active and passive pixel is given. Three advantages, mainly
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`a larger fill factor, lower pixel fixed-pattern noise (FPN) and a linear transfer function,
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`are cited as the motivation for this thesis. A larger fill factor is usually achieved with the
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`passive pixel since it requires a single transistor, leaving plenty of pixel area for photon
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`sensing. The lower pixel FPN is attributed to the simplicity of the passive pixel.
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`In
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`contrast with the active pixel, the passive pixel does not have any amplification or level
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`shifting within the pixel, making it independent of device mismatches from pixel to pixel.
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`Finally, the passive pixel uses a voltage-independent poly-to-poly capacitor, rather than the
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`photodiode depletion capacitance, for the charge-to-voltage conversion, leading to a linear
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`transfer function.
`
`23
`
`

`
`2.1 Background
`
`The passive pixel has a long history, longer than CCD's and the active pixel, dating back
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`to 1967. G. P. Weckler was the first to implement a photodiode with an MOS process and
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`operate it in integrating mode [15]. P. J. W. Noble followed him a year later with a 10-by-10
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`array with an integrating charge amplifier [16]. Both Weckler's and Noble's designs were
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`limited by the dark current and high parasitics, not to mention FPN and blooming, of the
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`technology at the time.
`
`Almost thirteen years later, Hitachi reported the implementation of a 320 x 244 passive
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`pixel sensor with high sensitivity and a FPN suppressing circuit. Using an additional P-
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`implant, S. Ohba et. al. successfully reduced the FPN by 20 dB [13]. Hitachi later combined
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`the passive pixel with a three-phase horizontal bulk charge-transfer device, similar to the
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`ones used by CCD's at the time. Using a hybrid circuit made up of enhancement-mode
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`and depletion-mode transistors, H. Ando et. al. were able to isolate the high column line
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`capacitance in order to limit the read noise of the output amplifier [14].
`
`Profitting from the advances in VLSI technology in 1989, R. H. Wyles integrated a
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`full column-parallel architecture in which one capacitive feedback transimpedance amplifier
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`is used to read each column [17]. Prior to this point, column-parallel architectures had
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`been difficult to implement since the readout circuits were too bulky to pitch-match the
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`pixel. Shortly thereafter, D. Renshaw and P. B. Denyer reported on the integration of
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`computational and control functions with 786 x 576 passive pixel arrays in a CMOS 0.8pm
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`technology [18].
`
`More recently, W. Hoekstra et. al. published a CIF format (352(H) x 288(V)) passive
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`pixel array in a CMOS 0.5pm technology, achieving a fill factor of 80% [12]. Despite the high
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`fill factor it represents, the passive pixel has been dismissed as "noisy" and "unscalable"
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`for visible range imagers [19],
`
`[20].
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`2.2 Architecture
`
`Fig. 2-1 shows the architecture of a simple passive pixel imager, consisting of a pixel array,
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`output circuit and row/column decoders [18]. The pixel array is read out in a typical raster-
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`scan fashion. An entire row is selected for readout simultaneously and the corresponding
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`charge from each pixel appears on the respective column line. The multiplexer then selects
`
`24
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`

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`one column at a time for charge-to-voltage conversion by the capacitive-feedback amplifier.
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`_0
`0
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`JL
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`_JL
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`rowsel
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`col
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`Multiplexer
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`Figure 2-1: Simple Passive Pixel Architecture.
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`2.3 Pixel Operation - From photons to electrons
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`Pixel photocurrent arises when photons exhibiting an energy higher than the bandgap
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`energy of the material (1.1 eV for Silicon) generate electron-hole pairs, as shown in figure 2-
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`2. The electric field at the edge of the depletion region of the photodiode then separates
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`the electron-hole pairs and the corresponding electrons and holes are collected in the N-well
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`and P-substrate respectively.
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`The amount of charge collected in the N-well depends on the location of the generated
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`carriers. If the carriers are generated right at the edge of the depletion region, they will be
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`immediately separated and collected. If, on the other hand, the photon is absorbed in the
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`N-well or P-substrate, the carriers will have to diffuse to the depletion region bef