A CMOS Area Image Sensor With Pixel Level A/D Conversion
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`Boyd Fowler
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`Abbas El Gamal
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`David X. D. Yang
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`Information Systems Laboratory, Electrical Engineering Department, Stanford University, Stanford, CA 94305-4055
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`email: fowler@isl.stanford.edu abbas@isl.stanford.edu dyang@isl.stanford.edu
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`Phone: 1-415-723-3473 FAX: 1-415-723-8473
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`Session Number: TP 13.5
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`June 21, 2001
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`Abstract
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`A CMOS 64 × 64 pixel area image sensor chip using Sigma-Delta modulation at each pixel for A/D
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`conversion is described. The image data output is digital. The chip was fabricated using a 1.2µm two
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`layer metal single layer poly n-well CMOS process. Each pixel block consists of a phototransistor and 22
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`MOS transistors. Test results demonstrate a dynamic range potentially greater than 93dB, a signal to
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`noise ratio (SNR) of up to 61dB, and dissipation of less than 1mW with a 5V power supply.
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`1
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`Magna 2029
`TRW v. Magna
`IPR2015-00436
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`

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`Boyd Fowler, Abbas El Gamal, and David X. D. Yang
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`2
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`Charge-coupled devices (CCD) are at present the most widely used technology for implementing area
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`image sensors. CCD image sensors have their shortcomings, however. They suffer from low yields, they
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`consume too much power [3], and they are plagued with SNR limitations due to the shifting and detection
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`of analog charge packets, and the fact that data is communicated off chip in analog form.
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`Several alternatives to CCD area image sensors that use standard CMOS technology have been developed.
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`Self scanned photodiode arrays have been used to produce both binary and grayscale image sensors [2, 3].
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`Bipolar junction phototransistor arrays [6], and charge injection arrays [5] have also been used. However,
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`these alternatives can suffer from low resolution due to limited pixel observation time, limited SNR due to
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`analog sensing, and as with CCDs, data is communicated off chip in analog form.
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`In this paper we describe an area image sensor that can potentially circumvent the limitations of CCDs
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`and their alternatives. The proposed image sensor uses a standard CMOS process and can therefore be
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`manufactured with high yield. Digital circuitry for control and signal processing can be integrated with
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`the sensor. Moreover, CMOS technology advances such as scaling and extra layers of metal can be used to
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`improve pixel density and sensor performance.
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`The analog image data is immediately converted to digital at each pixel using a one-bit Sigma-Delta
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`modulator [1]. The use of Sigma-Delta modulation also allows the data conversion circuitry to be simple
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`and insensitive to process variations [1]. A global “shutter” provides variable light input attenuation to
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`achieve wide dynamic range [2]. Data is communicated off chip in a digital form, thus eliminating the SNR
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`degradation of analog data communication.
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`To demonstrate the viability of our approach, an area image sensor chip has been designed and fabricated
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`in a 1.2 µm 1 CMOS technology. A functional block diagram of the chip is given in Figure 2. It consists of
`an array of 64 × 64 pixel blocks, a clock driver, a 6:64 row address decoder, 64 latched sense amplifiers, and
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`16 4:1 column multiplexers. The chip also contains data compression circuitry which will not be described
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`in this paper. A die photograph is given in Figure 5 and a summary of the main characteristics of the chip
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`are listed in Table 1.
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`1µ is the symbol for 10
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`−6.
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`

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`Boyd Fowler, Abbas El Gamal, and David X. D. Yang
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`3
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`A circuit schematic of the function implemented at each pixel is given in Figure 1. The phototransistor
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`is a vertical bipolar PNP transistor; the emitter is formed using source-drain p+ diffusion, the base is the
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`n-well surrounding the emitter and the collector is the p- substrate. The n-well is exposed to light, while
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`the rest of the circuitry is covered with the second level of metal to reduce the chance of photon induced
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`latch-up. The physical construction and operation of bipolar phototransistors are described in [7, 4]. Control
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`of the input photocurrent is achieved by setting the duty cycle (the ratio between the on and off times) of
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`the shutter input SHUTTER — the higher the duty cycle the larger the input photo current. Current from
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`the phototransistor is integrated on C1 and quantized using a regenerative latch clocked via PHI2. The
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`quantized value is converted into a current using a 1 bit D/A converter and fed back to the input capacitor
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`C1. The duty cycle of PHI1 and the voltage VBIAS1 control the magnitude of the feedback signal Delta.
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`PHI1 and PHI2 constitute a two phase nonoverlapping clock. At the completion of each two phase clock
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`cycle a single bit is produced. The bit is read by enabling the word line WORD. If the bit is high the
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`precharged bit line BIT is pulled down and sensed by a simple single-ended sense amplifier.
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`The operation of the area image sensor chip is as follows: after an image is focused on the chip the Sigma-
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`Delta modulators are reset via the global RESET signal. SHUTTER is then globally set to maximize
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`image SNR without saturating the data conversion circuitry. Next the Sigma-Delta modulators are globally
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`clocked at a rate Fs above the image frame rate 2Fd. This is necessary since a Sigma-Delta modulator
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`reduces quantization error at the cost of extra data. At the end of each clock cycle the outputs of the
`Sigma-Delta modulators form a 64 × 64 array of bits referred to as a “bit plane.” Each bit plane is read out
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`row by row. The image is fully captured using a number of bit planes determined by the target SNR. Using
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`the theoretical analysis in [1] the number of bit planes L needed versus SNR is given by
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`SNR = 9 log2 L − 5.2dB.
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`The maximum achievable SNR has been measured at 61dB. SNR degradation due to charge injection of the
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`digital circuitry in close proximity to the analog sensors is negligible since the frequency of operation is very
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`low (1kHz) and the circuitry consumes less than 20nA per pixel.
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`Figure 3 shows the output from a single pixel’s Sigma-Delta modulator.
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`Boyd Fowler, Abbas El Gamal, and David X. D. Yang
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`4
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`The digitized pixel values are reconstructed using a decimation filter [1]. Depending on the type of
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`application in which the sensor is used, this reconstruction may be implemented in software, using special
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`purpose hardware external to the sensor, or integrated with the sensor.
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`In a low resolution application
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`where no local reconstruction is needed, e.g. video phone or surveillance camera, the sensor digital output
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`is compressed and immediately transmitted. Reconstruction is done at the receiving end using general or
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`special purpose hardware. If the image is to be displayed or processed locally one or more decimation filters
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`are integrated with the sensor and an external RAM is used. The pixel values stored in the RAM are
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`recursively updated by reading them into the sensor, updating their values using the decimation filters and
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`the new bits from the corresponding sigma delta modulators, and storing the new values back into the RAM.
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`This scheme appears feasible even for a sensor with as many as 1 million pixels operating at 30 frames per
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`second at 8 bits per pixel resolution.
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`The sensor can achieve a dynamic range2 potentially greater than 93dB. This is because the magnitude
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`of the photocurrent can be varied by a factor of 1000, or 60dB, and the maximum measured SNR is approx-
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`imately 33dB with the SHUTTER duty cycle set at 100%, the frame sampling rate set at 30Hz, and the
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`oversampling ratio set at 64.
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`Figure 4 shows a scan from a 35mm print, and the image obtained by the sensor when contact exposed
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`to the 35mm negative.
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`The sensor’s estimated total power of less than 1 mW is significantly lower than that of other types of
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`image sensors.
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`We would like to thank B. P. Wong and D. How for their contribution to the test bed, M. Godfrey, B.
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`Wooley, and L. Hesselink for their support and encouragement, and MOSIS for fabrication.
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`References
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`[1] J. C. Candy. “A Use of Double Integration in Sigma Delta Modulation”. IEEE Trans. Comm., 33(3):249–
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`258, March 1985.
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`2The ratio of the maximum non-saturating photocurrent to the dark current.
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`Boyd Fowler, Abbas El Gamal, and David X. D. Yang
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`5
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`[2] P.B. Denyer et al. “On-chip CMOS sensors for VLSI imaging systems”. In VLSI 91, Edinburgh, UK,
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`August 1991.
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`[3] EG&G Reticon, 345 Potrero Ave., Sunnyvale, CA 94086-4197 USA. Image Sensing Products 1992/1993,
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`1992.
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`[4] C. Mead. “A Sensitive Electronic Photoreceptor”. In 1985 Chapel Hill Conference on VLSI, Chapel Hill,
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`NC, 1985.
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`[5] G. J. Michon and H. K. Burke. “Charge Injection Imaging”. In ISSCC Digest of Technical Papers, pages
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`138–139, February 1973.
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`[6] N. Tanaka et al. “A 310k Pixel Bipolar Imager (BASIS)”. In ISSCC Digest of Technical Papers, San
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`Fransisco, CA, February 1989.
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`[7] N. Tanaka, T. Ohmi, and Y. Nakamura. “A Novel Bipolar Imaging Device with Self-Noise Reduction
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`Capability”. IEEE Trans. Elec. Dev., 36(1):31–38, January 1989.
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`Boyd Fowler, Abbas El Gamal, and David X. D. Yang
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`6
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`1 bit A/D
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`2-D Mux
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`VBIAS1
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`PHI2
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`SHUTTER
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`Integrator
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`Phototransistor
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`VBIAS2
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`C1
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`RESET
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`VBIAS1
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`PHI1
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`1 bit D/A
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`WORD
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`BIT
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`Figure 1: Figure 1: Pixel Schematic. TP-13.5: ”A CMOS Area Image Sensor with Pixel-Level A/D Conver-
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`sion”, Boyd Fowler, Abbas El Gamal, and David X. D. Yang
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`Boyd Fowler, Abbas El Gamal, and David X. D. Yang
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`7
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`Two Phase Clock Inputs
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`Clock Drivers
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`64 x 64 Image Sensor Core
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`6 bit Address
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`6:64 Row Decoder
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`4 Column Outputs
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`4 Column Outputs
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`Output
`Latch
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`D
`Q
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`D
`Q
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`D
`Q
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`D
`Q
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`D
`Q
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`D
`Q
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`D
`Q
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`D
`Q
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`4:1 Multiplexer
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`4:1 Multiplexer
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`2 bit column
`decode
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`16 bit Output Data
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`Figure 2: Figure 2: Image Sensor Chip Functional Block Diagram. TP-13.5: ”A CMOS Area Image Sensor
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`with Pixel-Level A/D Conversion”, Boyd Fowler, Abbas El Gamal, and David X. D. Yang
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`

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`Boyd Fowler, Abbas El Gamal, and David X. D. Yang
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`8
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`0.001
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`0.002
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`0.003
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`0.004
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`0.005
`Seconds
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`0.006
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`0.007
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`0.008
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`0.009
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`0.01
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`0.001
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`0.002
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`0.003
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`0.004
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`0.005
`Seconds
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`0.006
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`0.007
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`0.008
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`0.009
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`0.01
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`0246
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`-2
`0
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`Volts
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`6
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`4
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`2
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`0
`0
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`Volts
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`Figure 3: Figure 3: Single pixel Sigma-Delta modulator output from HP54601A. The top graph is PHI2
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`versus time and the bottom graph is the pixel output waveform versus time. TP-13.5: ”A CMOS Area
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`Image Sensor with Pixel-Level A/D Conversion”, Boyd Fowler, Abbas El Gamal, and David X. D. Yang
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`

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`Boyd Fowler, Abbas El Gamal, and David X. D. Yang
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`9
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`Main Characteristics of 64x64 Area Image Sensor
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`Technology
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`Die Area
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`Pixel Area
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`1.2µm, 2-layer metal, 1-layer poly, nwell CMOS
`6500µm × 5000µm
`60µm × 60µm
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`Number of transistors per pixel
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`22
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`Phototransistor Area
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`105µm2
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`Package
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`Supply Voltage
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`Maximum SNR
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`Dynamic Range
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`Power Dissipation w/o Pads
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`Measurement Temperature
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`84pin PGA
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`5v
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`61dB
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`93dB
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`< 1 mW
`23◦C
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`Table 1: Table 1: Area Image Sensor Characteristics. TP-13.5: ”A CMOS Area Image Sensor with Pixel-
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`Level A/D Conversion”, Boyd Fowler, Abbas El Gamal, and David X. D. Yang
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`Boyd Fowler, Abbas El Gamal, and David X. D. Yang
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`10
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`Figure 4: Figure 4: 300dpi scan of print from negative (left). 64 × 64 image produced by sensor using
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`35mm negative contact exposure (right). TP-13.5: ”A CMOS Area Image Sensor with Pixel-Level A/D
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`Conversion”, Boyd Fowler, Abbas El Gamal, and David X. D. Yang
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`

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`Boyd Fowler, Abbas El Gamal, and David X. D. Yang
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`11
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`Figure 5: Figure 5: Die Photograph of 64 × 64 Image Sensor Chip. TP-13.5: ”A CMOS Area Image Sensor
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`with Pixel-Level A/D Conversion”, Boyd Fowler, Abbas El Gamal, and David X. D. Yang