1922
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 12, DECEMBER 1996
`
`ta
`
`Chye Huat Aw and Bruce
`
`A. Wooley, Fellow, IEEE
`
`Abstract-A 128 x 128-pixel image sensor with a 20 s-lOW4 s
`electronic shutter has been integrated in a 1.2-pm digital CMOS
`technology. The pixel cell consists of four PMOS transistors and a
`photodiode with antiblooming suppression. Each pixel measures
`24 pm by 24 pm and has a fill factor of 25%. Current is used to
`transfer pixel signals to the column readout amplifiers in order
`to minimize voltage swings on the highly capacitive column lines.
`Correlated double sampling is used to reduce intracolumn fixed
`pattern noise. The saturation voltage is 470 mV. The peak output
`signal to noise ratio is 45 dB, and the optical dynamic range is
`56 dB. The frame transfer rate is 1.7 ms per frame.
`
`I. INTRODUCTION
`ROWTH in the market for multimedia systems has
`generated an increasing demand for image acquisition
`systems that are able to directly import both video and
`photographic images into personal computers. Currently, such
`systems are usually implemented using charge-coupled device
`(CCD) technology. However, CCD imagers have several dis-
`advantages [1], [ 2 ] . First, although efforts have been made
`to integrate signal processing circuits together with CCD
`imaging arrays [3], [4], the CCD fabrication requirements
`can be incompatible with the fabrication yield and perfor-
`mance needed to implement large amounts of on-chip signal
`processing. Second, they require near perfect charge transfer
`between pixels in order to maintain signal integrity, and the
`charge transfer requirement becomes even more stringent as
`the array size increases. Finally, CCD arrays typically require
`the use of relatively high voltages, which is not compatible
`with deep-submicron VLSI technology. Notwithstanding their
`limitations, CCD technologies currently allow the implementa-
`tion of imagers with much smaller pixels than can be achieved
`with alternative approaches.
`To overcome the limitations of CCD imagers, attention is
`increasingly being focused on the possibility of implement-
`ing imaging arrays in standard CMOS technologies [5 ]-[ 1 11.
`CMOS image sensors with integrated signal processing have
`been implemented for a number of applications [12], [13].
`Most current CMOS imaging arrays have been designed for
`video applications, while less attention has been given to arrays
`designed specifically for digital photography.
`This paper describes the design and implementation of
`a prototype 128 x 128, active-pixel, standard-CMOS, still-
`image sensor suitable for digital photography applications that
`do not require the resolution of conventional film photography.
`Manuscript received May 6, 1996, revised July 23, 1996
`The authors are with the Center for Integrated Systems, Stanford University,
`Stanford, CA 94305-4070 USA.
`Publisher Item Identifier S 001 8-9200(96)08406-5
`
`128 x 128 - Pixel Array
`
`Row-Scan
`Shift
`Register
`
`Array
`Drivers
`
`Shutter Control
`Read Signal
`
`Logic
`
`Fig. 1. Image sensor architecture.
`
`Possible sub-array for
`exposure control and
`auto-focusing
`(not implemented in
`prototype)
`
`Column Readout
`
`Objectives in the design of this circuit included 1) implemen-
`tation in a standard digital CMOS technology, 2) a single 5-V
`power supply, 3) an electronic shutter with a wide range of
`exposure times, and 4) a readout speed fast enough for 640
`x 480-pixel video at 30 frames per second. Additional goals
`were a large dynamic range, low fixed pattern noise, low lag,
`antiblooming, low smear, and a fill factor greater than 20%.
`While state-of-art CCD sensors often include an electronic
`shutter capability, this feature typically requires the use of
`relatively high voltages.
`The prototype array was designed for implementation in
`a 1.2-pm, n-well CMOS process without the use of analog-
`specific components such as capacitors. Although designed for
`gray-scale imaging, the array can easily be adapted for color
`imaging through the addition of color filters to the CMOS
`process. The cost and complexity of the additional processing
`would be the same as that required for other types of integrated
`color image sensors. Adopting the design for video, rather than
`still image, applications is only a matter of redesigning the
`control logic to implement the proper timing control.
`
`11. ARCHITECTURE
`The architecture of the proposed image sensor is shown in
`Fig. 1. The core of the sensor is a 128 x 128 array of four-
`transistor active pixels. In response to input signals such as the
`Shutter Control and Read Signal, a control logic unit generates
`the internal signals needed to perform such tasks as opening
`the electronic shutter, scanning the array, and correlated double
`sampling readout. Row- and column-scan digital shift registers
`are used to generate the signals used to scan the rows and
`
`0018-9200/96$05,00 0 1996 IEEE
`
`Magna 2022
`TRW v. Magna
`IPR2015-00436
`
`

`
`AW AND WOOLEY A 128 X 128-PIXEL STANDARD-CMOS IMAGE SENSOR
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`n
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`Shutter Control
`
`Read Signal
`
`I L
`
`-
`Shutter
`
`I
`
`External Clock
`
`Read Active
`Output Signal
`
`Analog Output
`
`Fig. 2. Single frame exposure and readout sequence.
`
`columns, respectively, during readout. Each column of the
`array has a column readout amplifier that generates an analog
`output voltage proportional to the gray scale intensity of the
`image. An output buffer is used to drive external loads.
`A feature that can be easily implemented in the sensor,
`but was not included in this prototype, is the ability to read
`out a subarray of the image. Such a subarray can be used
`for exposure control and autofocusing prior to capturing the
`photograph. Image aspect ratio switching [3] can also be
`implemented easily.
`Incident light on each pixel of the imager generates a
`photocurrent that is integrated and stored as a voltage. Photo-
`integration is performed simultaneously on the entire array. A
`transconductance buffer in the pixel converts the stored voltage
`into a current that is read out on the column line. The use of a
`current-mode readout minimizes the voltage swings required
`on the highly capacitive column lines. Each column readout
`amplifier converts the current-mode signal from the selected
`pixel into an offset-compensated analog voltage sample that is
`multiplexed out sequentially.
`Fig. 2 illustrates the exposure and readout sequence for a
`single frame. Note that the timing is not to scale; the Shutter
`Control pulse is usually much longer than the readout timing.
`The Shutter Control and Read Signal provide the external
`control of the image sensor. The pixel array is held in a reset
`state until Shutter Control goes high. The electronic shutter is
`then "opened" for the duration of the Shutter Control pulse,
`thereby exposing the image. When the Shutter Control goes
`low, the electronic shutter is closed and readout commences on
`the assertion of Read Signal. The first row is activated and the
`signals in all pixels of that row are simultaneously read out and
`sampled by the column readout amplifiers. After settling, the
`sampled signals are sequentially multiplexed out through the
`output amplifier. The output signals are synchronized with the
`External Clock. Readout proceeds from row to row until the
`entire array has been scanned. The Read Active Output Signal
`indicates the duration of valid signals to facilitate external
`acquisition of the output data.
`111. CIRCUIT DESIGN
`
`A. Pixel Structure and Circuit
`In order to achieve a small pixel size, only a single type of
`MOSFET is employed within the pixel. For reasons explained
`
`Photodlodehransistor
`-
`
`M4
`
`Row =E
`
`Reset
`
`Fig. 3. Pixel circuit schematic.
`
`Column
`
`I
`
`l
`
`l
`
`
`
`Metal2 Light Shield and Power Bus
`
`P-diffusion
`/
`/
`Photo-diode ,
`
`N-well
`
`\
`, P-substrate
`
`Shutter Gate M3
`
`Photo-sensitive Area
`with Anti-blooming Suppression
`
`Fig. 4.
`Pixel cross-section view showing antiblooming structure and metal2
`light shield.
`
`later in this section, the use of p-diffusionln-well junctions as
`the photodiodes provides the benefit of antiblooming suppres-
`sion. Therefore, PMOS transistors are used in the pixel.
`Fig. 3 shows the circuit schematic of a pixel. It consists
`of four PMOS transistors and a photodiode. Transistor M1
`acts as a transconductance buffer that converts the voltage
`at node go into a current, M2 is the row access transistor,
`M 3 is the shutter transistor and M4 is the reset transistor.
`The pixel design, with the exception of the transconductance
`buffer, is similar to that described in [7]. The vertical column
`lines in the array are implemented using second-layer metal,
`while first-layer metal is used for the horizontal row lines. The
`VDD power bus is realized in second-layer metal and covers
`all active areas of the pixel except the photodiode.
`Prior to the exposure of a frame, M3 and M4 are on,
`resetting nodes pd and go to Keset. This reset action is
`fast and complete, resulting in low lag for rapidly changing
`frames. During exposure, M4 is turned off while the shutter
`transistor M 3 remains on. The photocurrent is integrated onto
`the parasitic capacitances at nodes go and pd. The shutter
`is closed by turning off 1113. The photosignal is stored as a
`voltage on node go. During readout, the row access transistor
`1112 is turned on, and the drain current of 1111 is fed via the
`column line to the column readout amplifier.
`A cross-sectional view of a pixel is presented in Fig. 4. To
`achieve antiblooming, a p-diffusionln-well junction is used
`as the photodiode so that excess charges generated by strong
`incident light will be drained away by the vertical substrate
`PNP bipolar action. This prevents the excess charges from
`leaking to neighboring pixels, to node go within the pixel, or
`
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 12, DECEMBER 1996
`
`I
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`Column
`
`Bias o
`
`Vcref
`
`Shutter Closed Pd
`
`( 4
`Fig 5
`Waveforms at nodes p d and go in the pixel during: (a) array reset,
`(b) exposure, (c) shutter closed, and (d) readout.
`
`directly to the column line through the output drain of the
`row access transistor M2. In addition to bringing in VDD, the
`Metal2 power bus serves as a light shield that covers all active
`areas of the sensor and prevents unwanted photo-integration
`at node go when the shutter gate is off. This light shield also
`helps to achieve low smear. Outside the active regions, Metal2
`is used to implement interconnects. Each pixel measures 24
`pm by 24 pm and has a fill factor of 25%.
`
`B. Pixel Operation
`Fig. 5 shows the waveforms at nodes pd and go during an
`exposure cycle. The pixels in a row are reset by holding both
`-
`Reset and Shutter low, turning on M 3 and M4. The voltages
`at nodes p d and go are thereby reset close to Keset. There is a
`small voltage drop across transistor M 4 during reset because
`light is continuously incident on the photodiode, which induces
`a positive photo current. If this voltage, which i s the drain-
`to-source voltage of M4, is small, it is given approximately
`by
`
`C1, C2, and Cc are MOSFET capacitors
`61, 62, and 83 are source followers
`
`Fig. 6. Column readout amplifier.
`
`The small-signal drain-to-source resistance of M 4 is nominally
`18 kR, while Iphoto is typically less than 1 PA. Thus, VDSM~
`is less than 18 nV and can be neglected.
`__
`During exposure Reset goes high, turning M 4 off, while
`Shutter remains IOW, so that M3 remains on. The photocurrent
`is then integrated onto the parasitic capacitances at pd and
`go. At the end of the exposure period, Shutter goes high,
`turning off M 3 and cutting off the photocurrent into node
`go. While the voltage at pd continues to rise, go holds a
`voltage proportional to the intensity of light falling on the
`pixel’s photodiode. A positive offset in the voltage at go is
`induced by charge injection that results from turning off M3.
`To the first order, this offset is cancelled by the correlated
`double sampling used in the readout amplifier.
`Readout is initiated when Row goes low, tuming on M2.
`The voltage at the drain of M1 falls from VDD to the bias
`voltage of the column line, and this change couples a small
`negative offset into node go. The drain current of M 1 is fed
`via the column line to the column readout amplifier.
`
`C. Column Readout Amplifier
`Fig. 6 is a schematic of the column readout amplifier. The
`design of this amplifier provides a low impedance load for the
`column line, converts the readout current from the selected
`pixel into a voltage that is proportional to the integrated
`photovoltage in the pixel, uses correlated double sampling to
`achieve low fixed pattern noise, and provides a column output
`reference voltage to reduce output voltage offset due to charge
`injection mismatch and bias ambiguity.
`M13 operates as a common-gate transistor so as to provide
`a low impedance load for the column line, thereby reducing
`the voltage swing required on the column. The current from
`the selected pixel is mirrored by the current mirror formed
`by M15 and M16. The negative feedback loop implemented
`by transistors M17-M20 forces the VDS of M16 to be very
`close to that of M15. M11 replicates the transconductance
`buffer transistor, M I , in the pixel cell, and the M15-Ml6
`current mirror forces the incremental current flowing through
`M11 to be the same as that in the selected pixel. The closed
`loop provided by the M17-M20 amplifier produces a voltage
`
`

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`AW AND WOOLEY: A 128 x 128-PIXEL STANDARD-CMOS IMAGE SENSOR
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`1925
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`Selected
`
`Control
`Signals
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`ReSet-u-
`
`Shutter-----\------
`
`vout
`
`operation of
`selected pixel
`
`1
`1
`Fig. 7 . Correlated double sampling of a single row.
`
`first
`readout
`
`reset
`
`I readout
`
`second
`
`...... I
`tput
`4
`I
`
`' Vcref
`
`Actual implementation of MOSFET-capacitors and adaptive biasing
`Fig. 8.
`in column readout amplifier.
`
`sampling sequence produces a high voltage at gl, while the
`second readout produces a low voltage corresponding to the
`reset value. This results in the top plate (gate) of C1, node
`n l in Fig. 6, being pulled below ground during readout of the
`pixel reset level. The drain-to-well junction of M23 would
`then be forward biased and G1 would be discharged. Adaptive
`biasing avoids this problem by moving the biasing voltage
`higher with higher g l voltage.
`Vcref provides a reference output level that compensates for
`the bias adjustment. It also serves to provide a local reference
`voltage so as to compensate for nonuniformities among the
`column readout amplifiers, such as mismatch in the source-
`follower buffers B2 and B 3 and the charge injection in the
`switches.
`
`D. Column Biasing
`A common-source transconductance stage such as M1 in the
`pixel cell is normally biased in the saturation region so as to
`achieve the maximum gain. However, in this image sensor, the
`column lines are biased at a high voltage in order to keep the
`pixel transconductance buffer M1 in the linear region during
`readout. Three reasons for this are as follows. First, in order
`to achieve a large dynamic range, Vreset in the pixel should
`be low. However, this will result in large readout current if
`M1 is operating in the saturation region, since a low Vreset
`corresponds to a large VGS for Ml. Increasing the channel
`length of M1 will reduce the readout current but will result in
`higher parasitic capacitance at node go in the pixel because of
`the increased gate capacitance, reducing the photosensitivity
`of the pixel. Therefore, M1 is operated in linear region so
`as to achieve lower readout current and power consumption.
`Second, if M1 operates in the saturation region, the readout
`current will vary widely with process variations. If M1 is
`biased in the linear region, its VDS can be controlled so as
`to compensate for such variations. Finally, biasing the column
`lines at a relatively high voltage provides a large voltage range
`at the input to the column readout amplifier, allowing more
`flexibility in its design.
`Fig. 9 shows how the biasing of the column lines is ac-
`complished. M B 1 and M B 2 in the bias generator mirror the
`transistors M1 and M2 in the pixels. M B 3 and IB1 mirror
`M13 and I 1 in the column readout amplifiers. The transistor
`sizes and current sources in the column bias part of the bias
`generator are four times those in the column readout amplifiers
`and the pixels in order to provide a low impedance drive for
`
`at node g l that is proportional to the voltage at node go in
`the pixel.
`As mentioned earlier, correlated double sampling is imple-
`mented in the readout process. The diagram in Fig. 7 illustrates
`the timing sequence of the double sampling for a single row.
`During the first readout period, the row access transistor, M2,
`in the selected pixel is turned on and the photovoltage at go
`in the pixel is proportionally reproduced at g l in the column
`readout amplifier. This voltage is sampled onto C1 when clock
`4 is high. Node n l at the other terminal of C1 is biased to
`the voltage at node bb which varies with the voltage at g l . As
`will be explained later, this biasing scheme is used to ensure
`the proper biasing of C1 and C2, which are implemented
`with MOSFET's. C2 is added to provide a memory of the
`bias voltage so as to serve as a reference for the final output
`signal. After 4 goes low, the selected row of pixels is first
`disconnected from the column lines and then reset. The reset
`- _ _
`operation follows exactly the same sequence of Reset, Shutter,
`and Row signals during array reset and exposure so as to
`obtain, to first order, the same charge injection. The selected
`pixels are then read out again. This produces a voltage at g l
`corresponding to the reset value at go in the pixel. The output
`signal is the final difference between Vcref and Vout in Fig. 6.
`Since a goal of this design is to use only components
`available in a standard digital CMOS technology, the capac-
`itors have been implemented with MOSFET' s biased in the
`inversion region. If the MOSFET-capacitors are to remain
`properly biased for different signal levels and process param-
`eters, a fixed bias voltage cannot be used at node bb in Fig. 6.
`Consequently, an adaptive biasing approach has been adopted.
`Fig. 8 is a circuit schematic of the actual implementation of
`the MOSFET-capacitors and the adaptive biasing. Node bb is
`biased to a voltage that varies with the voltage established at
`g l when 4 is high. The source follower B1 in Fig. 6 is formed
`by M21, M22, and 13. This circuit serves both as a buffer
`and a voltage level translator to ensure that C1 and C2 are
`biased in strong inversion.
`Without adaptive biasing, the bias voltage would have to
`be low enough so that C1 and C2 would remain in strong
`inversion when the voltage at g l is low, corresponding to
`low light intensity. However, this level of bias would not
`work properly for double sampling a pixel with strong light
`intensity. In such a case, the first readout of the double
`
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 12, DECEMBER 1996
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`a Pixel Column,
`
`Column
`Selected
`
`.....
`
`Analog Output
`
`Data Strobe
`
`Part of Bias Generator
`
`Readout
`
`Fig. 11. Column-scan shift register clocking
`
`Fig. 9. Column biasing implementation.
`
`Grouo of 16 Columns
`
`GrouD of 16 Columns
`
`Dark
`Column
`
`Output Buffer 7 0
`
`A: Column Readout Amplifier
`6: Group Buffer
`
`Dark Reference
`
`Internal p-diffusion resistors are included for the outputs
`
`to be connected as difference amplifier with external opamp
`
`Fig. 10.
`
`Buffering in the output signal path
`
`the bias line. By setting an appropriate value of IBB, the bias
`circuit establishes the voltage on column line, and therefore the
`drain current of M1 when M2 is on. IBB is provided by an
`on-chip bias current generator that is designed to be relatively
`insensitive to process variations.
`E. Buffering in the Output Signal Path
`If the column readout amplifier buffers, B2 and B3 in
`Fig. 6, were to drive the analog output buffer in Fig. 1 directly,
`their sizes and power consumption would need to be quite
`large because of the large loading capacitance of the signal
`path. To overcome this, intermediate buffering is used. The
`readout amplifiers are divided into groups of 16, each with an
`intermediate buffer that drives the output buffer as depicted
`in Fig. 10.
`The image sensor array also includes a dark reference col-
`umn in which the pixels’ photosensitive areas are completely
`covered by the Metal2 light shield. During testing, the dark
`reference was connected to an external difference amplifier
`and subtracted from outputs of the light-sensitive pixels. While
`an external difference amplifier was used for this prototype,
`the amplifier could be included on-chip in future designs.
`
`F. Minimizing Digital Noise Coupling
`Noise coupling from digital circuits into analog signal paths
`is a major concern in mixed-signal circuit design [14]. In the
`
`prototype imager, several design techniques have been used
`to minimize digital transitions during the settling of analog
`signals. First, the internal clock generator that provides the
`two-phase clocks for driving the scanning circuits is disabled
`until readout commences. This provides an environment that is
`almost free of digital noise during the array reset and exposure
`operations.
`Second, to minimize coupling into analog circuits via the
`substrate, the on-chip traces of the external clock are shielded
`with grounded metal lines. The shielding ground is fed directly
`off the chip to minimize coupling into the on-chip analog and
`digital grounds.
`Finally, in order to avoid a clock transition during the
`analog settling period, the digital shift register used to scan
`the columns is designed to shift at each edge of the external
`clock. Each pixel’s output is accessed for half the period of the
`external clock, which has a 50% duty cycle. The outputs of the
`odd and even columns are strobed on the positive and negative
`edges of the external clock, respectively, and the analog output
`rate is thus twice the external clock frequency. Circuit nodes
`in the shift register change state only on the transitions of
`the external clock, thus eliminating digital switching during
`analog signal settling period.
`Fig. 11 illustrates the analog output signal and the strobing
`of the output data relative to the external clock transitions.
`Fig. 12 shows the implementation of the column-scan shift
`register. Fig. 12(b) depicts a register cell, which is used to
`access two adjacent columns. Data is shifted into the cell at
`the In terminal and shifted out of the cell at the Out terminal.
`Bc, which is an output that feeds into the Ne input terminal
`of the preceding cell, disables the preceding column when the
`current column is selected. S1 and S 2 are the select signals
`for the two columns served by the register cell. As a digital
`“1” is shifted into the cell from the left, S1 goes high when
`41 goes high. When 41 falls, S1 goes low and S2 goes high,
`selecting the next column, as 42 transitions high. $1 and 42
`are generated from the external clock by an internal two-phase
`nonoverlapping clock generator.
`
`G. Layout
`The experimental image sensor has been fabricated in a
`1.2-pm CMOS technology. A die photograph of this circuit is
`shown in Fig. 13. The digital row-scan shift register and array
`
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`AW AND WOOLEY: A 128 X 128-PIXEL STANDARD-CMOS IMAGE SENSOR
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`I
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`1
`
`I
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`In
`
`out
`
`Fig. 13. Chip micrograph.
`
`1000 L
`
`. . . . . ...,
`
`. . . . . ....
`
`. . . . . . ..,
`
`. . . . . ..?
`
`(c)
`Fig. 12. Column-scan shift register design.
`
`drivers are located on the left of the pixel array, while the
`column readout amplifiers are just above the digital column-
`scan shift register at the bottom. The central control logic unit
`and the analog output buffers are located in the lower left
`comer of the photo. The size of the chip is 4.6 mm x 4.2
`mm.
`Care was taken in both the on-chip interconnect routing and
`the packaging to minimize the coupling of digital switching
`noise into the analog circuits via the supplies and substrate.
`Separate bond pads are used for the analog and digital supplies.
`A ring of substrate contacts around the periphery of the chip is
`connected to dedicated substrate bias pins. Multiple package
`pins and bond pads are used for all supplies and Vreset to
`reduce the parasitic inductance of the bond wires and package
`traces. The test chips were packaged in 44-pin J-lead ceramic
`chip carriers.
`
`IV . EXPERIMENTAL RESULTS
`Typical measured photoelectric conversion characteristics
`are shown in Fig. 14. Two sets of measurements were made:
`one at a shutter speed of 1/60 second, the other at U200
`second. The two curves clearly demonstrate the proportionally
`shortened integration time at the higher shutter speed. The
`saturation voltage is 470 mV, and the rms random noise in
`the dark was measured to be 2.6 mV. Thus, the peak output
`
`-
`
`Random Noise Level (rms)
`
`Optical Dynamic Range
`' " ~ " " ' ' ~ " " " '
`'
`' '
`
`1
`
`Fig. 14. Photoelectric conversion characteristics.
`
`t
`. ""-
`
`' ~ ~ ~ ~ '
`
`
`
`signal-to-noise ratio is 45 dB. The optical dynamic range is
`56 dB. It is apparent that the photosensitivity of the pixel
`is low. It is believed that the vertical PNP antiblooming
`structure degrades the sensitivity because some portion of the
`photocurrent actually flows to the n-welllp-substrate junction
`instead of the photodiode. Also, the output random noise
`voltage is relatively high. A major noise source is the switching
`noise that couples into the VDD and !Ireset buses in the pixel
`array when the entire array is being reset.
`Fig. 15 shows a series of reproduced images of a stationary
`gray scale picture. These images were taken under the same
`lighting conditions but at different shutter speeds. From the
`reproduced images it is apparent that the fixed pattern noise
`(FPN) in bright scenes is substantial and is dominated by
`column-to-column mismatch. For a uniformly bright scene,
`the rms FPN among pixels in a given column was measured
`to be 1.1% of the saturation voltage, whereas the intercolumn
`FPN is 4%. The corresponding figures for a uniformly dark
`scene are lower; the intracolumn FPN in the dark is only 0.3%,
`while the intercolumn FPN is 2.6%.
`
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`520
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`- Intercolumn
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`Intracolumn: 5.1 mV
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`420
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`0
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`32
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`64
`RowIColumn
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`96
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`128
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`Fig. 16.
`Intercolumn and intracolumn fixed pattern noise for a uniformly
`bright scene.
`
`Gain nonuniformity also contributes to the intercolumn
`FPN in a uniformly bright scene. In this case, the nonuni-
`formity is largely the result of component mismatch in the
`column biasing and column readout amplifier circuits, and
`is more pronounced. Threshold voltage and transconductance
`mismatches among input common gate transistors, M13, in
`the column amplifiers result in nonuniformity in the colNmn
`lines bias voltages. Because the pixel transconductance buffer
`is biased in the linear region by the voltage on the column line,
`nonuniformity in the column bias voltage directly influences
`the transconductance gain. Mismatches also exist among the
`transimpedances of M11 in the column readout amplifiers.
`The two sources for this are variation in the current sources
`I1 and 12, which produces nonuniformity in the bias current
`for M11, and mismatches in the characteristics of M11. The
`intercolumn FPN plot in Fig. 16 clearly exhibits a gradient that
`can be attributed to a process gradient. The FPN is relatively
`high compared to that of imagers such as that reported in
`[13] because of the small transistor sizes used in this design.
`For example, transistor M11 and the transistors used to
`implement I1 and I2 in the column readout amplifier measure
`9.6 pm/2.4 pm, 4.8 pm/3.6 pm, and 4.2 pm/3.6 pm, respec-
`tively. The FPN should be significantly reduced by increasing
`the size of these devices to improve device matching.
`Fig. 17 shows typical measured intercolumn and intracol-
`umn FPN plots for a uniformly dark scene. The intercolumn
`plot shows the average output voltage of each column, while
`the intracolumn plot shows the output voltage of each pixel
`in a typical column. The horizontal axis indicates the column
`position for the intercolumn FPN plot and the row position
`of the pixels for the intracolumn FPN plot. The intracolumn
`FPN is small, indicating that correlated double sampling is
`effective in cancelling the offset due to mismatches in the
`pixel characteristics.
`Fig. 18 shows the “dark” intercolumn FPN plot obtained
`with a column scan rate of 5 MHz, instead of the 10 MHz used
`to obtain all of the other experimental data. The intercolumn
`FPN reduces to 1.2% at the lower column scan rate. The
`higher intercolumn FPN for a uniformly dark scene at 10 MHz
`column scan rate can thus be attributed to inadequate settling
`
`(c)
`Fig. 15.
`Reproduced images of a gray scale stationary picture at different
`shutter speeds, but with the same lighting conditions and lens aperture.
`
`Fig. 16 shows typical measured intercolumn and intracol-
`umn FPN plots for a uniformly bright scene. The intercolumn
`plot displays the average output voltage measured for each
`column in an array, while the intracolumn plot shows the
`output voltage of each pixel in a typical column. The horizontal
`axis indicates the column position for the intercolumn FPN
`plot and the row position of the pixels for the intracolumn FPN
`plot. The intracolumn FPN was determined to be the result of
`nonuniformity in the gain from node go in the pixel to node
`g l in the column readout amplifier. It is apparent from the
`data in Fig. 16 that the gain nonuniformity is a consequence
`of both process gradients and random variation in component
`parameters. A small amount of the FPN can be attributed
`to nonuniformity in the photogeneration characteristics of the
`photodiodes. However, this should be relatively small because
`of the relatively large size of the photodiodes.
`
`

`
`AW AND WOOLEY: A 128 X 128-PIXEL STANDARD-CMOS IMAGE SENSOR
`
`1929
`
`40
`
`20
`
`1
`
`. lntracolumn I
`
`I
`
`F
`E
`v ”
`g
`
`o
`
`0 g .,
`U -20 ’
`
`
`
`’ I StandardDeviation: ’ 1
`
`Intercolumn: 12.0 mV
`Intracolumn: 1.5 mV
`
`32
`
`64
`
`96
`
`128
`
`RowIColumn
`
`-40
`
`0
`
`Fig. 17. Intercolumn and intracolumn fixed pattern noise for a uniformly
`dark scene.
`
`40 I
`
`1
`
`20
`
`a
`
`-20
`
`I
`
`Standard Deviation: 5.5 mV
`
`-40
`
`0
`
`32
`
`64
`
`Column
`
`96
`
`128
`
`Fig. 18.
`Intercolumn fixed pattem noise for a uniformly dark scene, mea-
`sured at column scan rate of 5 MHz. The horizontal lines indicate the grouping
`of the columns.
`
`time. A close look at Fig. 18 reveals that the FPN exhibits a
`pattem that correlates with the grouping of the columns shown
`in Fig. 10. This points to a contribution from the offsets of the
`intermediate group buffers. Variations within each group are
`probably the result of offsets in the column readout amplifier
`buffers.
`Fig. 19 shows the reproduced images of a rotating picture
`taken at two different shutter speeds. The object was rotating
`at approximately 160 rpm. The center of rotation was located
`beyond the top of the images. Image (a) was taken at a shutter
`speed of 1/60 second, resulting in a blurred picture. The image
`in (b) is clear and sharp, having been taken at a shutter speed
`of 1/1000 second. The lens aperture was wider for the higher
`shutter speed in order to achieve the correct exposure.
`Fig. 20 demonstrates the effectiveness of the image sensor’s
`antiblooming control. A transparency with two black stripes
`was placed in front of a 60 W light bulb at about 3 feet from
`the image sensor. The shutter speed was 1/60 second with the
`lens aperture set at f5.6. There is very little blooming. Only
`at the light bulb, where the light intensity is highest, is there
`a noticeable smearing of the stripe edges.
`Table I summarizes the performance of the image sensor
`prototype. Although the test setup only allows a shutter speed
`range of 1/20 s to
`s, it is estimated that an exposure time
`
`(b)
`Fig. 19. Reproduced images of a rotating picture at two different shutter
`speeds.
`
`Reproduced images showing the effectiveness of antiblooming
`Fig. 20.
`suppression.
`
`of up to 20 s can easily be achieved. The longest exposure time
`is limited by dark current that charges up nodes p d and g0
`in the pixels, thu