EXHIBIT 1043
`
`R. FORCHHEIMER, K. CHEN, C. SVENYSSOR and A. ASYTROM,
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`“Single-Chip Image Sensors with a Digital Processor Array,” Journal of VLSI
`
`signal processing systems for signal, image and video technology, April 1993
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`Vol. 5, Issue 2, pp. 121-131
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`TRW Automotive U.S. LLC: EXHIBIT 1043
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NUMBER 8,599,001
`IPR2015-00436
`
`

`
`Journal of' VLSI Signal Proce.-.:;ing, S, 121- 131 ( 1993)
`© 1993 Kluwer Academic Publishers, J3osron. ~1anufacwrcd in The Ncthctlands..
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`Single-Chip Image Sensors With a Digital Processor Array
`
`ROBERT FORCHHEIMER
`Dep<111menr of Electrical Engf,tetring, Li11kiif,tng Unlw~rsfl)~ SS8J 8J, linkqpl11g. S\t.>t:dei1
`
`KEPING CHEN, CHRISTER SVENSSON AND ANDERS ODMARK
`LSI Det ign Cett1tr, I PM, Unkoping Unh>crsiry, SS8/ 8J. LJnkQJ)ing, $l\>tden
`
`Rece;vcd Moy 7. 1991: Revis<d May 26. 1992.
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`Abstract. Thearchiteccures, implementation and applications of two smart sensors, LAPP and PASIC. are described.
`The basic idea of these two designs is to integrate an image sensor array with a digital processor array in a single
`chip. TI1e integrated camera-and-processor eliminates the bottleneck of sequential image read-out that characteri7,es
`conventional systems. They provide fast, compac-t and economic solutions for tasks such as industrial inspection,
`optical character recognition and robot vision.
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`1. Introduction
`
`Embedding of parallel prooossors in a sensing chip, a
`smart vision sensor, is an emerg.ing area of image sen~
`sor development. Smart sensors will play a significant
`role in industrial applications. However, commercially
`3V'Jilable image sensors today are developed mainly for
`television. Such sensors ha,•e excellent sensitivity, high
`resolution, can handle colors and have excellent relia(cid:173)
`bility. Their pixel read-out architecture, fixed frame rate
`and fixed resolution have a number of drawbacks for
`many .industrial applications. The pixel-by-pixel archi(cid:173)
`tecture limits the speed and flexible use of the sensor
`information.
`High speed image processing can be achieved by
`line-by-line or frame-by-frame parallel processing. A
`single chip solution is necessary, otherwise a lru:ge num(cid:173)
`ber of pad.s will be needed in a line-by-line or frome(cid:173)
`b)•frome parallel image processor architecture. It is
`therefore desirable to incorporate the sensor array and
`the processor array on a single chip. This will provide
`a mechanism to concurrently perform computations
`previously intractable in real-time. The continuous pro(cid:173)
`gress of VLSI technology bas provided this opportunity.
`Some excellent work on photo-sensor arrays with
`analog processing inspired by biological retinas has
`been performed by Carver Mead [I) . The basic idea
`is to include a simple and dedicated analog signal proc(cid:173)
`essor for each sensor element in a single chip. This
`frame-by-frame analog signal processing provides very
`high speed. Yang and Chiang have recently designed a
`
`CCD image sensor array integrated with an linear array
`of CCD analog processors to perform a simple edge
`detection algorithm line-by-line in real time [2J. By
`utWzing the ability of CCD technology that can sum
`and split charge packages, parallel convolutions with
`fixed coefficientS are realized. However, these analog
`implementations arc too specialized and do not have
`the flexibility to be tailored for different applications.
`An altemat.ive approach is to integrate a sensor array
`with a programmable digital processor array oa a single
`chip. An experimental chip has been developed using
`3-0 technology [3). The device consists of a 5-by-5
`photo sensor array, a 5-by-5 2-bit CMOS AID con,<erter
`array, a 2-bit ALU array and shift registers arranged
`in a 3-layer struccure. The size of a pixel is 1.05 x
`1.05 mm2 . Signals from the photo diodes are trans(cid:173)
`ferred to the 2-bit ND converters. The quantized digital
`data is then transferred to the third layer, the ALUs.
`Finally, the processed signals are read out with shift
`registers. The image sensing, quantization and data
`processing of all pixels are operated simultaneously
`frame-by-frame. This frame-by-frame architecture
`allows extremely high speed image processing. How(cid:173)
`ever, the low area resolution, the low signal amplitude
`resolution and the very higll 1/0 bandwidth demands
`in this design are severly limiting the applications.
`This article will describe the architcc-ture, imple(cid:173)
`mentations and applications of 1wo smart sensors,
`LAPP and PASIC. They provide fast, compact and eco(cid:173)
`nomic solutions to tasks such as industrial inspection,
`optical character recognition and robot vision. Section
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`1043-001
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`

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`128bit
`internal bus
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`~~~~~~~~~~..,
`
`PHOTO OIOOE ARRAY (PO)
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`RO
`
`R\3
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`122
`
`Forchheimer, Che11, Sve11sstm a11d Odmark
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`2 will describe the LAPP system which is designed for
`fast binary image processing. A sman sensor, PASJC,
`whose architecture is an expanded version of LAPP to
`an enhanced bit-serial processor array with a resolution
`progranunable AID convener al'ray, is described in Sec(cid:173)
`tion 3. Sectio,ts 4 and 5 discuss their similarities and
`differences. Finally, further development and trends
`will be discussed in Section 6.
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`Z. LAPP - Linear Array Picture Processor
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`The first attempt of integrating an image sensor array
`and a processor array on a single chip was made several
`years ago at Linkiiping University, LAPP, [4], [5]. Fig(cid:173)
`ure l shows the photograph of the LAPPI 100, which
`is a commercial version and having 128 photo sensor
`elements, 128 threshold units for digitization and a 128
`bit-serial processor in a single chip. The chip size is
`5 x 7 mm1 using a 3µm CMOS technology.
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`2.1. LAPP Architecture
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`TheblockdiagramofLAPP is shown in figure 2. The
`linear photo diode array (PD) uses threshold circuitry
`to commun.icate image information to a 128 bit internal
`bus. The register array (RO-RJ3) stores images and in(cid:173)
`termediate results. The computing unil~ GLU, NLU,
`PLU perform the image operations. Results are passed
`on to the accumulator. From there the result is either
`stored in a register, or used as the second operand in
`two-operand instructions.
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`Pig. 2. The block diag:nlm of the LAPP.
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`2./. I. Photo-Diode and Comp<m110, Array (PD). The
`photosensitive diode array c-0nsists of a Ii.near set of
`diodes, pre-charge transistors and comparatOrs as shown
`in figure 3. The active surface of each of the diodes is
`35 X 35 µm2 and the space between them is 50µm.
`The diode is first re\'ersely biased by pulsing the pre(cid:173)
`charge transistor. The charged diode will then discharge
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`Pig. J, LAPP chip photo-micrograph.
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`10
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`1043-002