EXHIBIT 1038
`
`U.S. PATENT NO. 5,043,820 TO WYLES
`
`(“the ‘820 Patent” or “WYLES”)
`
`TRW Automotive U.S. LLC: EXHIBIT 1038
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NUMBER 8,599,001
`IPR2015-00436
`
`

`
`United States Patent 1191
`Wyles et al.
`
`[11] Patent Number:
`[45] Date of Patent:
`
`5,043,820
`Aug. 27, 1991
`
`[54] FOCAL PLANE ARRAY READOUT
`EMPLOYING ONE CAPACITIVE FEEDBACK
`TRANSIMPEDANCE AMPLIFIER FOR
`EACH COLUMN
`
`[75] Inventors:
`
`Richard H. Wyles, Cardiff; James L.
`Gates, Vista; Steven D. Gaalema,
`Encinitas, all of Calif.
`[73] Assignee: Hughes Aircraft Company, Los
`Angeles, Calif.
`[21] Appl.No.: 329,229
`[22] Filed:
`Mar. 27,1989
`
`[51] Int. Cl.5 . . . . . .
`
`. . . . . . . . . . . . . . . . . . . . . . . . . .. H04N 5/30
`
`[52] US. Cl. .......................... .. SSS/213.28; 250/208.l;
`358/212; 358/213.27
`[58] Field of Search .............. .. 250/208.l; 358/2l3.l2,
`358/212. 213.28, 213.27
`References Cited
`U.S. PATENT DOCUMENTS
`
`[56]
`
`3,852,714 12/1974 Carson ........................... .. 250/208.l
`
`. . . . 258/2l3.29
`$349,162 4/1976 Malueg . . . . .
`358/2l3.l5
`4,345,148 8/1982 Pines et al. ........ ..
`358/212
`4,529,886 7/1985 Yokayama et al. .
`307/490
`4,786,831 11/1988 Morse et al. ,
`4.814.629 3/1989 Arnold .............................. .. 358/105
`
`OTHER PUBLICATIONS
`
`Design Consideration and Performance of a new MOS
`Imaging Device, I-Iaruhisa Ando. et al, IEEE Transac
`tions on Electron Devices. vol. ED-32, No. 8, pp.
`1484-1489.
`A Solid State Color Video Camera with a Horizontal
`Readout MOS Imager, Noda et a], IEEE Transactions
`
`on Consumer Electronics, vol. CE-32, No. 3. pp.
`329-335.
`Primary Examiner-Joseph A. Orsino
`Assistant Examiner—] ill Jackson
`Attorney, Agent, or F1'rm—W. C. Schubert; W. K.
`Denson-Low
`ABSTRACT
`[57]
`A readout circuit for use with a focal plane array that
`employs a single transistor in each unit cell and a single
`capacitive feedback transimpedance amplifier to prO
`cess the outputs of each column of detector elements of
`the array. The capacitive feedback transimpedance
`ampli?ers extract the signals associated with the pixels
`along a particular row of the array. The present inven
`tion permits high performance readouts to be con
`structed with very little circuitry in the unit cells. Only .
`a single minimum sized transistor switch is required in
`each unit cell to perform readout and reset functions for
`the array. In the disclosed embodiment. the readout
`circuit comprises an array of unit cells. each cell com
`prising a detector input circuit, a single transistor and a
`single charge storage capacitor. Row address circuits
`are coupled to the cells in each row of the array. A
`plurality of capacitive feedback transimpedance ampli- '
`fiers are coupled to the cells in each column of the
`array. The amplifiers process charge derived from the.
`detector elements and stored in the charge storage ca
`pacitor of each unit cell, Column multiplexing circuits
`multiplex the output signals provided by each of the
`amplifiers. Column address circuits are coupled to the
`column multiplexing circuits which couple output sig
`nals from each of the multiplexer circuits as the output
`from the readout circuit.
`
`15 Claims, 2 Drawing Sheets
`
`a
`
`UUTPUI
`
`1038-001
`
`

`
`U.S. Patent
`
`Aug. 27, 1991
`
`Sheet 1 of 2
`
`5,043,820
`
`OUTPUT
`
`1 038-002
`
`CIRCUIT
`
`DETECTOR
`INPUT
`
`1038-002
`
`

`
`US. Patent
`
`Aug. 27, 1991
`
`Sheet 2 of 2
`
`5,043,820
`
`1038-003
`
`

`
`1
`
`FOCAL PLANE ARRAY READOUT EMPLOYING
`.
`ONE CAPACITIVE FEEDBACK
`TRANSIMPEDANCE AMPLIFIER FOR EACH
`COLUMN
`
`5,043,820
`2
`proved input circuit performance in hybrid focal plane
`arrays.
`More speci?cally, in the disclosed embodiment, the
`present invention comprises a readout circuit for use
`with a focal plane array of detector elements. The read
`out circuit comprises an array of unit cells, each cell
`comprising a detector input circuit, a single transistor
`and a single charge storage capacitor. A plurality of
`row address circuits are individually coupled to the
`cells in a respective rows of the array. A plurality of
`capacitive feedback transimpedance ampli?ers are indi
`vidually coupled to the cells in a respective columns of
`the array. The ampli?ers process charge derived from
`the detector elements and stored in the charge storage
`capacitor of each unit cell.
`A plurality of column multiplexing circuits are cou
`pled to respective ones of the capacitive feedback tran
`simpedance ampli?ers which multiplex the output sig
`nals provided by each of the ampli?ers. A plurality of
`column address circuits are respectively coupled to the
`column multiplexing circuits which couple output sig
`nals from each of the multiplexer circuits as the output
`from the readout circuit.
`
`25
`
`35
`
`BRIEF DESCRIPTION OF THE DRAWING
`The various features and advantages of the present
`invention may be more readily understood with refer
`ence to the following detailed description taken in con
`junction with the accompanying drawings. wherein like
`reference numerals designate like structural elements,
`and in which:
`-
`FIG. 1a shows a block diagram of a focal plane array
`readout circuit in accordance with the principles of the
`present invention;
`FIG. 1b shows a diagram ofa unit cell of the readout
`circuit of FIG. 1a; and
`FIG. 2 shows a detailed diagram ofa capacitive feed
`back transimpedance ampli?er and unit cell employed
`in a focal plane array readout circuit in accordance with
`the principles of the present invention.
`
`BACKGROUND
`The present invention generally relates to focal plane
`arrays and more particularly to a focal plane array read
`out that employs a single capacitive feedback tran
`simpedance ampli?er for each column in the focal plane
`array.
`Existing high performance direct readout devices for
`focal plane arrays generally require several transistors
`in each unit cell, a unit cell being the circuit that stores
`charge from the detector elements of the focal plane
`array. Typically the number of transistors employed in
`the unit cell is four. Consequently, it is generally not
`possible to build monolithic focal plane arrays with
`small unit cells and high ?ll factors, rrreaning the ratio of
`detector area to total unit cell area. For hybrid focal
`plane arrays, input circuit performance is generally
`compromised using such conventional circuits. Charge
`coupled device readouts also require large amounts of
`space in the unit cell, and therefore have similar draw
`backs.
`Readout devices have been developed which require
`only two transistors in the unit cell. Such devices are
`30
`described in a publication entitled “A Solid State Color
`Video Camera with a Horizontal Readout MOS
`Imager,” authored by Masaru Noda, et al, published in
`IEEE Transactions on consumer Electronics, Vol. CE
`32, No. 3, August 1986. In addition to requiring more
`space in the unit cell this approach requires a very high
`speed ampli?er with low noise, a combination that is
`very difficult to achieve in practice.
`Single transistor unit cells have been used in the past
`for reading out photodiode arrays. However, the re
`ported devices have employed signal extraction cir
`cuitry, such as feedback enhanced direct injection cir
`cuits, whose noise performance is somewhat less than
`desirable. Typical of such single transistor unit cells are
`those referenced in “Design Consideration and Perfor
`mance of a New MOS Imaging Device,” authored by
`Haruhisa Ando, et al, in IEEE Transactions on Elec
`tron Devices, Vol ED-32, No. 8, August 1985.
`‘SUMMARY OF THE INVENTION
`In order to overcome some of the limitations of con
`ventional focal plane readout devices, including rela
`tively large unit cells and less than desirable circuit
`performance, the present invention provides for a read
`out device that employs a single transistor in each unit
`cell. In addition, a single capacitive feedback tran
`simpedance ampli?er is employed to process the out
`puts of each column of detector elements of the array.
`The capacitive feedback transimpedance ampli?ers
`extract the signals associated with the pixels along a
`particular row of the array.
`The present invention permits high performance
`readouts to be constructed with very little circuitry in
`the unit cells. Only a single minimum sized transistor
`switch is required in each unit cell to perform the read
`out and reset functions for the array. The remaining
`space in the unit cell is available to achieve high detec
`tor ?ll factors in monolithic focal plane arrays, or im
`
`40
`
`DETAILED DESCRIPTION
`Referring to FIG. la, a block diagram ofa focal plane
`array readout circuit 10 in accordance with the princi
`ples of the_present invention is shown. The readout
`circuit 10 comprises an array 11 of unit cells 12, shown
`in FIG. 10 as a 4X4 array of cells. Row address cir
`cuitry 13 comprising a plurality of row (Y) address
`‘ circuits 13a-13d, are coupled to each of the cells 11in a
`particular row of the array 11. The speci?c interconnec
`tion to the cells 12 will be described with reference to
`FIG. 1b.
`With reference to FIG. 1b, a diagram ofa unit cell of
`the readout device 10 of FIG. 1a is shown. The unit cell
`12 comprises a detector input circuit 21, whose input is
`coupled to a detector element in the focal plane array,
`and whose output is coupled through a unit cell transis
`tor 22 which operatesas a switch. A charge storage
`capacitor 23 is coupled from a point between the detec
`tor input circuit 21 and the transistor 22 and ground.
`The gate of the transistor 22 is coupled to a selected row
`address circuit 13a~13d employed to address the row in
`which the particular cell 12 resides along a horizontal
`signal line 25. The drain of the transistor 22 is coupled
`to a vertical signal line 24 which couples charge out of
`the unit cell 12.
`_
`Referring again to FIG. la, the vertical signal lines of
`each column of the array are respectively coupled to
`
`45
`
`55
`
`65
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`1038-004
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`

`
`Item
`
`Anode of detector 3i
`
`Left diffusion of
`transistor 32
`Bottom diffusion of
`transistor 34
`Bottom diffusion of
`transistor 41
`Gate of transistor 42
`Top diffusion of
`transistor 44
`Top diffusion of
`transistor 43
`Bottom plate of
`capacitor 45
`Top diffusion of
`transistor 52
`Top diffusion of
`transistor 63
`Bottom diffusion of
`transistor ol
`Bottom diffusion of
`transistor 62
`Bias applied above
`resistor 64
`Bottom plate of
`capacitor 72
`Top diffusion of
`transistor 81
`
`20
`
`25
`
`5,043,820
`3
`separate capacitive feedback transimpedance ampli?ers
`15a—15d. Each capacitive feedback transimpedance
`ampli?er 15a-15d is coupled to the unit cells in a partic
`ular column of the array. Outputs of each of the capaci
`tive feedback transimpedance ampli?ers 15a-15d are
`coupled to column multiplexing circuits 160-16d. Ca
`pacitive feedback transimpedance ampli?ers 15a-15d
`are generally well-known in the art, and reference is
`made to US. Pat. No. 4,786,831, entitled “Integrating
`Capacitively Coupled Transimpedance Ampli?ers,”
`issued to Morse et al, which illustrates one such tran
`simpedance ampli?er.
`Column address circuits 17a-17d are respectively
`coupled to each of the column multiplexing circuits
`16a-16d and are employed to address each of the col
`umn multiplexing circuits 16a-16a' in order to read out
`the signals therefrom as the output signals from the
`readout circuit 10. Also shown in FIG. 1a is an output
`driver 19 that is coupled to the column multiplexing
`circuits 16a-16d in order to drive the output signal from
`the readout circuit 10. This output driver 19 may also be
`used to provide an ampli?ed output signal, if desired.
`However, in some applications, this output driver 19
`may not be required, and hence it is an optional circuit.
`Referring to FIG. 2, a detailed diagram of a capaci
`tive feedback transimpedance ampli?er 15a and unit cell
`12 employed in a focal plane array readout circuit 10 in
`accordance with the principles of the present invention
`is shown. The circuit implementation is relatively
`straight forward, and as shown in the drawings, com
`prises the following subcircuits. The readout circuit 10
`comprises the unit cell 12, which includes a detector 31,
`which may be a Schottky detector or a mercury cad
`mium telluride detector, for example, whose output is
`coupled through the unit cell transistor 22.
`A detector reset transistor 32 and an optional charge
`injection circuit 30 comprising two transistors 33, 34
`and a capacitor 35 is coupled to the input of the capaci
`tive feedback transimpedance ampli?er 15a. The charge
`injection circuit 30 injects charge into the capacitive
`feedback transimpedance ampli?er 15a to adjust its
`operating point. The capacitive feedback transimped
`ance ampli?er 150 includes an ampli?er reset switch 38
`and feedback capacitor 39, and its primary ampli?er
`circuit 40 comprises four transistors 41, 42, 43, 44 and a
`capacitor 45. This ampli?er circuit 40 operates as a
`conventional inverting ampli?er with a dynamically
`bootstrapped load. The ampli?er circuit 40 is also one
`embodiment of many, which could be implemented to
`provide the desired ampli?cation functions.
`A clamp circuit 50 comprising coupling capacitor 51,
`and transistor 52 interfaces between the capacitive feed
`back transimpedance ampli?er 15a and a source fol
`lower buffer circuit 60 comprising three transistors 61,
`62, 63 and a resistor 64. The clamp circuit 50 reduces
`reset noise and eliminates DC nonuniformities in the
`capacitive feedback transimpedance ampli?er 15a. The
`buffer circuit 60 isolates the clamp capacitor 51 from
`capacitor 72 to prevent interaction that would result in
`a gain reduction in that portion of the readout circuit 10.
`The output of the buffer circuit 60 is coupled through
`a sample and hold circuit 70 comprising a transistor 71
`and a capacitor 72. The sample and hold circuit 70
`isolates the signal stored in capacitor 72 from the capac
`itive feedback transimpedance ampli?er 15a during
`column multiplexing operations. A column multiplexer
`circuit 160 comprises two transistors 81, 82. The output
`of the column multiplexer circuit 16a couples signals to
`
`4
`the output driver circuit 19 by way of output bus line
`26.
`For purposes of completeness, the following typical
`bias and clock voltages may be applied to the circuit of
`FIG. 2 as shown in the following Table l.
`TABLE 1
`Tvpical Bias and Clock Voltage (Volts)
`
`Bias
`
`Item
`
`Clock
`Low High
`
`Row select (gate
`of 22)
`Gate of 32
`
`Gate of 33
`
`Gate of 34
`
`Gate of 38
`Gate of 44
`
`Gate of 52
`
`Gate of 71
`
`Column select (gate
`of 82)
`
`0
`
`0
`
`O
`
`0
`
`O
`O
`
`0
`
`0
`
`0
`
`8
`
`8
`
`S
`
`8
`
`8
`8
`
`8
`
`S
`
`8
`
`0
`
`5
`
`1
`
`2
`
`3
`4
`
`8
`
`0
`
`4
`
`8
`
`4
`
`4
`
`8
`
`O
`
`S
`
`35
`
`40
`
`45
`
`50
`
`55
`
`65
`
`The operation cycle ofthe circuit described in FIGS.
`1 and 2 is as follows. Before a new row of unit cells 12
`in the array 11 is selected, all capacitive feedback tran
`simpedance ampli?ers 15 are reset using the reset tran
`sistor 38. This action puts the capacitive feedback tran
`simpedance ampli?ers Isa-15d into a mode in which
`they sense charge on their inputs. A new row of input
`cells 12 is then selected wherein the row address cir
`cuitry 13 generates a pulse which activates the new
`row. This pulse turns on the transistors 22 in each unit
`cell 12 in the selected row. The charge stored in the
`storage capacitor 23 in the unit cell 12, which comprises
`the integrated photocurrent from the detector element
`to which a unit cell 12 is coupled, is thus transferred to
`the vertical signal line 24.
`The respective capacitive feedback transimpedance
`ampli?er 15a—15d responds by producing an output
`signal which is proportional to the stored charge. Since
`there is a capacitive feedback transimpedance ampli?er
`15 associated with each column in the array 11, all
`columns are processed simultaneously, After the out
`puts of the capacitive feedback transimpedance ampli
`?er 15 have stabilized, the signal levels are then read
`out. The sample and hold circuit 70 is employed to
`isolate the signals from the capacitive feedback tran
`simpedance ampli?er 15 prior to the readout phase. The
`signals are read out using standard multiplexing tech
`niques. The column address circuitry 17 causes succes
`sive columns to be enabled and the signal from the
`column addressed at a particular instant is connected to
`the output bus line 26 and driven from the readout
`circuit 10 by the output stage 19.
`
`1038-005
`
`

`
`5,043,820
`
`5
`
`25
`
`5
`After the signal from each column has been read out,
`the unit cells 12 along the currently addressed row are
`reset using the reset transistor 32. This is done by simul
`taneously forcing all vertical signal lines 24 to a com
`mon reset voltage. Since the transistors 22 in the unit
`cells 12 along this row are still turned on, the charge
`storage capacitors 23 are reset to the voltage on the
`vertical signal line 24. The row enable pulse from the
`row address circuits 13 is then deactivated, leaving the
`charge storage capacitors 23 at the reset voltage. These
`capacitors 23 integrate photocurrent during the next
`frame period, until this row is again addressed.
`The operating cycle described above is then repeated
`for the next row. The capacitive feedback transimped
`ance ampli?ers 15 are reset. The next row of unit cells
`12 is activated, and the rest of the readout sequence is
`repeated.
`The circuit con?guration of FIG. 2 is only one em
`bodiment of many possible embodiments which realize
`the present invention. The circuit of FIG. 2 includes a
`variety of extra features that improve its performance.
`For example, an optional sample and hold and/or clamp
`and sample circuits, such as sample and hold circuit 70,
`is employed to minimize noise and nonuniformities.
`Bandwidth limiting may be employed to reduce noise.
`Precharging circuits, such as the optional charge injec
`tion circuit 30 is employed to reduce noise, control
`dynamic range, and allow analog nonuniformity com
`pensation. These and other techniques may be used to
`optimize the design of the capacitive feedback tran
`simpedance ampli?er 15 to meet the requirements of a
`speci?c application.
`Thus there has been described a new and improved
`focal plane array readout circuit which provides for the
`use of single transistor unit cells, and'for a single capaci
`tive feedback transimpedance ampli?er circuit for each
`column in the readout array. It is to be understood that
`the above-described embodiments are merely illustra
`tive of some of the many speci?c embodiments which
`represent applications of the principles of the present
`invention. Clearly, numerous and other arrangements
`can be readily devised by those skilled in the art without
`departing from the scope of the invention.
`What is claimed is:
`l. A focal plane array readout circuit for use with a
`45
`focal plane array having a predetermined number of
`rows and columns of detector elements, said readout
`circuit comprising:
`an array of unit cells, each cell comprising charge
`storage and transfer means for receiving and stor
`ing charge derived from the detector elements of
`the focal plane array;
`row address means coupled to each row of unit cells
`of the array;
`a plurality of capacitive feedback transimpedance
`ampli?ers, one capacitive feedback transimpedance
`ampli?er coupled to the cells in each column of
`unit cells of the array for processing charge stored
`in the charge storage and transfer means of the unit
`cells;
`column multiplexing means coupled to respective
`ones of the capacitive feedback transimpedance
`ampli?ers for multiplexing output signals provided
`thereby; and
`column address means coupled to the column multi
`plexing means for addressing each of the column
`multiplexing means and for coupling output signals
`provided thereby out of the readout circuit.
`
`65
`
`35
`
`40
`
`6
`2. The focal plane array readout circuit of claim 1
`which further comprises:
`charge injection means coupled to the input of each
`capacitive feedback transimpedance ampli?er.
`3. The focal plane array readout circuit of claim 1
`which further comprises:
`clamp circuit means coupled to the output of each
`capacitive feedback transimpedance ampli?er.
`4. The focal plane array readout circuit of claim 1
`which further comprises:
`buffer circuit means coupled to the output of each
`capacitive feedback transimpedance ampli?er.
`5. The focal plane array readout circuit of claim 4
`which further comprises:
`sample and hold circuit means coupled to the buffer
`circuit means.
`6. Focal plane array readout circuit for use with a
`focal plane array having a predetermined number of
`rows and columns of detector elements, said readout
`circuit comprising:
`an array of unit cells, each cell comprising a detector
`input circuit, a single transistor and a single charge
`storage capacitor;
`a plurality of row address circuits respectively cou
`pled to the cells in a selected row of the array;
`a plurality of capacitive feedback transimpedance
`ampli?ers equal to the number of columns of detec
`tor elements, each ampli?er respectively coupled
`to the cells in a selected column of the array for
`processing charge stored in the charge storage
`capacitor of each unit cell in parallel with the unit
`cells in the other columns;
`a plurality of column multiplexing circuits coupled to
`respective ones of the capacitive feedback Iran-
`simpedance ampli?ers for multiplexing output sig
`nals provided by each of the ampli?ers: and
`a plurality of column address circuits respectively
`coupled to the column multiplexing circuits for
`coupling output signals provided by each of the
`multiplexers as the focal plane array output from
`the readout circuit.
`7. The focal plane array readout circuit of claim 6
`which further comprises:
`charge injection means respectively coupled to the
`inputs of the plurality of capacitive feedback tran
`simpedance ampli?ers for injecting charge into the
`capacitive feedback transimpedance ampli?ers to
`adjust the operating point thereof.
`8. The focal plane array readout circuit of claim 6
`which further comprises:
`i
`_
`clamp circuit means respectively coupled to the out
`puts of the plurality of capacitive feedback tran
`simpedance ampli?ers for reducing reset noise and
`eliminating DC nonuniformities therein.
`9. The focal plane array readout circuit of claim 6
`which further comprises:
`buffer circuit means respectively coupled to the out
`puts of the plurality of capacitive feedback tran
`simpedance ampli?ers for preventing gain reduc
`tion therein.
`10. The focal plane array readout circuit of claim 9
`which further comprises:
`sample and hold circuit means respectively coupled
`to each of the buffer circuit means for isolating the
`respective capacitive feedback transimpedance
`ampli?ers during column multiplexing operations.
`11. Focal plane array readout circuit for use with a
`focal plane array having a predetermined number of
`
`1038-006
`
`

`
`5,043,820
`7
`rows and columns of detector elements, said readout
`circuit comprising:
`an array of unit cells, each cell comprising a detector
`input circuit, a single transistor and a single charge
`‘storage capacitance;
`a plurality of row address circuits respectively cou
`pled to respective gates of the transistors in a se
`lected row of unit cells of the array;
`a plurality of capacitive feedback transimpedance
`ampli?ers equal to the number of columns of detec
`tor elements, each capacitive feedback transimped
`ance ampli?er coupled to the transistors in a se
`lected column of unit cells of the array for process—
`ing charge stored in the charge storage capacitance
`of each unit cell ofa selected row of the unit cells
`in parallel;
`a plurality of column multiplexing circuits coupled to
`respective ones of the capacitive feedback tran
`simpedance ampli?ers for multiplexing output sig
`nals provided by each of the ampli?ers; and
`a plurality of column address circuits respectively
`coupled to the column multiplexing circuits for
`addressing each of the plurality of column multi
`
`8
`plexing circuits for coupling output signals pro
`vided by each of the multiplexer circuits as the
`focal plane array output from the readout circuit.
`12. The focal plane array readout circuit of claim 11
`which further comprises:
`a plurality of charge injection circuits respectively
`coupled to the inputs of each of the capacitive
`feedback transimpedance ampli?ers.
`13. The focal plane array readout circuit of claim 11
`which further comprises:
`a plurality of clamp circuits respectively coupled to
`the output of each of the capacitive feedback tran
`simpedance ampli?ers.
`14. The focal plane array readout circuit of claim 11
`which further comprises:
`a plurality of buffer circuits respectively coupled to
`the output of each of the capacitive feedback tran
`simpedance ampli?ers.
`15. The focal plane array readout circuit of claim 14
`which further comprises:
`a plurality of sample and hold circuits respectively
`coupled to the buffer circuits.
`*
`*
`Ik
`*
`*
`
`20
`
`25
`
`35
`
`45
`
`55
`
`65
`
`1038-007