EXHIBIT 1031
`
`U.S. PATENT NO. 4,000,418 TO WALDRON
`
`(“WALDRON”)
`
`
`
`
`
`
`
`TRW Automotive U.S. LLC: EXHIBIT 1031
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NUMBER 8,599,001
`IPR2015-00436
`
`

`
`llnited States Patent
`Waldron et al.
`
`[19]
`
`[54] APPARATUS FOR STORING AND
`RETRIEVING ANALOG AND DIGITAL
`SIGNALS
`
`[75]
`
`Inventors: Wesley K. Waldron, Scotia; Charles
`W. Eichellberger, Schenectady, both
`of N.Y.
`
`[73] Assignee: General Electric Company,
`Schenectady, N.Y.
`Nov. 26, 1975
`
`[22] Filed:
`
`[21] Appl. No.: 635,702
`
`[52] U.S. Cl. .......................... .. 250/211 J; 307/304;
`357/24; 357/32
`Int. Cl.” ....................................... .. 1101.] 39/12
`[51]
`[58] Field of Search .......... .. 250/211 R, 211 J, 578;
`307/304; 357/24, 30, 32; 340/166 R
`References Cited
`UNITED STATES PATENTS
`
`[56]
`
`.................. .. 307/304
`Engeler et al.
`8/1975
`3,898,685
`8/1975 Hasegawa ct al.
`................. .. 357/32
`3,900,883
`Primary Examiner-——David C. Nelms
`Attorney, Agent, or Firm—.lulius J. Zaskalicky; Joseph
`T. Cohen; Jerome C. Squillaro
`
`[11]
`
`[45]
`
`4,000,418
`
`Dec. 28, 1976
`
`[57]
`
`ABSTRACT
`
`An array of charge storage devices each including a
`pair of closely coupled conductor—insulator—semicon—
`ductor cells, one a row line connected cell and the
`other a column line connect.ed cell, is provided on a
`common semiconductor substrate. The potential well
`associated with the row connected cell is deeper than
`the potential well associated with the column con-
`nected cell. Read out of charge stored in a row of de-
`vices is accomplished by lowering the absolute poten-
`tial of the row line to a first level to cause the charges
`stored in the row connected cells to be transferred to
`column connected cells of the row. The voltage on
`each of the column lines is then lowered in absolute
`magnitude in sequence to a second level to cause the
`charges to be transferred from the column connected
`cells to the row connected cells. The charge induced on
`the row line during transfer of charge from the column
`connected cells to the row connected cells is sensed to
`
`provide non-destructive readout of the stored charges.
`
`14 Claims, 33 Drawing Figures
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`Dec. 28, 1976
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`US. Patent
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`Dec. 28, 1976
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`Dec. 28, 1976
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`US. Patent
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`Dec. 28, 1976
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`Sheet 6 _of 6
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`I
`
`4,000,418
`
`2
`
`APPARATUS FOR STORING AND RETRIEVING
`ANALOG AND DIGITAL SIGNALS
`
`5
`
`The present invention relates in general to apparatus
`including devices and circuits therefor for storing and
`retrieving analog and digital signals, and in particular to
`such apparatus wherein the information is stored in the
`form localized charges in a semiconductor substrate.
`This application relates to improvements in the appa-
`ratus of U.S. Pat. No. 3,805,062 and patent application
`Ser. No. 554,155, filed Feb. 28, 1975, both of which
`are assigned to the assignee of the present application
`and both of which are incorporated herein be reference
`thereto.
`
`An object of the present invention is to provide im-
`provements in apparatus including an array of charge
`storage devices on a common semiconductor substrate
`for storage and retrieval of analog and digital signals
`which may be initially obtained either in the form of a
`pattern of radiation or in the form of electrical signals.
`Another ojbect of the present invention is to provide
`simple apparatus including an ari'ay of charge storage
`devices on a common semiconductor substrate for
`non-destructive read out of localized charges repre-
`senting analog and digital signals.
`,
`A further object of the present invention is to provide
`apparatus including an array of charge storage devices
`on a common semiconductor substrate for read out of
`localized charges representing analog signals which is 30
`relatively insensitive to variations in the geometric
`organization of the devices of the-array.
`In carrying out the invention in one illustrative em-
`bodiment thereof there is provided a substrate of semi-
`conductor material of one conductivity type having a
`major surface. A plurality of first conductive plates are
`provided, each overlying and in insulated relationship
`to the major surface and forming a first conductor-
`insulator—semicondu.ctor capacitor with the substrate.
`A plurality of second conductive plates are provided,
`each adjacent a respective first conductive plate to
`form a plurality of pairs of plates, the pairs of plates
`being arranged in a matrix of rows and columns, each
`of the second conductive plates overlying and in insu-
`lated relationship to the major surface and forming a
`second conductor-insulator-semiconductor capacitor
`with the substrate. Each second conductor-insulator-
`semiconductor capacitor is coupled to a respective first
`conductor-insulator-semiconductor capacitor so as to
`permit the transfer of stored charge between them. A
`plurality of row conductor lines are provided, the first
`conductive plates in each of the rows are connected to
`a respective row conductor line. A plurality of column
`conductor lines are provided, the second conductive
`plates in each of the columns are connected to a re-
`spective column conductor line.
`A first voltage means provides a first voltage between
`the row conductor lines and the substrate to deplete
`respective first portions of the substrate lying thereun-
`der of majority charge‘ carriers and providespan abso-
`lute potential of a first value therein. A second voltage
`means provides a second voltage between the column
`conductor lines and the substrate to deplete respective '
`second portions of the substrate lying thereunder of
`majority charge carriers and provides an absolute po- 65
`tential of a second value therein. Preferably, the second
`value of potential
`is substantially less than the first
`value of potential. Means are provided for storing
`
`charge in the first portions of the substrate. First means
`are provided for reducing the first voltage on each of
`the row conductor lines in sequence to a first level
`during a respective first period of time to cause the first
`portions of the substrate associated with the respective
`row line to be reduced in absolute potential to a third
`value less than the second value whereby charge stored
`in the first portions transfers into respective second
`portions of the substrate associated with the respective
`row line. Second means are provided for reducing in
`sequence the second voltage: on each of the column
`conductor lines to a second l.‘evel to cause the second
`
`portions of the substrate to be reduced in potential to a
`fourth value less than the third value whereby charge
`stored in each of the second portions transfers into the
`first portions.
`Means are provided for sensing in sequence each of
`the signals induced on the respective row line during
`the transfer of charge from the second portions to the
`first portions of the substrate associated with the re-
`spective row line.
`The novel features which are believed to be charac-
`
`teristic of the present invention are set forth with par-
`ticularity in the appended claims. The invention itself,
`both as to its organization and method of operation,
`together with further objects: and advantages thereof
`may best be understood by reference to the following
`description taken in connection with the accompanying
`drawings wherein:
`FIG. 1 is a plan view of an array or assembly of
`charge storage devices incorporated in the apparatus of
`the present invention shown in FIG. 5.
`FIG. 2 is a sectional view of the assembly of FIG. 1
`taken along section lines 2——2 of FIG. 1.
`FIG. 3 is a sectional view of the assembly of FIG. 1
`taken along section lines 3-3 of FIG. 1.
`FIG. 4 is a sectional View of the assembly of FIG. 1
`taken along section lines 4-4 of FIG. 1.
`FIG. 5 is a block diagram of a system capable of
`operating either as an image senser or as a memory in
`accordance with the present invention.
`-
`FIGS. 6A through 6W are diagrams of amplitude
`versus time of voltage signals occurring at various
`points in the system of FIG. 5. The diagrams of FIGS.
`6A—6I are drawn to a common time scale and depict
`two lines of scan. The diagrams of FIGS. 6.I—6W are
`drawn to another expanded common scale and depict a
`single line of scan. The point of occurrence of a signal
`of FIGS. 6A-6W in the block diagram of FIG. 5 is
`identified in FIG. 5 by a literal designation correspond-
`ing to the literal designation of the figure.
`FIG. 7 is a schematic diagram of the read-write cir-
`cuit of the system of FIG. 5 illustrating the manner in
`which the system may be used as an analog memory.
`FIGS. 8A through 8D show waveform diagrams use-
`ful in explaining the operation of the circuit of FIG. 7.
`Before proceeding to describe the apparatus of FIG.
`5 embodying the present invention the array of charge
`storage and radiation sensing devices used in the appa-
`ratus will be described. While a specific form of the
`array fabricated using a specific technology is shown
`and described, it will be understood that the array uti-
`lized in the apparatus may take on other forms andthat
`any of the commonly used technologies for charge
`transfer devices may be used in the fabrication thereof.
`Reference is now made to FIGS. 1-4 which show an
`
`array 20 of charge storage and radiation sensing de-
`vices 21, such as the device described in FIGS. 2A, 2B
`
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`4,000,418
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`3
`and 2C, of aforementioned U.S. Pat. No. 3,805,062
`arranged in four rows and columns. The array includes
`four row conductor lines. each connecting the row-ori-
`ented plates of a respective row of devices, and are
`designated from top to bottom X1, X2, X3 and X... The
`array also includes four column conductor lines, each
`connecting the column-oriented plates of a respective
`column of devices, and are designated from left to right
`Y,, Y2, Y3 and Y4. Conductive connections are made to
`lines through conductive landings or contact tabs 22
`provided at each end of each of the lines. While in FIG.
`1 the row conductor lines appear to cross the column
`conductor lines, the row conductor lines are insulated
`from the column lines by a layer 24. of transparent glass
`as is readily apparent in FIGS. 2, 3 and 4. In FIG. 1 the
`outline of the structure underlying the glass layer 24 is
`shown in solid outline for reasons of clarity.
`The array includes a substrate or wafer 25 of semi-
`conductor material of N-type conductivity over which
`is provided an insulating layer 261 contacting a major
`face of the substrate 25. A plurality of deep recesses 27
`are provided in the insulating layer. each for a respec-
`tive device 21. Accordingly, the insulating layer 26 is
`provided with thick or ridge portion 28 surrounding a
`plurality of thin portions 29 in the bottom of the re-
`cesses. In each of the recesses is situated a pair of sub-
`stantially identical conductive plates or conductive
`members 31 and 32 of rectangular outline. Plate 31 is
`denoted a row-oriented plate and plate 32 is denoted a
`column oriented plate. The plates 31 and 32 of a device
`21 are spaced close to one another along the direction
`of a row and with adjacent edges substantially parallel.
`In proceeding from the left hand portion of the array to
`the right hand portion, the row-oriented plates 31‘alter-
`nate in lateral position with respect to the column ori-
`ented plates 32. Accordingly, the row-oriented plates
`31 of pairs of adjacent devices of a row are adjacent
`and are connected together by a conductor 33 formed
`integral with the formation of the plates 31.‘ With such
`an arrangement a single connection 34 from a row
`conductor line through a hole 39 in the aforementioned
`glass layer 24 is made to the conductor 33 connecting
`a pair of row-oriented plates. The column-oriented
`conductor lines are formed integrally with the forma-
`tion of the column-oriented plates 32. The surface
`adjacent portion of the substrate 25 underlying the
`space between the plates 31 and 32 of each device 21
`is provided with a P-type conductivity region 36. The
`glass layer 24 overlies the thick portion 28 and thin
`portion 29 of the insulating layer 26 and the plates 31
`and 32, conductors 33 and column-oriented conductor
`lines Y,—Y., thereof except for the contact tabs 223‘
`thereof. The glass layer 24 may contain an acceptor
`activator and may be utilized in the formation of the;
`P-type region 36. A ring shaped electrode 38 is ‘secured
`to the major surface of the substrate opposite the major
`surface on which the devices 21 were formed and pro-
`vides conductive connection to the substrate. Such a.
`connection to the substrate permits rear face as well as
`front face illumination of the array.
`The array 20 and the devices 21 of which they are
`comprised may be fabricated using a variety of materi-
`als and in variety of sizes in accordance with estab-
`lished techniques for fabricating integrated circuits as
`described in
`the aforementioned U.S. Pat. No.
`3,805,062..
`Referring now to FIG. 5 there is shown a block dia-
`gram of apparatus utilizing the charge storage array of
`
`4
`FIG. 1 which is capable of function as both an imager
`and as an analog memory..'I‘he apparatus will be ini-
`tially described with regard tolits functioning as an I
`imager and then will be described with regard to its
`functioning as an analog memory. Functioning as an
`imager, the apparatus. provides agvideo signal
`in re-
`sponse to radiation imaged onthe array by a lenslsys-
`tem (not shown), for example. The video signal may be
`applied to a suitable display device (not shown) such as
`a cathode ray tube as described in the above-.
`referenced U.S. Pat. No. 3,805,062 along with sweep
`voltages synchronized with the scanning of the array to
`convert the video signal
`into a visual display of the
`image.
`The systemrwill be described in connection with
`FIGS. 6A-6W which show diagrams of amplitude ver-
`sus time of signalsioccurring at various pointsin the
`system of FIG. 5. The point of occurrence of a signal of *
`FIGS. 6A—6W is referenced in FIG. 5 by a literal desig-
`nation corresponding to the literal designation of the
`figure reference.
`The system includes a clock pulse generator 51 -
`which develops a series of regularly occurring Y-axis
`pulses S2 of short duration shown in FIG. 6A, occur-
`ring in sequence at instants of time t1—ts and represent-
`ing a half scanning cycle of operation of the array. The
`output of the clock pulse generator 51 is applied to a
`first counter 53 which divides the count of the clock
`
`«
`
`pulse generator by four to derive X-axis clock pulses
`54, such as shown in FIG. 6B. The output of the first
`counter 53 is also applied to a second counter 55- which
`further divides the count applied to it by four to pro- 1
`vide frame synchronizing pulses.56 to the array.
`The sensing array 20, which is identical to the charge
`storage array‘ of FIG. 1 and isidentically designated,
`includes row conductor lines Xgthru X4 andcolumn
`conductor lines Y, thru Y4. The drive circuitsfor the
`row conductor lines X,—X4 and for the column conduc- .
`tor lines Y,-Y4 of array 20 are included onthe same
`substrate 50vas the array to minimize the number of
`external connections which are required to be made for
`connection of the array 20 into the system.
`To enable selective read out of a row of devices a
`
`plurality of row-enable switches 61-64 are provided.
`The row-enable switches 61-64. are in the form of
`
`MOSFET transistor devices formed integrally on the
`substrate, each having a source electrode, a drain elec-
`trode and a gate electrode. Each of the drains of de-
`vices 61-64 is connected. to one end of a respective one
`of the row conductor lines X,~X., and each» of the
`sources of the devices 61-64 is connected to row termi-
`nal 65. The row terminal 64 is connected to the invert-
`ing terminal 71 of a high gain differential amplifier 70,‘
`the non-inverting terminal 72 of which is connected to
`the pole 73 of a single pole double throw switch 74. (A
`change in voltage at the inverting input terminal in one
`direction in relation to a reference potential produces a
`change in voltage at the output terminal in the opposite
`direction in relation to the reference potential. A
`change in voltage at the non-inverting terminal in one
`direction in relation to a reference potential produces a
`change in voltage at the output terminal in the same
`direction in relation to the reference potential). One
`terminal 75 of the switch 74 is ‘connected to the nega-
`tive terminalof a 5 volt bias source 77, the‘ positive
`terminal of which is connected to ground. The pole 73
`of the switchis driven by injection actuator 78 synchro-
`nized with the Y-axis clock pulses to provide the wave-
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`4,000,418
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`5
`form of FIG. 6F at the noninverting terminal 72 of the
`differential amplifier 70. When the switch 74 is set to
`apply a -5V bias to the noninverting terminal 72, as
`indicated by the dotted portion 78a of waveform of
`FIG. 617', read out of charge in a row may be repeated,
`as will be explained below. A feedback capacitor C“, is
`connected between the output and the inverting input
`terminal 71 of the high gain differential amplifier 70.
`The feedback capacitor CM is shunted by a reset switch I
`79 in the form of a MOSFET transistor, the gate of
`which is driven by the integrator reset circuit 79a syn-
`chronized with the Y—axis clock pulses of FIG. 6A. The
`potential of inverting terminal 71 follows the nonvert-
`ing terminal 72 of the high gain differential amplifier
`70. Thus, when the reset switch 79 is closed the voltage
`on terminal 65 is the same as on the nonverting termi-
`nal 72, i.e. the voltage waveform of FIG. 6F. The gate
`electrodes of the transistors 61-64 are connected to
`successive output terminals of the row shift register 80,
`numbered respectively 1, 2, 3 and 4. The outputs at
`terminals 1 and 2 of the row shift register are shown,
`respectively, in FIGS. 6D and 6E. The outputs at termi-
`nals 3 and 4 are similar to output of terminal 1 except
`appropriately delayed in time to occur during the third
`and fourth row line scan periods, respectively. The
`input to row shift register 80, referred to as frame sync
`pulse, is the pulse obtained at the output of the second
`counter 55. One frame sync pulse occurs for every 16
`Y-axis clock pulses. Oppositely phased clock drive
`pulses for the row shift register 80 are derived from the
`X-axis clock pulses. The oppositely phased drive line
`pulses are applied to each of the stages of the row shift
`register 80 to produce the indicated outputs at the
`terminals 1-4 thereof. The row shift register 80 may be
`any of a number of shift registers known to the art. The
`elements of the shift register 80 may be concurrently
`formed on the substrate at the same time that the de-
`vices of the array 20 are formed.
`To reestablish storage voltage on all of the row lines
`and, in particular on the row just read out, row reset
`switches 81-84 are provided. The reset switches 81-84
`are in the form of MOSFET transistors integrally
`formed on the substrate 50, each having a drain elec-
`trode connected to the other end of a respective one of
`the row conductor lines X,-X4 and each having a
`source electrode connected to a row line biasing termi-
`nal 85, which in the operation in the system as an
`imager is connected through a two position switch 86
`to the negative terminal of a —-20 volt source 87, the
`positive terminal of which is connected to ground.
`Each of the gate electrodes of the transistors 81-84 is
`driven by a common drive signal 88 shown in FIG. 61
`obtained from the output of column and row reset
`generator 89 through a two position switch 90. The
`inputs to the column and row reset generator 89 are the
`X-axis clock pulses of FIG. 6B.
`To reestablish storage potential on all of the column
`lines after read out of a row of devices, column reset
`switches 91-94 are provided. The reset switches 91-94
`are in the form of MOSFET transistors integrally
`formed on the substrate 50, each having a source elec-
`trode, a drain electrode and a gate electrode. Each of
`the sources of the devices 91-94 is connected to one’
`end of a respective one of column lines Y1 -Y4 and
`each of the drains is connected to column drain termi-
`nal 95 which in turn is connected through two position
`switch 96 to the negative terminal of ---IO volt source
`97,
`the positive terminal of which is connected to
`
`5
`
`10
`
`6
`ground. Each of the gates of devices 91-94 is con-
`nected to gate terminal 98 which is connected through
`two position switch‘ 90 to the column and row reset
`generator 89. Thus, during the occurrence of the line
`X, row enable gating pulse of FIG. 6D the voltage
`appearing on line X, is set by the voltage on terminal 65
`shown in FIG. 6F. After the line X, rises to zero volts,
`charge is injected into the substrate and the voltage
`thereafter drops to -20V and remains there in response
`to actuation of the row reset switches 81-84 by the
`voltage waveform of FIG. 61 applied to switches 81-84.
`A similar sequence of voltage changes occurs on line
`X2 during the occurrence of the line X2 row enable gate
`waveform of FIG. 6E. Also, a similar sequence of volt-
`age changes (not shown.) occurs on lines X3 and X4.
`When the apparatus of FIG. 5 is operated either as an
`imager or as an analog memory in the read out mode
`the two position switches 86, 90 and 96 controlled by
`precharge actuator 99 are in the position shown in the
`drawing. When the switches 86, 90 and 96 are set in the
`other position by the precharge actuator and referred
`to as the precharge position, —-5 volt sources 101 and
`102 are connected to row lines X,-X4 and to column
`lines Q,—Y., by switches 86 and 96. This action is
`achieved by connecting the gates of devices 81-84 and
`91-94 to bias source 103 through switch 90. With the
`switches set in the precharge position, thermally gener-
`ated charge in the substrate fills the potential wells of
`all of the devices of the array preparatory to electrically
`setting the charge levels in the device in accordance
`with an analog signal to be electrically written in and
`stored in the array, as will be fiurther explained below.
`Also integrally formed on the substrate 50 are a plu-
`rality of column line drive switches in the form of MOS-
`FET transistors 111-114. Each of the transistors
`111-114 has a drain electrode connected to the other
`
`45
`
`60
`
`end of a respective one of column conductor lines
`Y,-Y4. The source electrodes of transistors 111-114
`are connected to terminal 115. The gate electrodes of
`the transistors 111-114 are connected to successive
`output terminals of the column shift register 116, n-um-
`bered respectively 1, 2, 3 and -4. The output terminals
`1, 2, 3 and 4 of the column shift register are shown,
`respectively,
`in FIGS. 6M-6P‘. The input to column
`shift register, referred to as line sync, are the X-axis
`clock pulses obtained from the output of the first
`counter 53. Oppositely phased clock drive pulses for
`the column shift register 116 are derived from the Y-
`axis clock pulses. The oppositely phased drive pulses
`are applied to each of the stages of the column shift
`register to produce the indicated outputs at the termi-
`nals 1-4 thereof.
`As mentioned above the selected row of devices is
`read out by resetting the selected row line to its read
`out level of voltage of —-5 volts and maintaining the
`voltage at this level during the transfer of charge from
`a column cell to a row cell of the selected row for each
`of the devices of the selected row. Resetting the se-
`lected row is accomplished by applying the resetting
`pulses of FIG. 61 to the reset switch 79 which connects
`the output of the high gain differential amplifier to the
`inverting input for a short interval prior to actuation of
`each of the column switches 111-114. As the non-
`
`inverting terminal 72 is connected to a -5 volt source
`77 and as the potential of the inverting terminal 71
`follows the potential of the noun-inverting terminal, -5
`volts appears on the selected row line. Shortly after the
`reset switch 79 is opened by return of gate voltage of
`
`1031-010
`
`1031-010
`
`

`
`4,000,418
`
`8 .
`
`‘
`
`7
`FIG. 6L to zero, the first column line Y, is connected to
`ground by application of gate voltage of FIG. 6M to
`switch 111. The transfer of charge from the column
`connected cell into row connected cell causes an op-
`posing charge to be induced in the selected row line,
`for example row line X,, which is proportional to the
`transferred charge. This induced charge is in response
`to.‘ amplifier action in which the feedback capacitance
`C“, functions to drive the inverting terminal 71 of the
`amplifier to maintain zero difference in voltage be-
`tween its potential and the potential on the non-invert-
`ing terminal 72 connected to the source 77. The
`change in output voltage appearing at the output termi-
`nal of the differential amplifier 70 is equal to the charge
`delivered to the row line X, divided by the feedback
`capacitance .C,.~,;. Accordingly, the voltage developed
`across the feedback capacitor C“, and hence at the
`output terminal of the differentialamplifier 70 is pro-
`portional to charge stored in the column cell and trans-
`ferred to the row cell. Charge sensing in this manner is
`further described and claimed in copending patent
`application Ser. No. 591,636, filed, June 30, 1975 and
`assigned to the assignee of the present invention. The
`charge‘ stored in each of the other column cells of the
`selected rows are similarly sensed by first resetting the
`selected row line by reset pulse of FIG 61 and thereafter
`connecting the selected column line to ground to ob-
`tain a voltage at the output of the differential amplifier
`which isproportional to the stored charge. The volt-
`ages appearing onthe Y,—Y, lines during this sequence
`of operations is shown in FIGS. 6Q—6T, respectively.
`Note that actuation of the switches 111-114 by column
`register outputs shown in FIGS. 6M—6P causes the »
`column lines Y,-Y, to rise from -10V to zero and
`remaining at zero until, reset, by the column and row
`reset pulse of FIG. 61. The pulses of FIG. 61 causes the
`column lines Y,—Y., to be reset to —-l0V and the row
`lines X,-X4 to be reset to —-20V after each row of scan.
`As evident from FIG. 6F prior to column and row reset-
`ting operation the charge stored in the row cells of a
`selected row may be either injected into the substrate
`by the potential of the selected row line rising to zero or
`it may be retained by maintaining the voltage on the
`row line at —-5 volts as shown in dotted portion 118 of
`FIG. 6F. During the occurrence of row resetting pulse
`of FIG. 61 the selected row line is dropped to -20V and
`charges stored in the row cells of the selected row .
`become stored and availablefor a subsequent read out.
`The signals appearing at the output of the differential
`amplifier 70 are shown in FIG. 6U. The signals are
`sampled by a sample‘ and hold circuit 120 and then
`applied to output amplifier 121. The sample andhold
`circuit 120 includes transistor 122 having a drain 123,
`a source 124 and a gate 125 and a capacitor C,. The
`source to drain current flow path of the transistor 120
`is connected betweenethe output of the amplifier 70
`and one terminal of capacitor C,, the other terminal of
`which is connected to ground. The gate 125is con-
`nected to sample pulse generator 126 which isrdriven
`by the Y-axis clock pulses and provides the train of
`sampling pulses 127 shown in FIG. 6V. Each of the
`pulses 127 are of short duration and are equally spaced
`along the time axis. One sampling pulse occurs for
`every Y-axis clock pulse. Each of the pulses 127 are
`phased to occur during the occurrence of a signal level
`at the output of amplifier 70 corresponding to the
`charge sensed thereby dure to the transfer of charge
`from a column cell to a row cell of a device in the
`selected row.
`
`In the operation of the system the voltage of the row
`line source 87 which is shown as —-20 volts, establishes»
`the charge storage capability of the row connected or
`oriented cells of each of the devices of the array and
`the voltage of the column line source 97, which is
`shown as -10 volts, establishes the charge storage ca-
`pability of the column connected or oriented cells of
`each of the devices of the array. Preferably, the storage
`capability of the row cell should be greater than the
`column connected cell of each device. This result is
`achieved by applying higher voltages to the row con-
`nected plates than to the column connected plates. Of
`course, the same result could be achieved by using a
`thicker layer of oxide under the column connected
`plate than the row connected plate and ‘utilizing the
`same voltages on the column and row lines. Under the
`control of the clock pulse generator frame synchroniz-
`ing pulses, such as shown in FIG. 6C, are applied to the
`row shifter register. Line interval gating pulses, two of
`which are ‘shown for lines X, and.X2 in FIGS. 61) and
`6E, respectively, are derived at the output points 1-4 of
`the row shift register 80 in response to line rate clock-
`ing of the row shift register by the X-axis clock pulses.
`The line rate pulses are utilized to gate in sequence the
`row enable switches 61-64 to apply in sequence the.
`voltage appearing on terminal 65 to the row lines
`X,—X.,.
`With the row enable pulse applied to line X, the
`potential of line X, changes fromthe —-20 volt level to
`the -5 volt level and causes the charge stored in the
`row connected cells of row X, to transfer to the column
`connected cells of that row. Under the control of the
`
`line synchronizing pulses
`clock pylse generator 51,
`shown in FIG. 6B are applied to the column shift regis-
`ter 116. Device or element gating pulses such as shown
`in FIGS. 6M—6P arederived, respectively, at the output
`points 1-4 of the column shift register 116 in response
`to the element rate clocking of the column shift register
`by the Y-axis clock pulses. The element rate pulses are
`utilized“ to gate in sequence the column line switches
`111-114 connecting in sequence the column lines ‘.
`Y,—Y, to ground through mode switch 117. Thus, the
`charges stored in the column cells of row X, are now
`transferred to the row connected cells of row X,. It
`should be noted that the charges in all of the other
`devices in all of the other rows of the array are situated
`in the row connected cells of the devices. The gating in
`sequence of the column lines Y,—Y.,has no effect with
`respect to the transfer of charge in the devices of other
`rows. The effect of applyingthe gating pulses to the
`column line ‘switches 111-114 on the column line