EXHIBIT 1029
`
`T. Ozaki, et al., “A Low-Noise Line-Amplified MOS Imaging Devices”,
`
`IEEE Transactions on Electron Devices, Vol. 38, No. 5 (May 1991)
`
`TRW Automotive U.S. LLC: EXHIBIT 1029
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NUMBER 8,599,001
`IPR2015-00436
`
`

`
`IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL 38. NO 5. MAY 1991
`
`A Low-Noise Line-Amplified MOS Imaging Devices
`
`969
`
`Toshifumi Ozaki, Hajime Kinugasa, and Takashi Nishida
`
`Abstract-A new MOS imaging device is proposed. It has an
`amplifier and a correlated double sampling (CDS) circuit at
`each vertical signal line and an offchip smear differential gear.
`The 1/2-in image format, 500 X 485 pixels, is designed on
`1.5-pm CMOS technology and its fundamental characteristics
`are analyzed. Random noise is 120 PA, and the aperture ratio
`is greater than 70%. The smear level is 100 dB. The fixed pat-
`tern noise is 2000 pA in the dark, 0.62% in light. Some advan-
`tages of this device include a 5-V power supply requirement, a
`high saturation current, a high signal-to-random-noise ratio
`and a low smear level. However, the fixed pattern noise in the
`dark must to be lowered.
`
`I. INTRODUCTION
`OLID-state imaging devices have been widely used for
`
`S home video cameras. However, there is a great need
`
`to reduce the image format, thereby making the camera
`more compact. Conversely, future high-definition TV
`systems will require 5 to 8 times as many pixels as current
`devices contain [1]-[4]. In order to meet these require-
`ments, the size of each pixel element needs to be reduced
`to allow for a higher pixel density.
`There are two types of imaging devices: a CCD type
`and an X-Y addressable MOS type. Currently, an inter-
`line-CCD [ 5 ] , [6] is mainly used commercially because
`of its low random noise characteristics. In the CCD de-
`vice, however, the photodiode and vertical transfer struc-
`ture exist on the same plane. As a result, two problems
`prevent a reduction of the pixel size, even if fine process
`technology were used. First, the area of the vertical-trans-
`fer structure cannot be reduced since it must be capable
`of storing the charge for a saturated signal. Secondly, the
`isolation length between the vertical-transfer structure and
`photodiode must be preserved in order to maintain the
`smear level.
`A pixel of an X-Y addressable MOS sensor [7], [8]
`could be scaled down by implementing a smaller process
`technology. There would be no similar problems as those
`encountered with the interline CCD. However, parasitic
`capacitance of a signal line does cause a 10 times greater
`random noise level than in CCD. Accordingly, the au-
`thors propose a new X-Y address MOS type device to im-
`prove random noise characteristics. This device differs
`from the conventional MOS sensor in that is has an am-
`
`Manuscript received May 22. 1990: revised Scpteiiibci- 27. I990.
`T. Ozahi and T. Nishida iirc % i t h the Ccntrul Research Laborator). Hi-
`tachi Ltd.. Kohuhunji. Tokyo 185. Japan.
`H . Kinugaha is with Hitachi Device EngineerinE. Co.. Ltd.. Mobara.
`Chiba 297. Japan.
`IEEE Log Number 9142978.
`
`plifier and a correlated double sampling (CDS) circuit [9]
`for each vertical signal line. This device is called
`- Line-Amplified-MOS Imaging Device (LAM). Section I1
`describes the circuit configuration and operation. After the
`analysis of random noise and design considerations, the
`new structure’s effect on random noise is discussed in
`Section 111. Methods for suppression of smear, which pre-
`vent pixel size reduction, are presented in Section IV. In
`Section V, the fixed pattern noise introduced by the LAM
`device is discussed in terms of its origin and suppression
`method. Finally, the results of the analysis are summa-
`rized in Section VI. The analyzed values are for a 1 /2-in,
`500 x 485 image sensor built on 1.5-pm CMOS process.
`
`11. CONFIGURATION A N D OPERATION
`
`A schematic diagram of LAM is given in Fih. 1. Sim-
`ilarly to a conventional MOS device [7], the photodiode
`is addressed by a vertical scanner, which scans the verti-
`cal switch, and a horizontal scanner, which scans the hor-
`izontal switch. In addition, LAM has a line amplifier and
`a CDS circuit [9] at each vertical signal line and off-chip
`smear differential gear [lo].
`The circuit diagram of the signal readout path and clock
`timing is shown in Fig. 2. LAM operates in the following
`sequence:
`1) t = tl-t4: In the first increment of horizontal blank-
`ing time, smear reads out to memory capacitance CMl .
`t = t l : Switch SI is on to reset the vertical signal-
`line capacitance Cv.
`t = t,: Switch SI is off to activate the line amplifier.
`At the same time, KTC noise generates on the vertical
`signal-line capacitance Cv.
`t = t3: Switch S, is off to activate the source-fol-
`lower. Smear without KTC noise is transferred to memory
`capacitance CMl through coupling capacitance C, (clamp).
`t = t4: Switch S? is off and smear has been held on
`the memory capacitance CMl (sample-and-hold) .
`2) t = t5-t9: The second increment of horizontal blank-
`ing time is similar to the first increment, except that the
`signal with smear is now read out to memory capacitance
`CM2. In this case, the vertical switch SpD is on at time t7.
`3) During the horizontal scanning period, switches SRI
`and SHl are sequentially enabled together to read out smear
`from memory capacitance CMl through the output source-
`follower. Then, after one horizontal clock delay, the sig-
`nal with smear is read out in the same way by enabling
`SR, and SH2.
`4) After the smear charge is delayed one horizontal
`
`0018-938319110500-0969$01 .OO 0 1991 IEEE
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`1029-001
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`

`
`970
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 38. NO. 5. MAY 1991
`
`Id
`
`.VERTICAL
`SIGNAL-LINE
`
`DRIVER
`
`OUT
`
`Fig. 1. Schematic diagram of the line-amplified MOS imaging device.
`
`LINE
`AMPLIFIER
`c-w
`
`CDS ClRUlT
`
`SMEAR
`DIFFERENTIAL
`
`(a)
`*
`SMEAR- READOUT SIGNAL- READOUT
`t
`4
`HBL A
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`s1
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`R I " -
`
`--- NOISE
`._.
`
`(b)
`Fig. 2. Basic operation of LAM. (a) Circuit diagram ofsignal readout path
`(h) Clock timing and voltage of each node.
`
`clock, the smear-only charge and the signal with smear
`charge are differentiated to obtain just the signal charge.
`LAM'S configuration and operation offers many advan-
`tages including:
`1) a photosite of a high aperture ratio (more than 70%);
`a pixel consisting of one photodiode and one switch;
`2) low random noise; the line amplifier leads to 1/5
`input capacitance and 1/6 noise band compared to
`a conventional MOS device [7], [8]: the CDS cir-
`cuit cancels the KTC noise;
`3) low smear; smear merges into the signal in only one
`sampling period T,, which is 1/60 as short as the
`conventional value [7]; an off-chip smear differen-
`tial gear separates smear from the signal.
`The configuration of each amplifier is shown in Fig. 3.
`The line amplifier consists of a cascoded CMOS inverting
`amplifier [ 141 due to high voltage gain. The PMOS driver
`of the source-follower is formed in a separate well which
`is connected to the output. As a result, the circuit is free
`
`Fig. 3. Amplifiers. The channel width ( W ) and length (L) is indicated in
`micrometers for each device ( W / L ) . Vs2. Vs,, V,,, are bias voltages. (a)
`Line amplifier. (b) Source-follower. (c) Buffer amplifier. (d) Output source-
`follower.
`
`from body effect and its voltage gain is unity. The buffer
`amplifier consists of a CMOS inverter with an NMOS
`driver. The output source-follower has the same circuit
`configuration as the source-follower.
`
`111. RANDOM NOISE
`In this section, random noise is analyzed. Based on the
`results, design methods to reduce random noise are con-
`sidered. Finally, noise values are presented.
`
`A. neoretical Analysis
`LAM has the following two noise origins: one is from
`a MOS transistor in each amplifier and the other comes
`from each switch when the switch is off. The noise volt-
`ages referred to the input of each line amplifier VR,
`can
`be expressed as
`f
`
`jzl 1 1 ~
`
`n
`
`
`
`cos 2r.fTA(Il - I,) d~
`
`vRNA = So 2
`
`n
`
`(1)
`In (I), 5''
`is the noise power spectrum density of the MOS
`transistor referred to the input of the transistor [ 1 13, [ 121.
`FA is the reference coefficient from the input of the tran-
`sistor to the input of the amplifier [ 1 I]. F, is the reference
`coefficient from the input of the amplifier to the input of
`the line amplifier. TA is the sampling period of the ampli-
`fier output, and n is the sampling number of the amplifier
`output in one readout sequence. 1, is the arithmetic sign
`in the signal of the sampled output of the amplifier (+ or
`-) andf, is the noise bandwidth when the output of the
`amplifier is sampled.
`Otherwise, the noise voltage referred to the input of the
`line amplifier of each switch VNRs can be given as
`'VNR, = F R n R KT/ CR.
`
`(2)
`
`1029-002
`
`

`
`TABLE 1
`RANDOM NOISE SUPPRESSION METHODS
`
`Noise form MOS Transistor in Each Amplifier
`
`Source
`
`Line amplifier
`Source-follower
`Buffer amplifier
`Output source-
`follower
`
`Source
`
`Suppression
`Method
`
`-
`line amplifier
`line amplifier
`line amplifier
`
`Reference
`Coefficient F,
`
`1
`I / G :
`I / G i
`I / G i
`
`Noise from Each Switch
`
`Suppression
`Method
`
`CDS circuit
`line amplifier
`line amplifier
`
`line amplifier
`differential
`
`Reference
`Coefficient FR
`
`exp (k45&FT$)
`I /GS
`I / G f
`I / G i exp (-D/ IO)
`
`I /GF
`
`GF Gain of line amplifier
`T, Sampling period.
`fC.+ Cutoff frequency for line amplifier
`D Differential factor.
`( ) Reset capacitance
`
`In (2), CR is the value of the capacitance which is reset
`by the switch, K is Bolzmann's constant, and Tis absolute
`temperature. FR is the reference coefficient from the input
`of reset capacitance to the input of the line amplifier, and
`nR is the switching number of the switch in one readout
`sequence.
`Since signal is expressed as charge in an imaging de-
`vice, noise should also be expressed in charge or current.
`Thus noise voltage VN is converted to noise current IN by
`
`In (3), Cv is the capacitance value at the input of the line
`amplifier, fH is the driving frequency of the horizontal
`scanner, and fe is signal bandwidth at the device output.
`
`B. Design Consideration
`The reference coefficients F,, FR, which are given in
`Table I, express the response of the total circuit to each
`noise source. The voltage gain of the souce-follower and
`buffer are assumed to be 1. Since the line amplifier has a
`high voltage gain GF (45 in design), noises other than from
`the line amplifier and switch SI can be negligibly small.
`Moreover, the CDS circuit reduces the reset noise of
`switch SI by choosing a cutoff frequency fcF just wide
`enough for the line amplifier. Accordingly, the main
`source of LAM is the line amplifier.
`Ordinary noise voltage decreases as noise band de-
`creases [13]. Thus the noise bandwidth fc of the line am-
`plifier is limited, as shown in Fig. 4. When switch S2 is
`off, the noise below the cutoff frequency 1 /27rRS2 Cc of
`the high-pass filter, which consists of the coupling capac-
`
`- r
`
`sz OFF
`
`97 I
`
`r
`
`FREQUENCY ( Hz )
`(b)
`Fig. 4. Random noise band for line amplifier output, (a) when switch S2
`is off (clamp), (b) when switch S, is off (sample and hold). R,:. R,, are,
`respectively, the on-resistance of switches S3. S3. C,- is coupling capaci-
`tance and C , is memory capacitance.
`
`itances Cc and the on-resistance of switch S2, is clamped
`and merged into one signal. When switch S3 or S4 is off,
`the noise below the cutoff frequency 1/2xRs3CM of the
`low-pass filter, which consists of the memory capacitance
`C, and the on-resistance of switch S3 or S,, is sampled
`and held and then merged into one signal. Since readout
`to memory capacitance C,
`is done in the horizontal blank-
`ing period of about 10 ps, each sampling interval can be
`selected at 1 ps. According to the Nyquist criterion, these
`cutoff frequencies are designed to be 500 kHz. Moreover,
`switch S, and S4 contain a complementery MOS transistor
`to prevent variation of on-resistance associated with sig-
`nal level variation.
`The reference coefficient FA of each transistor of the
`line amplifier is, respectively, given by
`( 4 4
`1,
`for the driver
`(4b)
`( g m L / g r , d 2 .
`for the load
`(4c)
`0,
`for the cascode.
`is the transconductance of the driver and g,,
`is
`Here, g,,
`the transconductance of the load. The transconductance
`of the load can be made much lower than the driver's
`without strongly affecting circuit performance. So, the
`driver is the primary noise source.
`A MOS transistor has two noise origins: thermal noise
`and 1 lfnoise. Noise power spectrum density S, [ 111, [ 121
`is proportional, respectively, to one over the square root
`of the ratio of channel width to channel length (current I
`constant) and to one over the channel area. Accordingly,
`its noise voltage can be reduced by using the minimum
`channel length and a wide channel width. In the case of
`the driver, however, the total input capacitance of the line
`amplifier, including the gate capacitance of the driver, in-
`creases as the channel width increases. So, signal voltage
`is also reduced and a minimum random noise current is
`
`1029-003
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`IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 38. NO. 5. MAY 1991
`
`I
`
`3 1.5
`
`1.0 n
`
`v,
`
`THERMAL NOISE
`
`DRIVER CHANNEL WIDTH W , ( A.U.)
`Fig. 5. Driver channel width dependence of random noise current in line
`amp1 ifier.
`
`reached. The dependence of the noise current on the driver
`channel width is shown in Fig. 5. The noise current that
`is generated by 1 /f noise has a minimum value at the
`point where the gate capacitance of the driver CG WD(LD
`+ 2 4 ) is equal to the vertical signal line capacitance Cvo.
`W, is the channel width of the driver; Lo is the effective
`channel length of the driver; CG is the unit gate capaci-
`tance; and xj is the depth of the diffused layer. The noise
`current that is generated by thermal noise reaches a min-
`imum value at a channel width of 1 /3.
`Finally, the transistor type is considered. The minimum
`current of the driver is calculated for the NMOS driver
`and PMOS driver, as shown in Fig. 6. Here, p is the mo-
`bility, nTE is the effective trap density of l /f noise, and
`y is the inclination of 1 /f noise power spectrum [ 121,
`which is obtained from experiment. Thermal noise is
`higher in the PMOS driver than in the NMOS driver due
`to the lower mobility: However, 1 /f noise, though, is
`lower in PMOS driver due to the higher inclination of 1 /f
`noise power spectrum. Since total noise at a sampling pe-
`riod of l ps is lower in the PMOS driver, it is selected
`and the gate capacitance was designed to be 1 / 3 of the
`vertical signal capacitance to minimize thermal noise.
`
`C. Random Noise Value
`The calculated random noise value for each noise source
`is shown in Table 11. The total noise of the LAM is 120
`PA, which is about four times as large as the interline
`CCD's (30 PA) [6]. However, the aperture of LAM (71 %)
`is about three times as large as that of the interline-CCD
`(24%) [6]. Therefore, the signal-to-noise ratio in LAM is
`about the same as in the interline CCD.
`
`IV. SMEAR
`When pixel size is scaled down, smear increases, due
`to a reduction of the isolation length. Thus suppression of
`smear is an important problem in solid-state imaging de-
`vices. In this section, methods for smear reduction are
`presented. A technique for widening the dynamic range,
`which enhances smear reduction, is also explained.
`
`fcF 1112Ts
`Cvo 11.6 pF
`Cor, 11.12 fF /p m2
`L0+25 -1.5pm
`x, I 0.2 p m
`
`5 t
`
`50 100
`5 10
`1
`SAMPLING PERIOD Ts (p SBC )
`(b)
`Fig. 6. Comparison of minimum random noise current for p-channel driver
`and n-channel driver in line amplifier. (a) Thermal noise. (b) I / f noise.
`Noise band for line amplifierf,.,
`is assumed to be 1 /2Ts.
`
`TABLE 11
`RANDOM NOISE CURRENT
`
`Source
`
`Line amplifier
`
`Source-follower
`
`Buffer amplifier
`
`Output source-
`follow er
`Subtotal
`
`driver
`cascode
`load
`driver
`load
`driver
`load
`driver
`load
`
`Thermal
`
`I / f
`
`59
`0
`37
`6.7
`4.9
`7.6
`6.9
`4.7
`4.9
`71
`
`30
`0
`61
`3.3
`4.2
`13
`0.9
`4.1
`4.1
`70
`
`43
`35
`35
`7. I
`15
`67
`120
`
`Units: picoamperes.
`
`A. Methods for Smear Reduction
`Smear in a MOS device is caused by the photo-gener-
`ated carriers diffusing into the vertical signal line during
`
`the horizontal scanning period. In LAM, pixels are con-
`structed on a p-type substrate to avoid voltage modulation
`[15] caused by parallel operation of the line amplifiers.
`
`1029-004
`
`

`
`OZAKI c/ (,/. A LOW-NOISE LINE-AMPLIFII-I) MOS IMAGING DEVICF.
`
`973
`
`TRANSFER CURVE
`
`) >
`w
`0
`
`i RANGE ,+ C-
`.i*
`.y.. __________________________ BIAS
`
`;
`
`I- s
`a 5 B
`I- 3 n
`0
`I- 3
`0
`0
`"0
`INPUT VOLTAGE VI,
`(b)
`
`1
`>
`,1201
`
`4
`
`0
`
`7
`
`
`
`SMEARMERGE-TIME T, ( F sec)
`Fig. 7. Smear suppression methods: merge time reduction and differential.
`
`The smear level is 35 dB in a conventional MOS device
`[7]. In LAM, however, the following two methods lead
`to a low smear level, as shown in Fig. 7:
`1) The time it takes the smear to merge with signal T,
`is reduced from one horizontal scanning period, 63.5 ps,
`to one sampling time, 1 ps.
`2) A smear differential separates the smear from the
`signal and reduces the smear level by about -30 dB.
`As a result, the calculated smear level reaches about
`100 dB.
`The maximum output voltage swing of the line ampli-
`fier limits the maximum signal level over which smear
`cannot be canceled by the smear differential. This maxi-
`mum signal-to-signal saturation MSS can be expressed by:
`
`(5)
`In (3, TG is the smear generation time, TH is the horizon-
`tal scanning period, VDR is the maximum output voltage
`swing of the line amplifier, and V s A T is the signal satu-
`ration output voltage swing of the line amplifier. The cal-
`culated maximum signal-to-signal saturation in LAM is
`65 dB. (TG = 2 /.Ls, TH = 63.5 /AS, V D R = 2.6 V, VSAT =
`1.3 V.) This value is high enough for ordinary use.
`
`B. Dynamic Range of Line AmpliJier
`In LAM, the maximum output voltage swing (dynamic
`range) of the line amplifier is enlarged by the capacitive
`coupling of the gate switch S, to the line amplifier input
`through bias capacitance C,, as shown in Fig. 8(a). The
`operation of the bias capacitance is illustrated in Fig. 8(b).
`When switch SI is on, the amplifier is biased at the cross
`point of the transfer curve of the amplifier and the line VIN
`= VoUT (auto-zero biasing) [16]. This point is near the
`power supply VD because the driver is PMOS. Next, when
`PMOS switch S, is off, the gate voltage raises from 0 V
`to VD and the input voltage of the amplifier also raises
`through the bias capacitance C,. As the signal has a minus
`charge, the maximum output voltage may be enlarged.
`Circuit simulation, in Fig. 8(c), indicates that the opti-
`mum value of the bias capacitance is 25 fF. Thus a
`2.6-V dynamic range is obtained.
`
`= - 1v
`vs, =5v
`
`C
`
`= 2 .lpF
`
`C , = 4 0 f F -
`
`30
`'0
`20
`10
`40
`COUPLING CAPACITANCE C,
`
`!
`( f F )
`
`(C)
`Fig. 8. Enlargement of dynamic range by bias capacitance Cu for line am-
`plifier. (a) Circuit diagram of line amplifier including bias capacitance C8.
`(b) Operation principle. (c) Bias capacitance dependence of bias voltage
`by circuit simulation.
`
`V . FIXED PATTERN NOISE
`Parallel readout-to-memory capacitance has advantages
`such as noise band reduction and smear merge time re-
`duction. However, this causes fixed pattern noise that is
`not nuniform with the output voltage of each line due to
`varying size and threshold voltage. In this section, the
`nonuniform output voltage of each line, both in the dark
`and in light, are discussed in terms of their origin and
`suppression methods.
`
`A. Fixed Pattern Noise in the Dark
`There are two origins for fixed pattern noise in the dark.
`One is from the dc output voltage of each amplifier. An-
`other is due to the feedthrough charge of each switch,
`which is a part of the inversion layer charge merging into
`a capacitance (including bias charge by bias capacitance
`C, described in Section IV). The noise voltage referred
`to the input of the line amplifier for the dc output voltage
`of each amplifier VNFA can be expressed as
`
`(6)
`VNFA = F06Vo.
`In (6), V, is the dc output voltage of each amplifier and
`Fo is reference coefficient to the input of the line ampli-
`fier. The noise voltage referred to the input of the line
`amplifier for the feedthrough charge of each switch VNFs
`can be expressed as
`VNFS = FF6(qF/cS)*
`
`(7)
`
`1029-005
`
`

`
`914
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38. NO. 5. MAY 1991
`
`In equation (7), qF is the feedthrough charge, Cs is the
`voltage conversion coefficient, and FF is the reference
`coefficient to the input of the line amplifier. As in the case
`of random noise, noise voltage can be converted to noise
`current by (3).
`The reference coefficients Fo, FF, are given in Table 111.
`The noise, other than from the line amplifier, due to switch
`SI, and bias capacitance C, is reduced as the voltage gain
`of the line amplifier increases. The CDS circuit sup-
`presses the noises from the line amplifier, switch SI, and
`bias capacitance C,. The differential circuit can eliminate
`the noises except for those from switches S3 and S,. The
`dc output voltage of the buffer amplifier does not affect
`the device output voltage. This is because the input of the
`buffer amplifier is virtually grounded due to a high open-
`loop voltage gain CO, of the amplifier (39 in design). Thus
`the readout voltage from the memory capacitance C,, or
`C,,
`is forced to be equal to the read-in voltage (offset-
`free buffer) [ 171.
`The calculated value of fixed pattern noise in the dark
`is shown in Table IV. It was assumed that the variation
`of size is 0.05 pm and the variation of the threshold volt-
`age was 30 mV. Total fixed pattern noise was 2000 PA,
`which is more than a hundred times as large as the inter-
`line-CCD’s nonuniform dark current of each pixel [6].
`Thus fixed pattern noise in the dark limited the signal-to-
`noise ratio achieved by the device. The primary contrib-
`utors to the fixed pattern noise are switches S3 and S,. One
`the noise but increases it by a factor of A. Secondly,
`reason for this is that the differential does not eliminate
`switches S3 and S4 have a long-channel length (NMOS’ is
`32 pm, PMOS’ is 9 pm, and NMOS is mainly on in the
`dark) in order to realize a high on-resistance for random
`noise bandwidth reduction. The total fixed pattern noise
`could be reduced by a factor of 15 ( 1 30 PA) by using a
`shorter channel length (1.5 pm) to decrease the feed-
`through charge and by inserting a high resistance polysil-
`icon into the signal path for bandwidth restriction. After
`this improvement, the total fixed pattern noise is esti-
`mated at 550 PA. Achievement of CCD’s noise level
`needs additional 1 /20 noise reduction.
`
`B. Fixed Pattern Noise in Light
`Fixed pattern noise in light stems from nonuniformity
`of the gain of each amplifier, shown as
`SG/ G .
`( 8)
`Here G is the amplifier gain. Table V summarizes the
`suppression method and its effect. A capacitance feedback
`circuit is used for the line amplifier, shown in Fig. 2. In
`this circuit, gain (voltage conversion coefficient) is de-
`cided by feedback capacitance value CF by using a high
`open-loop gain G O F for the amplifier (300 in design). This
`feedback capacitor is formed between the layer of alu-
`minum and the diffused layer which results in a minimum
`capacitance value per unit area in this device. As a result,
`the size of the capacitance CF can be enlarged (41 pm X
`10.5 pm) to reduce the percentage of nonuniformity.
`
`TABLE Ill
`SUPPRESSION METHODS FOR FIXED PATTERN NOISE IN THE DARK
`
`Noise from DC Output of Each Amplifier
`
`Source
`
`Line amplifier
`Source-follower
`
`Buffer amplifier
`
`Suppression
`Method
`
`CDS circuit
`line amplifier
`differential
`line amplifier
`offset free buffer
`differential
`
`Reference Coefficient Fo
`
`0
`l / G F e x p ( - D / 2 0 )
`
`I / G F X GOB (1 + CST/CM)
`x exp ( - D / 2 0 )
`
`~
`
`~~
`
`~~
`
`GF Gain of line amplifier.
`D
`Differential factor.
`GOB Open-loop gain of buffer amplifier.
`C,, Storage capacitance at input of buffer amplifier.
`C, Memory capacitance.
`
`~ Noise from Feedthrough Charge of Each Switch
`
`Source
`
`SI, C B
`
`s2
`
`s3 + s4
`S6
`
`Suppression
`Method
`
`CDS circuit
`differential
`line amplifier
`differential
`line amplifier
`line amplifier
`differential
`
`Reference Coefficient FF
`
`l/GF exp (-2rfC-Ts) X exp
`(- D / 2 0 )
`1 / G F exp ( - D / 2 0 )
`I / G - x J3
`1 / G F exp ( - D / 2 0 )
`
`GF Gain of line amplifier.
`T, Sampling period.
`f,-- Cutoff frequency for line amplifier.
`D Differential factor.
`
`TABLE 1V
`CURRENT OF FIXED PATTERN NOISE IN THE DARK,
`ASSUMING SIZE VARIATION OF 0.05 pl AND
`THRESHOLD VOLTAGE VARIATION OF 30 mV
`
`Source
`
`Noise Current (PA)
`
`Line amplifier
`Source-follower
`Buffer amplifier
`Output source-follower
`s,
`SZ
`s3 + s 4
`S6
`Total
`
`0
`536
`23
`7.5
`21
`11
`1930
`5.6
`2000
`
`The driver of the source-follower is formed in a sepa-
`rated well which is connected to the output of the source-
`follower, as shown in Fig. 3(b). As a result, the circuit is
`free from the body effect and its voltage gain is unity
`(0.984 in design), not depending on the device constant.
`The buffer amplifier has a unity gain circuit configura-
`tion, as described in Section V-A [17]. Gain is unity, re-
`gardless of the device constant, if the open-loop gain of
`the amplifier G O B is high enough.
`The calculated fixed pattern noise in light is shown in
`Table VI. The total noise is 0.62%. This value is still
`
`1029-006
`
`

`
`TABLE V
`SUPPRESSION METHODS FOR FIXED PATTERN NOISE IN LIGHT
`
`Source
`
`Suppression Method
`
`Gain
`
`Line amplifier
`
`capacitance feedback
`
`Source-follower
`
`driver in well
`
`Buffer amplifier
`
`unity gain buffer
`
`Qs
`CV/GOF + CF (1 + ~ / G o F )
`I
`
`Qs Signal charge.
`Capacitance of vertical signal line.
`C ,
`Go, Open loop gain of line amplifier.
`C,
`Feedback capacitance.
`Mutual conductance of source-follower driver.
`g,,,,,
`rOs Output resistance of source-follower.
`GOB Open-loop gain of buffer amplifier.
`C, Memory capacitance.
`Csr Storage capacitance at input of buffer amplifier.
`
`TABLE VI
`FIXED PATTERN NOISE VALUE IN LIGHT, ASSUMING SIZE
`VARIATION OF 0.05 pm A N D THRESHOLD VOLTAGE VARIATION OF
`30 mV
`
`Source
`
`Line amplifier
`
`Source-follower
`Buffer amplifier
`
`GO,
`C"
`CF
`
`R,"US ros
`GO8
`CM
`CS,
`
`Noise Value (%)
`
`0.35
`0.19
`0.42
`0.084
`0.20
`0.009
`0.012
`
`Total
`
`0.62
`
`TABLE VI1
`CALCULATE11 CHARACTERISTICS OF LAM
`
`Image format
`Number of pixels
`Pixel size
`Aparuter ratio
`Random noise
`Fixed patter noise
`dark
`light
`Smear
`Saturation signal current
`Power supply
`Technology
`
`1 / 2 in
`500(H) x 485(V)
`13(H) x IO(V) pm'
`71 '%
`120 pA (3 MHz)
`
`2000 pA
`0.62%
`100 dB ( I / I O V)
`500 nA
`s v
`I .S-pm CMOS
`
`three times as large as that of the interline-CCD [ 6 ] , but
`low enough for ordinary use.
`
`VI. CONCLUSION
`A new MOS imaging device is proposed. It has an am-
`plifier and a CDS circuit at each vertical signal line and
`off-chip smear differential gear. The calculated character-
`istics of this device for 1/2-in image format with 500 x
`485 pixels are given in Table VII. The signal-to-random-
`noise ratio is the same as in the interline-CCD. The smear
`
`915
`
`level and saturation signal current are higher than in the
`interline-CCD. These characteristics would be suitable for
`realizing smaller pixels suitable for higher packaging
`densities. However, one problem which remains to be
`solved is the fixed pattern noise in the dark condition.
`
`ACKNOWLEDGMENT
`The authors wish to thank the engineers in the process
`integration center in the Central Research Laboratory and
`Dr. Wada for their support in process design and device
`fabrication, and N. Ozawa for his advice concerning off-
`chip signal processing circuits.
`They also wish to thank Dr. Y. Nagata and Dr. T. Ma-
`suhara for their continuous encouragement and useful
`suggestions.
`
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`1029-007