EXHIBIT 1027
`
`RENSHAW et al., “ASIC Image Sensors,” IEEE International Symposium on
`
`Circuits and Systems, 1-3 May 1990, pp. 3038-3041 Vol. 4 (1990)
`
`
`
`
`
`TRW Automotive U.S. LLC: EXHIBIT 1027
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NUMBER 8,599,001
`IPR2015-00436
`
`

`
`ASIC IMAGE SENSORS
`ASIC IMAGE SENSORS
`
`D . Renshaw, P . B . Denyer, G. Wang & M . Lu
`D. Renshaw, P. B. Denyer, G. Wang & M. Lu
`
`Department of Electrical Engineering, University of Edlnburgh,
`Department of Electrical Engineering, University of Edinburgh,
`King's Buildings, Mayfield Road, Edinburgh.
`King's Buildings, Mayfield Road, Edinburgh.
`
`51 : ABSTRACT
`sl : ABSTRACT
`This paper describes two image array sensors designed and
`This paper describes two image array sensors designed and
`fabricated using a standard 2 level metal ASIC CMOS
`fabricated using a standard 2 level metal ASIC CMOS
`process. The results show that (i) good quality, grey-level
`process. The results show that (i) good quality, grey-level
`images can be formed and (ii) CMOS sensor arrays can be
`images can be formed and (ii) CMOS sensor arrays can be
`successfully
`integrated with efficient analogue sense
`successfully integrated with efficient analogue sense
`amplifiers and with digital controvimage processing logic.
`amplifiers and with digital control/image processing logic.
`The first sensor is a proto-type 128x128 pixel test arfay.
`The first sensor is a proto-type 128x 128 pixel test array.
`The second is a 312x287 pixel image sensor chip, which
`The second is a 312x 287 pixel image sensor chip, which
`includes all the necessary circuitry to produce full PAL
`includes all the necessary circuitry to produce full PAL
`format video output, as well as automatic, electronic
`format video output, as well as automatic, electronic
`exposure control and built-in test circuits. Test results
`exposure control and built-in test circuits. Test results
`characterising the devices are also given, covering
`characterising the devices are also given, covering
`dynamic range, spectral response, sensitivity, resistance to
`dynamic range, spectral response, sensitivity, resistance to
`blooming etc. Finally, some potential applications for
`blooming etc. Finally, some potential applications for
`such devices are mentioned.
`such devices are mentioned.
`
`s2 : INTRODUCTION
`§2 : INTRODUCTION
`
`In a standard, low-cost ASIC CMOS process there are
`In a standard, low-cost ASIC CMOS process there are
`three possible photodetector device structures available :
`three possible photodetector device structures available :
`photoconductor, photo-diode and photo-transistor. Fac-
`photoconductor, photo-diode and photo-transistor. Fac-
`tors affecting the choice of device include device area,
`tors affecting the choice of device include device area,
`response time, and gain. The theory of operation of these
`response time, and gain. The theory of operation of these
`devices and design using them are well documented [7].
`devices and design using them are well documented [7].
`Photoconductors are unsuited to use in array sensor dev-
`Photoconductors are unsuited to use in array sensor dev-
`ices, due to large area and slow response time. Compar-
`ices, due to large area and slow response time. Compar-
`ing photodiode with phototransistor, the photodiode has
`ing photodiode with phototransistor, the photodiode has
`advantages of simpler structure, smaller area and faster
`advantages of simpler structure, smaller area and faster
`response time. The phototransistor benefits from greater
`response time. The phototransistor benefits from greater
`gain but its use in array devices is complicated by inevit-
`gain but its use in array devices is complicated by inevit-
`able device and operating condition variation. For these
`able device and operating condition variation. For these
`reasons the photodiode is the basic sensing element used
`reasons the photodiode is the basic sensing element used
`in both designs.
`in both designs.
`
`5 3 : SENSOR I
`§3 : SENSOR I
`- Design :- Our first CMOS sensor chip comprises a
`- Design :- Our first CMOS sensor chip comprises a
`1 2 8 ~ 128 pixel photodiode array, which includes all the
`128x 128 pixel photodiode array, which includes all the
`address, sense and amplification circuitry necessary to pro-
`address, sense and amplification circuitry necessary to pro-
`vide a self-scanned 1 volt peak-to-peak grey-level output
`vide a self-scanned 1 volt peak-to-peak grey-level output
`signal. The device was designed and built specifically to
`signal. The device was designed and built specifically to
`test the suitability of a standard CMOS ASIC process for
`test the suitability of a standard CMOS ASIC process for
`image sensing, with the eventual aim of developing low-
`image sensing, with the eventual aim of developing low-
`cost, low-power ASIC image processing and sensing chips.
`cost, low-power ASIC image processing and sensing chips.
`
`Solid state image sensors have been designed and demon-
`Solid state image sensors have been designed and demon-
`strated by various researchers and companies. Available
`strated by various researchers and companies. Available
`devices e.g., [1,2,3] are capable of delivering good qual-
`devices e.g., [1,2,3] are capable of delivering good qual-
`ity grey-level images. They use either CCD or photo-
`ity grey-level images. They use either CCD or photo-
`diode array technologies, which are non-standard MOS
`diode array technologies, which are non-standard MOS
`Imaging DRAM devices
`processes.
`[4], using MOS
`processes. Imaging DRAM devices [4], using MOS
`memory processes, have also been demonstrated but are
`memory processes, have also been demonstrated but are
`unsuitable for many applications, as they give binarized,
`unsuitable for many applications, as they give binarized,
`rather than grey-level data. Other MOS sensors [9]
`rather than grey-level data. Other MOS sensors [9]
`require off chip sense and amplification circuitry. Some
`require off chip sense and amplification circuitry. Some
`researchers have developed special purpose image sensors
`researchers have developed special purpose image sensors
`[5,6,8] using low cost ASIC CMOS processes. These
`[5,6,8] using low cost ASIC CMOS processes. These
`devices, although very interesting architecturally and use-
`devices, although very interesting architecturally and use-
`ful for single, specific functions, do not demonstrate good
`ful for single, specific functions, do not demonstrate good
`quality general-purpose grey-level image sensing capabil-
`quality general-purpose grey-level image sensing capabil-
`ity.
`ity.
`A major disadvantage of all commercially available image
`A major disadvantage of all commercially available image
`sensors chips is their requirement for off-chip sense andor
`sensors chips is their requirement for off-chip sense and/or
`amplification circuitry, for off-chip dgital control circui-
`amplification circuitry, for off-chip digital control circui-
`try, and for multiple supply voltage levels. The experi-
`try, and for multiple supply voltage levels. The experi-
`mental work reported here demonstrates that good quality
`mental work reported here demonstrates that good quality
`images can be obtained from devices fabricated on a stan-
`images can be obtained from devices fabricated on a stan-
`dard, low-cost ASIC CMOS process, that they require
`dard, low-cost ASIC CMOS process, that they require
`very low power, single voltage supply and that the analo-
`very low power, single voltage supply and that the analo-
`gue and digital circuitry required to provide the complete
`gue and digital circuitry required to provide the complete
`Figure 1 : CMOS sensor pixel & sense amplifier.
`sensor function can be integrated on the chip.
`Figure 1 : CMOS sensor pixel & sense amplifier.
`sensor function can be integrated on the chip.
`CH2868-8/90/0000-303$1.00 0 1990 IEEE
`CH2868-8190/0000-3038$1.00 © 1990 IEEE
`
`SENSE AMPLIFIER
`
`FET SWITCH
`
`FOR RESET & READ
`
`\
`
`-DIODE
`I'HO1'0
`
`1027-001
`
`

`
`'I'lic sensor circuit used is shown in Figure I . In opera-
`The sensor circuit used is shown in Figure I. In opera-
`tion, the photodiode capacitor is reset to a voltage refer-
`tion, the photodiode capacitor is reset to a voltage refer-
`ence level v,~, by opening the FET switch. This stores a
`ence level v,,, by opening the FET switch. This stores a
`fixed charge on the capacitor. The photodiode and capa-
`fixed charge on the capacitor. the photodiode and capa-
`citor are then isolated. Photocurrent, produced by the
`citor are then isolated. Photocurrent, produced by the
`cftcct of photons impinging on the diode, discharges the
`effect of photons impinging on the diode, discharges the
`capacitor. The rate of discharge is proportional to the
`capacitor. The rate of discharge is proportional to the
`photocurrent, which is in turn proportional to the incident
`photocurrent, which is in turn proportional to the incident
`light level. The final charge retained on the capacitor,
`light level. The final charge retained on the capacitor,
`after a fixed time interval will represent the light intensity
`after a fixed time interval will represent the light intensity
`at that point of the image. Thus the photodiode must be
`at that point of the image. Thus the photodiode must be
`accessed through the FET switch after a fixed time inter-
`accessed through the FET switch after a fixed time inter-
`val and the remaining charge sensed; this is the read
`val and the remaining charge sensed; this is the read
`operation. Key to the success of operation is the perfor-
`operation. Key to the success of operation is the perfor-
`mance of the charge sensing function. Pixel design was
`mance of the charge sensing function. Pixel design was
`contained by a 20km pitch in both X and Y dimensions.
`contained by a 20p„m pitch in both X and Y dimensions.
`('l'liis may be tailored in application specific redesign.)
`(This may be tailored in application specific redesign.)
`'I'he sensor architecture is shown in Figure 2.
`The sensor architecture is shown in Figure 2.
`
`WIZON•I'A . SIIIITf REGISIF.5
`PS (cid:9)
`
`SAM
`
`OUTPUT
`AMPLIFIER
`
`A UA9)
`
`SENSEAMPLIFIERS
`
`OUTPUT
`
`A VIA)
`
`L
`
`crK11
`
`~-
`
`-___
`
`~~
`
`~
`
`Figure 3 : Prototype CMOS 1 2 8 ~ 128 sensor array.
`Figure 3 : Prototype CMOS 128 x 128 sensor array.
`
`- Test and Characterisation Results :- The design was
`- Test and Characterisation Results :- The design was
`fabricated using Es2 2 ~ m ASIC CMOS process. Samples
`fabricated using ES2 2p,m ASIC CMOS process. Samples
`(Figure 3 ) have been tested and characterised. Initial
`(Figure 3) have been tested and characterised. Initial
`testing included &splay of visual images on an oscilloscope
`testing included display of visual images on an oscilloscope
`screen, for frame rates of 60 f.p.s. To evaluate the qual-
`screen, for frame rates of 60 f.p.s. To evaluate the qual-
`ity achievable on a conventional monitor display, (Figures
`ity achievable on a conventional monitor display, (Figures
`4, 5) a PC with enhanced VGA was used together with
`4, 5) a PC with enhanced VGA was used together with
`an ADC and dedicated RAM frame-store interface. The
`an ADC and dedicated RAM frame-store interface. The
`images obtained displayed unexpectedly good grey-level
`images obtained displayed unexpectedly good grey-level
`quality, with excellent uniformity.
`quality, with excellent uniformity.
`
`Nix)
`
`CI.XV
`
`DONJ)
`
`VERTICAL min.
`REGISTER
`
`Figure 2 : CMOS sensor array architecture.
`Figure 2 : CMOS sensor array architecture.
`
`'I'lic pixels of a line of photodiodes are read and then
`The pixels of a line of photodiodes are read and then
`reset in parallel. The row-read operation uses a row of
`reset in parallel. The row-read operation uses a row of
`sensitive charge integrators to perform the essential
`sensitive charge integrators to perform the essential
`charge-sensing operation on-chip : a novel feature of this
`charge-sensing operation on-chip : a novel feature of this
`device. These sense amplifiers must be small enough to
`device. These sense amplifiers must be small enough to
`pitch-match the pixels, yet sensitive enough to give a good
`pitch-match the pixels, yet sensitive enough to give a good
`signal to noise ratio on the sensed signal; they must also
`signal to noise ratio on the sensed signal; they must also
`hc insensitive to at least the first order process parameter
`he insensitive to at least the first order process parameter
`variations. The results of the read operation are held
`variations. The results of the read operation are held
`cqxicitively and then read out sequentially through an
`capacitively and then read out sequentially through an
`output amplifier, to give a line scan. Each line is
`output amplifier, to give a line scan. Each line is
`accessed in sequence.
`(Alternative application specific
`accessed in sequence. (Alternative application specific
`reclcsigns could allow parallel read out of the full line, or
`redesigns could allow parallel read out of the full line, or
`pirt of it.) The chip is supplied with clock and initialisa-
`part of it.) The chip is supplied with clock and initialisa-
`tion signals and a single 5 volt supply. The read-out rate
`tion signals and a single 5 volt supply. The read-out rate
`ancl exposure (integration) time are variable. The small
`and exposure (integration) time are variable. The small
`active area (11 sq. mm.) allows for integration of other
`active area (11 sq. mm.) allows for integration of other
`processing logic.
`processing logic.
`
`3039
`3039
`
`Figure 4 : Grey-scale image formed by 128X 128 pixel
`Figure 4 : Grey-scale image formed by 128x 128 pixel
`prototype sensor.
`prototype sensor.
`
`1027-002
`
`

`
`s4 : SENSOR 2
`§4 : SENSOR 2
`- Design :- The second sensor (Figure 7) has been
`- Design :- The second sensor (Figure 7) has been
`designed to demonstrate the potential of ASIC CMOS for
`designed to demonstrate the potential of ASIC CMOS for
`building fully
`integrated image sensor-processors.
`It
`building fully integrated image sensor-processors. It
`comprises a 312x287 pixel photodiode array, similar to
`comprises a 312x287 pixel photodiode array, similar to
`that in Sensor 1. In addition to the basic sense and con-
`that in Sensor 1. In addition to the basic sense and con-
`trol circuits used in sensor 1 there are circuits which pro-
`trol circuits used in sensor 1 there are circuits which pro-
`vide the following functions:
`vide the following functions:
`256x256 selected scan image output
`I .
`1. 256 x 256 selected scan image output
`full interlaced video format (CCITT) output
`2.
`2.
`full interlaced video format (CCII'l) output
`electronically adjustable exposure (via control
`3.
`3. electronically adjustable exposure (via control
`of integration time)
`of integration time)
`automatic electronic control of exposure setting
`4.
`4. automatic electronic control of exposure setting
`These additional functions are provided through a 4,000
`These additional functions are provided through a 4,000
`gate processor, adjacent to the sensor array. This device
`gate processor, adjacent to the sensor array. This device
`is, therefore, a single chip video camera : provided with a
`is, therefore, a single chip video camera : provided with a
`5 volt power supply and focused light images it provides a
`5 volt power supply and focused light images it provides a
`black and white CCI7T format video output. To our
`black and white CCITI format video output. To our
`knowledge, all previously developed video imagers require
`knowledge, all previously developed video imagers require
`one or more boards of surface mount components to
`one or more boards of surface mount components to
`achieve this. This design has been completed and is at
`achieve this. This design has been completed and is at
`present in fabrication. Details of
`the design and test
`present in fabrication. Details of the design and test
`results can be summarised at the Symposium.
`results can be summarised at the Symposium.
`
`~5 : CONCLUSIONS
`§5 : CONCLUSIONS
`
`The design and performance of ASIC CMOS VLSI image
`The design and performance of ASIC CMOS VLSI image
`sensors has been reported here. Extension of the design
`sensors has been reported here. Extension of the design
`to produce integrated ASIC sensor-processors has also
`to produce integrated ASIC sensor-processors has also
`been described. Their features of low cost processing
`been described. Their features of low cost processing
`technology, single low-voltage supply requirement, low
`technology, single low-voltage supply requirement, low
`power dissipation and potential for integration of digital
`power dissipation and potential for integration of digital
`logic demonstrate the viability of CMOS for single chip
`logic demonstrate the viability of CMOS for single chip
`combined image sensing and processing devices. In the
`combined image sensing and processing devices. In the
`near future, as a development of this, we may expect to
`near future, as a development of this, we may expect to
`see an increasing number of products based on such tech-
`see an increasing number of products based on such tech-
`nology. Applications would include security and surveil-
`nology. Applications would include security and surveil-
`lance cameras, remote sensing devices and special purpose
`lance cameras, remote sensing devices and special purpose
`image sensor-processors, where tailoring of the archi tec-
`image sensor-processors, where tailoring of the architec-
`ture of the sensor or its interface gives real advantages.
`ture of the sensor or its interface gives real advantages.
`
`- ACKNOWLEDGEMENTS -
`- ACKNOWLEDGEMENTS -
`
`We would like to thank D.Suen and C.H. Lau for techni-
`We would like to thank D.Suen and C.H. Lau for techni-
`cal contributions. We acknowledge the co-operation of
`cal contributions. We acknowledge the co-operation of
`the South-Eastern University of China, Nanjing, for
`the South-Eastern University of China, Nanjing, for
`seconding G. Wang & M. Lu as Visiting Academics. We
`seconding G. Wang & M. Lu as Visiting Academics. We
`acknowledge support received from the University of
`acknowledge support received from the University of
`Edinburgh Quantum Fund and from the Science 6i
`Edinburgh Quantum Fund and from the Science &
`(Grant GFUF 36538
`Engineering Research Council
`Engineering Research Council (Grant GRP 36538
`IED2/1/1159).
`IED2/1/1159).
`
`Figure 5 : Grey-scale image formed by 128 x 128 pixel
`Figure 5 : Grey-scale image formed by 128x 128 pixel
`prototype sensor.
`prototype sensor.
`
`In order to characterise the imager, an optical test meas-
`In order to characterise the imager, an optical test meas-
`urement set-up, was used. Table 1 (at the end of this
`urement set-up, was used. Table 1 (at the end of this
`paper) summarises the measured results of the perfor-
`paper) summarises the measured results of the perfor-
`mance characterisation experiments. There was no
`mance characterisation experiments. There was no
`observable cross-talk, ghosting or smear. Anti-blooming
`observable cross-talk, ghosting or smear. Anti-blooming
`performance is comparable with commercially available
`performance is comparable with commercially available
`CCD and photodiode devices. Over-exposure on one
`CCD and photodiode devices. Over-exposure on one
`frame has no measurable persistence effect on subsequent
`frame has no measurable persistence effect on subsequent
`frames. The sensitivity and spectral response (Figure 6)
`frames. The sensitivity and spectral response (Figure 6)
`are particularly well suited to the visible spectrum and
`are particularly well suited to the visible spectrum and
`exhibit only low ripple (probably due to effects in the pas-
`exhibit only low ripple (probably due to effects in the pas-
`sivation layer). Performance is well maintained over a
`sivation layer). Performance is well maintained over a
`range of operating supply voltages (3.5V - 12V) and tem-
`range of operating supply voltages (3.5V - 12V) and tem-
`peratures. Notably the entire sensor system may be
`peratures. Notably the entire sensor system may he
`operated successfully from a single 5V supply.
`operated successfully from a single 5V supply.
`RESPONSE
`RESPONSE
`
`(V./1.1.Wcm2)
`
`(V&Wm2) 1
`012 -
`
`0.14 -
`
`0.12 -
`
`0.10 -
`oln -
`
`0.08 -
`0.08 -
`0.06 -
`
`0.06 -
`
`0.02 -
`
`004 -
`0.04 -
`0.02 -
`0
`1
`300
`300 (cid:9)
`
`
`
`ASIS-1030
`
`COMMERCIAL.
`CCU
`
`I
`400
`400 (cid:9)
`
`I
`500
`5(61 (cid:9)
`
`I
`600
`600 (cid:9)
`
`I
`700
`700
`
`I
`XW
`800
`
`I
`900
`900 (cid:9)
`
`I
`1000
`10(X1
`
`2L(1161)
`
`Figure 6 : Comparison of spectral response of 128x 128 pixel
`Figure 6 : Comparison of spectral response of 128x 128 pixel
`prototype sensor with that of' a commercial CCD device.
`prototype sensor with that of a commercial CCD device.
`
`3040
`3040
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`1027-003
`
`(cid:9)
`(cid:9)
`

`
`References
`References
`sensor, Mullard
`I .
`Frciiiie
`trcuzsfer
`I. Frame transfer sensor, Mullard
`clcvclopment data, 1985.
`development data, 1985.
`Iiiiage Sensing Products, EG&G
`2.
`Image Sensing Products, EG&G
`2.
`lieticon, 1988.
`Rcticon, 1988.
`Seiiiicorzductor Products List, Sony,
`3.
`3. Semiconductor Products list, Sony,
`1088.
`1988.
`Ciarcia, in BYTE, pp. 21-31, Sept,
`4.
`4. Ciarcia, in BYTE, pp. 21-31, Sept,
`1083.
`1983.
`Lyon, in ChfU VLSl Corfereizce, pp.
`5.
`5. Lyon, in CMU VLSI Conference, pp.
`1-19, 1981.
`1-19, 1981.
`Mcad, Aiznlog VLSl & izeurnl sys-
`0 .
`6. Mead, Analog VLSI & neural sys-
`1c111s. Addison-Wesley, 1989.
`tems. Addison-Wesley, 1989.
`7.
`Szc, IJiiysics cf sei~~icoizductor dev-
`Sze. Physics of semiconductor dev-
`;(w, pp. 743-789, Wiley, 1981.
`ices, pp. 743-789, Wiley, 1981.
`I-latficld, et. al., in ESSCIRC'88, pp.
`I latfield, et. al., in ESSCIRC'88, pp.
`339-342, 1988.
`339-342, 1988.
`Kinugasa, ct. al., Z.E.E.E Trans.
`Kinugasa, et. al., 1.E.E.E Trans.
`Comuriier Electronics, vol. CE-33,
`Consumer Electronics, vol: CE-33,
`pp. 240-255, Aug, 1987.
`pp. 249-255, Aug, 1987.
`
`x.
`
`9.
`
`TABLE 1
`TABLE I
`
`Parameter
`Parameter (cid:9)
`
`Minimum
`Minimum (cid:9)
`
`Nominal
`Nominal (cid:9)
`
`Maximum
`Maximum (cid:9)
`
`Units
`Units
`
`Integration time
`Integration time
`Refresh rate
`Refresh rate
`OiP voltage swing
`0/P voltage swing
`(peak to peak)
`(peak to peak)
`Operating voltage
`Operating voltage
`Power dissipation
`Power dissipation
`SNR (measured)
`SNR (measured)
`Blooming protection?
`Blooming protectiont
`Dark current 3
`Dark current *
`Operating
`Operating
`Temperature range
`Temperature range
`
`I
`
`17.5
`17.5
`3.3
`3.3
`
`3.5
`3.5
`
`< -20
`<-20
`
`I
`
`I
`
`1.0
`1.0
`
`5.0
`5.0
`3.0
`3.0
`51
`51
`500 x
`500x
`0.01
`0.01
`
`25
`25
`
`300
`300
`57
`57
`
`12.0
`12.0
`
`+ 80
`+80
`
`I
`
`ms
`ms
`frameslsec
`frames/sec
`Volts
`Volts
`
`Volts
`Volts
`mW
`mW
`dB
`dB
`
`$
`
`"C
`°C
`
`Over-exposure which causes a small bright spot to form a detectable streak.
`fi Over-exposure which causes a small bright spot to form a detectable streak.
`3 Dark current, measured at 25"C, expressed as % of saturation exposure
`Dark current, measured at 25°C, expressed as % of saturation exposure
`over an integration time of 20 msec.
`over an integration time of 20 msec.
`
`Figure 7 : Integrated ASIC camera chip
`Figure 7 : Integrated ASIC camera chip
`
`3041
`3041
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`1027-004