EXHIBIT 1019
`
`P. FRY and P. NOBLE, “Fixed Pattern Noise in Photomatrices,”
`
`IEEE JSSC, Vol. SC-5, No.5, Oct. 1970
`
`
`
`
`
`TRW Automotive U.S. LLC: EXHIBIT 1019
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NUMBER 8,599,001
`IPR2015-00436
`
`

`
`250
`
`IEEIIJOURN.tLOF SOLID-STATECIRCUITS,VOL.SC-5,NO. fi,OC’I!OBEB1970
`
`Fixed-PatternNoise in Photomatrices
`
`PETER W. FRY, PETER J. W. NOBLE, AND ROBERT J. RYCROFT
`
`Abstract-Two MOS photomatrixconfigurations,voltage sam-
`pling and recharge sampliig, have been comparedwith regard to
`sources of fixed-patternnoise (FPN). Voltage sampling provides a
`high-amplitude low-impedance photosignal, with FPN primarily
`due to threshold variation in the amplifying MOST at each element.
`Recharge sampling is used for large high-yield rapidly scanned
`arrays, with FPN caused mostly by variations in spurious capacitive
`breakthrough. Production peak-to-peak signal to FPN ratios are
`20:1 for voltage sampling and 50:1 for recharge sampling.
`
`INTRODUCTION
`
`v ARIOUS photomatrices have been under develop-
`
`ment for the past 5–7 years [1]–[61. Until recently
`they have formed the basis of considerable research
`and development programs but, with the exception of the
`electron-beam-scanned
`array [7], have not been applied
`to real environments such as steel mills, computer periph-
`erals, etc.
`However, with many teams actively applying photo-
`matrices to pattern recognition,
`especially optical char-
`acter recognition, measurement, position sensing, edge
`sensing, etc., the authors consider that the time has come
`to define various relevant parameters of signals that are
`obtained from such arrays, with particular regard to the
`signal-to-noise ratios (SATR)obtained. This paper attempts
`to classify the sources of noise present in some forms of
`photodiode
`arr~ys with integral
`lMOS switching
`and
`amplification that are currently being manufactured. 1
`We would suggest that the following standard nomen-
`clature be adopted to simplify future correspondence.
`1) Video Window (VW): Peak-to-peak
`signal obtain-
`able from an array, or the output swing between dark and
`overload conditions.
`output
`(FPN): Peak-to-peak
`.2) Fixed-Pattern Noise
`signal of a fixed pattern nature, obtained under uniform
`(or zero) illumination of all photodiodes.
`3) Signal-to-Noise Ratio (A’NR): The VW/FPN ratio
`VW/FPN.
`It is not intended in this paper to dwell on the various
`external
`(or internal) methods of reducing FPIS. It is
`sufficient
`to say that FPN has been reduced by the
`authors to <1 mV giving SNR of 10 000:1. However,
`this involves
`a complex array and external
`circuitry.
`It is also acknowledged that, with the recharge array,
`virtually all switching spikes can be eliminated by signal
`processing. The point of this paper, however,
`is to show
`
`Manuscript received May 4, 1970; revised lMay 27, 1970.
`The authors are with Integrated Photomatrix, Ltd., The Grove
`Trading Estate, Dorchester, Dorset, England.
`1For example, IPL 20, a 50 X 1 array with integral scanning,
`Integrated Photomatrix, Ltd.
`
`that acceptable video signals can be obtained by relatively
`simple arrays, with high yield for production purposes.
`
`VOLTAGESAMPLING
`The basic element of one major type of photodiode array
`is illustrated in Fig, 1. This consists of the photodiode D,
`the recharging switch M,, amplifying transistor M, and
`output switch Ms. This is the typical format for a voltage-
`sampled element of an array. The array is scanned by
`means of an MOS shift register/ring
`counter providing
`sequential switching pulses to lines n and n + 1. The
`operation is such that when n + 1 is switched, the diode
`capacitance CD is charged to a negative potential VDC.
`The remaining diodes in the array are then charged
`sequentially until
`line n is switched. This turns M3 on
`thus providing a current path via ill,, M,, and RL and
`giving rise to a voltage VO,$across RL. RL is common to
`the entire array and is generally external,
`Ideally V..,
`should bear a linear relationship to incident illumination
`integrated
`over a scan period. Whereas all voltages
`referred to are negative relative to earth, this has been
`ignored in order
`to simplify the presentation. Where
`necessary, sign reversals are used, but
`the conclusions
`are still valid since differences in voltage
`(signal) are
`derived.
`
`v out = M(VD, + K)
`Vi), = VD.– v.
`
`V. = constant X
`
`t.
`
`/
`
`t,
`
`Pdt=PAt
`
`illumination where
`for steady
`is diode voltage after
`VD,
`discharge due to illumination, V. is voltage throug~ which
`the diode has decayed, P is light incident power at time t,
`At = t, – t, the integration period, M is the gain, and K
`the offset of the amplifying circuitry to the left of point A“.
`However,
`in practice various mechanisms give rise to
`errors that vary in random fashion over the array. These
`random errors set a lower limit
`to the light-intensity
`change required to obtain a meaningful change in output
`signal. Since they are a form of spatial noise that is fixed
`in position for any given array, they are given the name
`fixed-pattern noise (FPN).
`In the above, they correspond
`to variation in the constants V~c, K, and M, and in the
`coefficient of PAt.
`
`A. Diocle-Charging Le~’el VD~
`
`The diode will charge to a voltage dependent on the
`negative-rail voltage V~ ~ and the switching voltage V~
`on the gate of Ml.
`If V~ < V~~ + VTI then V~c, =
`
`1019-001
`
`

`
`FltY etd.:FIXED-PATTERNNOISEIN-PHOTOMATRICES
`
`251
`
`LineN+l
`--_, I
`
`-1
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`1
`
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`f
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`.-.
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`RL
`---
`
`Vout
`H
`
`or——-—...--.—–-_–.—-----------------
`,
`t
`i
`I
`
`i
`
`M2
`
`X*
`
`1I
`
`!
`1
`1(
`
`1 element
`L___._._. _.–.–._._._... _.._. –.-- ___._.---.4
`Fig. 1. Basic element.
`
`I
`I
`
`(which
`is the threshold voltage of Ml
`V. – V., where V,,
`is dependent
`is the
`and V~ct
`on source/substrate
`bias)
`voltage attained by D while Ml is on. When Ml is switched
`off as its gate voltage rises towards O volts, a positive
`voltage step is added to V~c, due to the gat~source
`capacitance Ccs of Ml.
`Given that the gate voltage of Ml rises by AV. z V.,
`and that
`the photodiode
`capacitance
`is CD (assumed
`constant as a first approximation),
`the step in voltage on
`the diode is approximately
`
`AV~ CQs _ AV~ C~,y
`CD+ CQS—
`c.
`“
`
`The final diode-charging voltage is therefore,
`
`Two sources of FPN affect the value of V~c. 1) VT, is
`not constant across the array. This is represented by a
`term AV,I in the following equation. 2) The ratio CQS/CD
`will vary across the array, mainly owing to variations in
`alignment, gate
`CGS, which is affected by gate-source
`metallization etching accuracy, etc. This is represented by
`the term AC@S.
`The final diode-charging voltage now becomes
`
`V.c = V. – (Vrl + AV,,)
`
`(C.. + AC..).
`– V. ——
`c.
`
`18 volts,
`volt and V.ct =
`< ~0.3
`In practice AV,,
`giving a 30:1 ratio of maximum signal peak-to-peak FPN
`due to AV,,. A voltage drop of about 6 volts in the
`following circuitry limits the final output swing to 12 volts,
`reducing this ratio to 20:1. If VL > VD D
`-!-- VT1,
`then
`V.ct = ~’DD and VDc = VDD – V./C~
`(CG. -t AC..).
`The first source of FPN is now eliminated; the second is
`still present, and so great care must be taken in design
`to ensure that ACQS/CD is minimized, bearing in mind the
`effects of mask alignment,
`etch undercutting,
`etc. A
`typical
`ratio obtained by the authors for this mode of
`
`where ID is the diode dark current and T is the integration
`period. Now CD = ACA, where CA is the diode junction
`capacitance per unit area and so we can eliminate area
`from the above equation to give
`
`where IDA is the dark current per unit area.
`Significant error,s between one diode of the array and
`the next occur in IDA and q, and possibly CA. The effect
`of IDA on I?PN is roughly inversely proportional
`to the
`photocurrent; the dark current level is typically equivalent
`to incident
`radiation of <10-7 W. cm-’
`(black body
`radiation at 2900°K), and variations are of the same order,
`so that by operating in excess of 10-5 W. cm-a of light
`FPN will be <1 percent of signal. These figures refer to
`room-temperature
`(20°C) operation.
`lD~ increases by a
`factor 10 with every 30”C rise in temperature.
`Variations in q and C. account for less than 1 percent
`signal-to-FPN ratio in diodes 75 microns
`square.
`of
`Statistical considerations show that these effects decrease
`with an increase in diode area.
`
`C. O#set in the Ampli$er Circuit K
`Let us assume that M,, when on, is a resistor of value
`R... The source voltage of M,, V,
`is given by
`
`where Va is the gate voltage of M2 (VG = V~ c — V.),
`is the threshold voltage of M,
`(including the effect of
`V,,
`source/substrate
`bias), p is the gain factor of M’, and
`Rz is the common load resistor.
`We will, for the present, assume the gain of this source–
`follower circuit to be unity, i.e., L?(R.. + R.) ~ ~.
`Hence V. = VG — V.,
`or, including a term AV,,
`represent the random variations in VT’,
`
`to
`
`operation is 100:1, which is quite acceptable
`purposes.
`
`for most
`
`B. Voltage Drop Caused by Illumination V,
`For simplicity let us assume that CD is independent of
`voltage. The photocurrent
`in the diode 1. is given by
`
`~ve
`
`I. = J“ AqhKP d~ = AK /“ qhP d~
`0
`o
`
`where A is the diode area, ~ is the quantum efficiency at
`wavelength k, P is the irradiant power per unit area per
`unit wavelength, K = e/he = 8.05 X 103A W-l. cm-l.
`
`—ve
`
`Therefore,
`
`Ip+ID_dV
`c.
`
`dt
`
`v. = # (1= + ID)
`
`D
`
`1019-002
`
`

`
`252
`
`-
`
`(V,, + AV,,).
`
`v, = V.
`The circuit. output voltage VOa,across Rfi is given by
`v
`,., = (V,RJ/(RL
`(ARon) in R.,, due to threshold
`We include variations
`voltage and gain factor variations in Ms, so that
`
`+ ROJ.
`
`The term in the first bracket has a typical value given by
`
`V@ = 18 volts
`v2i,= 5 volts
`AV~z = ~0.3 volts
`
`20 due to AV~~ alone.
`so that the peak signal/FPN ratios
`is affected by the
`The term in the second bracket
`designed ratio of R..
`to R.. A& has a worst case value
`50.1 R... Thus,
`if we design R..
`to be less than 0.1 RL,
`the variation in this term will be less than 2 percent
`of value.
`
`D. Gain M of the Ampli$er Circuit
`
`In the above calculation of amplifier offset, we assumed
`/3(R.n + R.) + co, making the source-follower gain unity.
`In fact, if we calculate the relationship between V, and V.
`from simple MOS theory, we obtain:
`
`“
`
`= ‘“
`
`1
`– ‘“2 + @(RO. + RJ
`
`.
`
`J“”1
`
`2(VG – v,,)
`~(ROn + R.)’ + 6(R.n + RJ
`
`and
`
`dvE_l _
`dv~
`
`1
`V’1 + 2(VG – VzJP(R.n + RL)”
`
`The errors in this gain due to AV,, and A& are dependent
`on the magnitude of the second term. Putting in typical
`values:
`
`IEEEJOURNALOF SOLID-STATECIRCUITS,OCTOBER1970
`
`able design optimization one of the main limitations in
`terms of FPN is due to threshold voltage variations in the
`amplifying MOST MZ, This assumes extreme care in the
`design and manufacture to limit capacity coupling effects.
`
`COMPARISONOF THEORETICAL FPN WITH
`PRACTICAL RESULTS
`
`The basic element shown in Fig. 1 has been used in the
`50 X 1 array now in full production by the authors’
`company (Fig. 2). 1 Typical
`figures established from over
`1000 arrays are as follows, with scan rates from 10 kHz
`to 1 MHz.
`
`Typical
`
`Best
`
`Peak video signal
`
`12
`
`14 volts
`
`Peak-to-peak
`FPN
`SNR
`
`+0.3
`20
`
`*O. 1 volt
`70
`
`(with –22 volts
`apphed to array)
`
`can be readily made
`It can be seen that photomatrices
`with SNR of 20 or more using the voltage-sampling
`technique.
`Fig. 3 shows an oscilloscope trace of a 50 X 1 video
`output. Diodes 1–25 show response to a circle of light of
`graded intensity imaged onto half of
`the array. The
`remaining portion of
`the video trace shows the FPN
`peculiar to diodes 26-50 of this array. Perhaps it is worth
`noting that this array is 22S X 42 roils and typically gives
`production yields in excess of 30 percent at probe test.
`It is now in use in OCR equipment as well as measurement,
`edge sensing, and inspection.
`
`RECHARGE SAMPLING
`
`If high (> 5 MHz) scanning rates and large arrays are
`required, it is often preferable to make use of the recharge-
`sampling technique. The circuit for this comprises Ml and
`D only of Fig. 1 (see Fig. 4). The negative rail is taken to
`a “virtual negative” amplifier input (i.e., a “virtual earth”
`with negative offset), and the charge necessary to reinstate
`the bias on the diode is the signal taken as the video
`output. Different noise conditions prevail.
`
`A. Diode Area and Quantum E&iency Eflects
`
`We are now measuring the charge, and not voltage;
`thus diode area becomes significant. Again
`
`P = 32 ~A/V’
`Ron = 5 kfi?
`R~ = 200 kQ
`VG = 10 volts
`V,2 = 5 volts
`
`G=
`dVG
`
`1 – (1/%/65)
`
`= 0.876,
`
`.02
`
`A ~ 0.3 volt change in VT, will change this by less
`than 0.6 percent. Changes in R.n will have negligible
`effect. The overall gain M is given by
`
`Let
`
`This is affected by R..
`in the same way as discussed under
`amplifier offset, giving a 2 percent peak signal to FI?N
`ratio when R.JRL = 0.1.
`Summarizing the above, we conclude that, given suit-
`
`Therefore,
`
`1P = AB.
`
`The total charge lost by the diode in period T is
`Q. = (L + 1.) T = (-D + ID)T.
`
`1019-003
`
`

`
`F~Yetal.: FI=D-PATTERNNOISEIN PHOTOMATRICES
`
`253
`
`. ....i
`
`...—
`
`_._.._T.__...i_
`J_D
`
`?’
`
`M
`
`Fig. 2. Self-scanned array.
`
`Fig. 3. Video output waveform.
`
`I. may be ignored since the main use of this technique is
`for high-speed sampling at high light
`level although
`low-speed applications do exist [9]. Therefore, Q. = ABT.
`Unlike the voltage-sampling
`system, the diode capaci-
`tance does not enter this equation; diode area does,
`however. Variations
`in B due to quantum efficiency v
`variations cannot be differentiated from variations in A.
`
`B. Capacitive Charge Breakthrough
`
`capacitance of M, will again transfer
`The gatesource
`charge to the diode when the gate goes positive at the end
`of
`the recharge pulse. An equal
`charge is, however,
`removed by the negative edge at the beginning of the next
`recharge pulse. No net charge is passed to the amplifier
`by this effect.
`of M, will, however,
`The
`gain–drain capacitance
`transfer a charge spike to the amplifier superimposed on
`the recharge signal at the beginning of the recharge pulse.
`Again an equal opposite charge spike occurs at the end of
`the cycle, superimposed on the signal and charge spike
`from the next array element. The net effect of the two
`opposing edges is to cancel the contribution due to CD(3
`(the nominal capacitance) but to leave that due to AC~G
`(the random variation):
`
`p..
`
`Line N
`
`—-——
`
`spike wt~ut
`
`Fig. 4.
`
`charge injected
`charge removed
`net charge (FPN)
`
`V~ (CD~ ~ AC~~)
`V~ (C~~ ~ AC~a)
`+ 2V~ AC~@,
`
`of diode
`Since capacitive breakthrough is independent
`area A, and area variation is roughly proportional to diode
`perimeter,
`it is apparent that A must be maximized for
`best results.
`The 50 X 1 array mentioned previously has also been
`used in the recharge mode and gives a typical peak
`signal/FPNT ratio of 70:1. Therefore,
`it is obvious that for
`best results the recharge principle is the best for most
`applications such as OCR. At present an array, based on
`the recharge technique,
`is being made for a particular
`OCR requirement. This has 5 parallel output
`lines of
`over 70 serially scanned diodes (i.e., over 350 diodes in all).
`At present
`thk device
`is in preproduction,
`but
`first
`samples are giving good SNR with scan rates of 5 MHz.
`Yield is such that 10-30 arrays 100 X 400 roils are being
`obtained at probe test from 2-inch slices. A new technique
`has been adopted for making thk array in that the scan-
`ning and array are processed on separate slices and
`interconnected at assembly. The array is an infinite array
`100-mils wide by 2 inches. Diodes are on 4-roil centers.
`The whole slice is probed in sections of 6 X 5 diodes and
`faulty sections marked by the prober. Then blocks of the
`correct size are cut from the slice. It is not unusual for
`flawless blocks up to 1 inch (250 diodes)
`in length to be
`found. Results are encouraging for photomatrices now
`in design, which include 32 X 32 arrays.
`
`CONCLUSIONS
`
`the authors draw from the
`that
`conclusion
`The basic
`is that by careful design and selection
`of
`the
`foregoing
`most appropriate methods
`of scanning,
`acceptable
`SNR
`can be achieved without
`recourse
`to excessive
`external
`signal processing.
`gives consistent SNR
`technique
`The voltage-sampling
`of 20:1 and 35:1 and can be selected at about 1W15 percent
`of production level. This is adequate for all OCR and
`most measurement systems of which the authors have
`knowledge. The recharge technique is more applicable to
`larger and faster arrays, as it gives higher yields (fewer
`
`1019-004
`
`

`
`254
`
`IEEEJOURN.4LOFSOLID-STATECIRCUITS,VOL.SC-5,NO.5,OCTOBER1970
`
`components), and more rapid signal extraction as voltage
`levels of output
`lines do not have to change. SNR of
`over 50:1 is consistently obtained, and scan
`rates up to
`10 MHz are obtainable.
`
`ACKNOWLEDGMENT
`
`The authors would like to express their appreciation of
`the work and expertise contributed by numerous colleagues
`that are evident from the results described in this paper.
`
`[1]
`
`[2]
`
`REFERENCES
`P. K. Weimar,,G. Sadasiv, J. E. Meyer, Jr., L. Meray-Horvath,
`and W. S. Pike, “A self-scanned solid-state image sensor,”
`Proc. IEEE, vol. 55, pp. 1591-1602, September 1967.
`G. P. Weckler, “Storage mode operation of a phototransistor
`and its adaptation to integrated arrays for image detection,”
`presented at, the Int. Electron Devices Meeting, Washington,
`
`[3]
`
`[4]
`
`D. C., October 1966; also Electronics,vol. 40, p. 75, May 1967.
`M. A. Schuster et al., “Fabrication considerations for high order
`monolithic solid-state mos~ics of opto-electronic elements,”
`presented at the AIME Conf. on Material Science and Tech-
`nology in Integrated Electronics. San Francisco. Calif.. Seu-
`,.
`tembr 1965.
`-
`P. J. W. Noble,
`‘(Light sensitive arrays based on photo diodes
`combined with M. O.S. devices,” presented at the IEE Conf.
`on Integrated Circuits, Eastbourne, England, May 1967; also
`IEE Conf. Publ., VO1. 30, p. 251.
`image detectors,” presented at the SIRA
`——— ‘Wlid-state
`Cont., Eastbourue, England, April 10-12, 1967.
`—,
`“Self-scanned silicon Image detector arravs.” IEEE Trans.
`Elect’ronDevice?, vol. ED-15, pi. 202-209, Ap~l 196%
`M. H. Crowell, ‘[An image sensing diode array with electron
`beam accessin~,” presented at the Solid-State Devices Conf.,
`Manchester, England. September 5-7, 1967.
`B. Crowle, ‘[A novel circuit element for MOS integrated circuits,”
`IS8CC Digest Tech. Papers, February 1970, paper 14.3.
`J. D. .Plumrner and J. D. Meindl, “MOS electronics for a read-
`ing ald for the bhnd,” ISSCC Digest Tech. Papers, February
`1970, paper 14.1.
`
`[.5]
`
`[6]
`
`[7]
`
`[8]
`
`[9]
`
`ImagingSystem
`MicrominiatureSolid-State
`Techniques
`UtilizingHybrid LSI
`
`WILL1&h”
`
`G. h~E~T~, EUGEhTE
`
`E. ~[CCOY, MEMBER, IEEE, .4ND R~LAhTD
`
`i%.A~DERS,
`
`MEMBER,
`
`IEEE
`
`Absfracf—This paper describes the design, construction, and
`performance characteristics of a low-resolution 50 X 80 element
`solid-state imaging system that has been fabricated using multichip
`large-scale integration. The complete system electronics that are
`packaged on a single 2.6 by 3.Mnch ceramic substrate are described.
`Techniques used to fabricate the substrate that contains 117 MOS
`and low-power bipolar integrated circuits plus the 4000-element
`phototransistormosaic sensor array are discussed. Also, the methods
`used to mount and provide interdevice signal paths, including
`the use of advanced multilayer flexible interconnection techniques
`are shown.
`System-design parameters are discussed, including the techniques
`employed to minimize system power consumption and achie~e an
`overall system power consumption of 400 mW. This achievement
`represents a significant reduction over conventional design ap-
`proaches. The optical
`imaging system is discussed,
`including
`performance parameters and a novel arrangement for achieving
`maximum optical performance at minimum cost.
`A descri~tion of the electronic logic circuitry required to address
`and read out the phototransistor array is presented. The collector
`readout technique used for the mosaic is presented and compared
`to alternative techniques such as emitter readout. Also included
`is a discussion of the processing circuitry needed to provide CRT
`Z-axis modulation and A--Y deflection for image display. Finally,
`performance characteristics of the system and a discussion of
`future development in the low-resolution solid-state imaging field
`are presented.
`
`INTRODUCTION AND SUMMARY
`
`1?
`
`past several years, there has been con-
`OR THE
`siderable interest
`in the utilization of monolithic
`arrays of silicon phototransistors
`as the electro-
`optical sensing element in television camera systems [1]–[3].
`These solid-state arrays, as compared to conventional
`vidicon sensors, have the advantage of reduced size and
`weight, low-voltage operation (typically less than 12 volts),
`low-power
`consumption,
`lack of need for magnetic
`or
`high-voltage deflection systems,
`increased reliability and
`long life, relative immunity
`to mechanical
`shock, and
`compatibility with the latest
`techniques
`in miniature
`packaging.
`Spurred on by technological
`advances
`in
`large-scale integration (LSI),
`the phototransistor mosaic
`work has progressed from 2500 elements on 10-mil spacing
`to 51200 on 3.7-mil centers, and work is now underway
`to develop sensors capable of achieving element densities
`comparable to those of standard vidicon sensors.1
`While these large-scale arrays are still developmental
`in nature,
`it is possible now to build lower resolution
`imaging
`systems
`that, by
`taking advantage
`of LSI
`techniques developed for the larger systems, can provide
`a producible,
`extremely
`compact,
`imaging
`system at
`
`Manuscript received March 16, 1970; revised Nlay 8, 1970.
`The authors are with Systems Development, Westinghouse
`Advanced Technology Laboratories, Baltimore, Md. 21203.
`
`1Ll[lch of this work has been funded by the George C. Lfarshall
`Space Flight Center, Huntsville, Ala., under Contract NAS8-5112.
`
`1019-005