ARM610
`
`Data Sheet
`
`Document Number: ARM DDI 0004D
`Issued: Aug 1993
`Copyright Advanced RISC Machines Ltd (ARM) 1993
`All rights reserved
`
`Proprietary Notice
`ARM and the ARM Powered logo are trademarks of Advanced RISC Machines Ltd.
`
`Neither the whole nor any part of the information contained in, or the product described in, this
`datasheet may be adapted or reproduced in any material form except with the prior written
`permission of the copyright holder.
`
`The product described in this datasheet is subject to continuous developments and
`improvements. All particulars of the product and its use contained in this datasheet are given by
`ARM in good faith. However, all warranties implied or expressed, including but not limited to
`implied warranties or merchantability, or fitness for purpose, are excluded.
`
`This datasheet is intended only to assist the reader in the use of the product. ARM Ltd shall not
`be liable for any loss or damage arising from the use of any information in this datasheet, or any
`error or omission in such information, or any incorrect use of the product.
`
`Change Log
`Issue
`Date
`
`D
`
`Aug 93
`
`By
`
`TP
`
`Change
`
`Unified FrameMaker version created.
`
`Advanced RISC MachinesARM
`
`SCEA Ex. 1052 Page 1
`
`

`
`Preface
`
`The ARM610 is a general purpose 32-bit microprocessor with 4kByte cache, write buffer and Memory
`Management Unit (MMU) combined in a single chip. The ARM610 offers high level RISC performance yet
`its fully static design ensures minimal power consumption, making it ideal for portable, low-cost systems.
`
`The innovative MMU supports a conventional two-level page-table structure and a number of extensions
`which make it ideal for embedded control, UNIX and Object Oriented systems. This results in a high
`instruction throughput and impressive real-time interrupt response from a small and cost-effective chip.
`
`Applications
`The ARM610 is ideally suited to those applications requiring RISC performance from a compact, power
`efficient processor. These include:
`n Personal computer devices e.g.PDAs
`n High-performance real-time control systems
`n Portable telecommunications
`n Data communications equipment
`n Consumer products
`n Automotive
`
`Feature Summary
`n High performance RISC
`15 MIPS sustained @ 20 MHz (20 MIPS peak)
`n Fast sub microsecond interrupt response
`for real-time applications
`n Memory Management Unit (MMU)
`support for virtual memory systems
`n Excellent high-level language support
`n 4kByte of instruction & data cache
`n Big and Little Endian operating modes
`n Write Buffer
`enhancing performance
`IEEE 1149.1 Boundary Scan
`n
`n Fully static operation, low power consumption
`ideal for power sensitive applications
`n 144 Thin Quad Flat Pack (TQFP) package
`
`Address
`Bus
`
`MMU
`
`Write
`Buffer
`
`JTAG
`
`ARM6
`CPU
`
`4Kbyte
`Cache
`
`Control
`
`ii
`
`ARM610 Data Sheet
`
`SCEA Ex. 1052 Page 2
`
`

`
`Introduction
`
`1.0 Introduction
`
`ARM610, is a general purpose 32-bit microprocessor with 4kByte cache, write buffer and Memory
`Management Unit (MMU) combined in a single chip. The CPU within ARM610 is the ARM6. The ARM610
`is software compatible with the ARM processor family and can be used with ARM support chips, eg IO,
`memory and video.
`
`The ARM610 architecture is based on 'Reduced Instruction Set Computer' (RISC) principles, and the
`instruction set and related decode mechanism are greatly simplified compared with microprogrammed
`'Complex Instruction Set Computers' (CISC).
`
`The on-chip mixed data and instruction cache together with the write buffer substantially raise the average
`execution speed and reduce the average amount of memory bandwidth required by the processor. This
`allows the external memory to support additional processors or Direct Memory Access (DMA) channels
`with minimal performance loss.
`
`The MMU supports a conventional two-level page-table structure and a number of extensions which make
`it ideal for embedded control, UNIX and Object Oriented systems.
`
`•
`
`The instruction set comprises ten basic instruction types:
`•
`Two of these make use of the on-chip arithmetic logic unit, barrel shifter and multiplier to perform
`high-speed operations on the data in a bank of 31 registers, each 32 bits wide;
`Three classes of instruction control data transfer between memory and the registers, one optimised
`for flexibility of addressing, another for rapid context switching and the third for swapping data;
`Two instructions control the flow and privilege level of execution; and
`Three types are dedicated to the control of external coprocessors which allow the functionality of
`the instruction set to be extended off-chip in an open and uniform way.
`
`•
`•
`
`The ARM instruction set is a good target for compilers of many different high-level languages. Where
`required for critical code segments, assembly code programming is also straightforward, unlike some RISC
`processors which depend on sophisticated compiler technology to manage complicated instruction
`interdependencies.
`
`The memory interface has been designed to allow the performance potential to be realised without
`incurring high costs in the memory system. Speed-critical control signals are pipelined to allow system
`control functions to be implemented in standard low-power logic, and these control signals permit the
`exploitation of paged mode access offered by industry standard DRAMs.
`
`ARM610 is a fully static part and has been designed to minimise its power requirements. This makes it ideal
`for portable applications where both these features are essential.
`
`Datasheet Notation:
`
`0x
`BOLD
`binary
`
`- marks a Hexadecimal quantity
`- external signals are shown in bold capital letters
`- where it is not clear that a quantity is binary it is followed by the word binary
`
`3
`
`SCEA Ex. 1052 Page 3
`
`

`
`ARM610 Data Sheet
`
`ARM610 is a variant of the ARM600, differing from that device in the following respects:
`
`•
`•
`•
`•
`•
`
`No external coprocessor bus interface
`Internal Address latches controlled by ALE added
`nRW, nBW, LOCK also latched by ALE, and tristated by ABE. (CBE therefore removed)
`Dedicated chip test port added
`Device packaging
`
`4
`
`SCEA Ex. 1052 Page 4
`
`

`
`1.1 Block Diagram
`
`Introduction
`
`ABE
`
`A[31:0] nR/W nB/W LOCK
`
`ALE
`
`TCK TDI TMS nTRST TDO
`
`nWAIT MCLK SnA FCLK
`
`nRESET
`
`MSE
`
`nMREQ
`
`SEQ
`
`ABORT
`
`nIRQ
`
`nFIQ
`
`TESTOUT[2:0]
`
`TESTIN[16:0]
`
`Control
`
`COPROC
` #15
`
`Address Buffer
`
`JTAG Test
`
`Clock
`
`Internal Address Bus
`
`MMU
`
`4 kByte
` Cache
`
`ARM6
` CPU
`
`Internal Data Bus
`
`Write
`Buffer
`
`DBE
`
`D[31:0]
`
` Figure 1: ARM610 Block Diagram
`
`5
`
`SCEA Ex. 1052 Page 5
`
`

`
`ARM610 Data Sheet
`
`1.2 Functional Diagram
`
`SnA
`
`FCLK
`
`MCLK
`
`nWAIT
`
`nIRQ
`
`nFIQ
`
`nRESET
`
`ABE
`
`DBE
`
`ALE
`
`MSE
`
`VDD
`
`VSS
`
`TCK
`
`TDI
`
`TDO
`
`TMS
`
`nTRST
`
`ARM610
`
`A[31:0]
`
`Address
`Bus
`
`D[31:0]
`
`nRW
`
`nBW
`
`LOCK
`
`nMREQ
`
`SEQ
`
`ABORT
`
`TESTOUT[2:0]
`
`TESTIN[16:0]
`
`Data
`Bus
`
`Control
`Bus
`
`Memory
`Interface
`
`Chip
`Test
`
` Figure 2: Functional Diagram
`
`Clocks
`
`Interrupts
`
`Bus
`Controls
`
`Power
`
`JTAG
`Test
`
`6
`
`SCEA Ex. 1052 Page 6
`
`

`
`Signal Description
`
`2.0 Signal Description
`
`Name
`
`Type
`
`A[31:0]
`
`OCZ
`
`ABE
`
`ABORT
`
`ALE
`
`IT
`
`IT
`
`IT
`
`D[31:0]
`
`ITOTZ
`
`DBE
`
`IT
`
`Description
`
`Address Bus. This bus signals the address requested for memory accesses. Normally it
`changes during MCLK HIGH.
`
`Address bus enable. When this input is LOW, the address bus A[31:0], nRW, nBW and
`LOCK are put into a high impedance state (Note 1).
`
`External abort. Allows the memory system to tell the processor that a requested access has
`failed. Only monitored when ARM610 is accessing external memory.
`
`Address latch enable. This input is used to control transparent latches on the address bus
`A[31:0], nBW, nRW & LOCK. Normally these signals change during MCLK HIGH, but
`they may be held by driving ALE LOW. See section 13.2.2 on page 124.
`
`Data bus. These are bi-directional signal paths used for data transfers between the proces-
`sor and external memory. For read operations (when nRW is LOW), the input data must
`be valid before the falling edge of MCLK. For write operations (when nRW is HIGH), the
`output data will become valid while MCLK is LOW. At high clock frequencies the data
`may not become valid until just after the MCLK rising edge (see section 13.3 on page 125).
`
`Data bus enable. When this input is LOW, the data bus, D[31:0] is put into a high imped-
`ance state (Note 1). The drivers will always be high impedance except during write opera-
`tions, and DBE must be driven HIGH in systems which do not require the data bus for
`DMA or similar activities.
`
`FCLK
`
`ICK
`
`Fast clock input. When the ARM610 CPU is accessing the cache or performing an inter-
`nal cycle, it is clocked with the Fast Clock, FCLK.
`
`LOCK
`
`OCZ
`
`MCLK
`
`ICK
`
`MSE
`
`nBW
`
`IT
`
`OCZ
`
`Locked operation. LOCK is driven HIGH, to signal a “locked” memory access sequence,
`and the memory manager should wait until LOCK goes LOW before allowing another
`device to access the memory. LOCK changes while MCLK is HIGH and remains HIGH
`during the locked memory sequence. LOCK is latched by ALE.
`
`Memory clock input. This clock times all ARM610 memory accesses. The LOW or HIGH
`period of MCLK may be stretched for slow peripherals; alternatively, the nWAIT input
`may be used with a free-running MCLK to achieve similar effects.
`
`Memory request/sequential enable. When this input is LOW, the nMREQ and SEQ out-
`puts are put into a high impedance state (Note 1).
`
`Not byte / word. An output signal used by the processor to indicate to the external mem-
`ory system when a data transfer of a byte length is required. nBW is HIGH for word
`transfers and LOW for byte transfers, and is valid for both read and write operations. The
`signal changes while MCLK is HIGH. nBW is latched by ALE.
`
`nFIQ
`
`IT
`
`Not fast interrupt request. If FIQs are enabled, the processor will respond to a LOW level
`on this input by taking the FIQ interrupt exception. This is an asynchronous, level-sensi-
`tive input, and must be held LOW until a suitable response is received from the processor.
`
`Table 1: Signal Descriptions
`
`7
`
`SCEA Ex. 1052 Page 7
`
`

`
`ARM610 Data Sheet
`
`Name
`
`Type
`
`nIRQ
`
`IT
`
`nMREQ
`
`OCZ
`
`nRESET
`
`IT
`
`Description
`
`Not interrupt request. As nFIQ, but with lower priority. May be taken LOW asynchro-
`nously to interrupt the processor when the IRQ enable is active.
`
`Not memory request. A pipelined signal that changes while MCLK is LOW to indicate
`whether or not in the following cycle, the processor will be accessing external memory.
`When nMREQ is LOW, the processor will be accessing external memory
`
`Not reset. This is a level sensitive input which is used to start the processor from a known
`address. A LOW level will cause the current instruction to terminate abnormally, and the
`on-chip cache, MMU, and write buffer to be disabled. When nRESET is driven HIGH, the
`processor will re-start from address 0. nRESET must remain LOW for at least 2 full FCLK
`cycles or 5 full MCLK cycles which ever is greater. While nRESET is LOW the processor
`will perform idle cycles with incrementing addresses and nWAIT must be HIGH.
`
`nRW
`
`OCZ
`
`Not read/write. When HIGH this signal indicates a processor write operation; when
`LOW, a read. The signal changes while MCLK is HIGH. nRW is latched by ALE.
`
`IT
`
`IT
`
`OCZ
`
`IT
`
`IT
`
`OCZ
`
`IT
`
`IT
`
`Test interface reset. Note this pin does NOT have an internal pullup resistor. This pin
`must be pulsed or driven LOW to achieve normal device operation, in addition to the nor-
`mal device reset (nRESET).
`
`Not wait. When LOW this allows extra MCLK cycles to be inserted in memory accesses. It
`must change during the LOW phase of the MCLK cycle to be extended.
`
`Sequential address. This signal is the inverse of nMREQ, and is provided for compatibil-
`ity with existing ARM memory systems.
`
`This pin should be hard wired HIGH.
`
`Test bus input. This bus is used for off-board testing of the device. When the device is fit-
`ted to a circuit all these pins must be tied LOW.
`
`Test bus output. This bus is used for off-board testing of the device. When the device is fit-
`ted to a circuit and all the TESTIN[16:0] pins are driven LOW, these three outputs will be
`driven LOW. Note that these pins may not be tristated, except via the JTAG test port.
`
`Test interface reference Clock. This times all the transfers on the JTAG test interface.
`
`Test interface data input. Note this pin does NOT have an internal pullup resistor.
`
`OCZ
`
`Test interface data output. Note this pin does NOT have an internal pullup resistor.
`
`IT
`
`Test interface mode select. Note this pin does NOT have an internal pullup resistor.
`
`Positive supply. 16 pins are allocated to VDD in the 160 PQFP package.
`
`Ground supply. 16 pins are allocated to VSS in the 160 PQFP package.
`
`Table 1: Signal Descriptions
`
`nTRST
`
`nWAIT
`
`SEQ
`
`SnA
`
`TEST
`IN[16:0]
`
`TEST
`OUT[2:0]
`
`TCK
`
`TDI
`
`TDO
`
`TMS
`
`VDD
`
`VSS
`
`8
`
`SCEA Ex. 1052 Page 8
`
`

`
`Signal Description
`
`Notes:
`
`1.
`
`2.
`
`When output pads are placed in the high impedance state for long periods, care must be taken to
`ensure that they do not float to an undefined logic level, as this can dissipate power, especially in
`the pads.
`Although the input pads have TTL thresholds, and will correctly interpret a TTL level input, it must
`be noted that unless all inputs are driven to the voltage rails, the input circuits will consume power.
`
`Key to Signal Types:
`
`IT - Input, TTL threshold
`OCZ - Output, CMOS levels, tri-stateable
`ITOTZ - Input/output tri-stateable, TTL thresholds
`ICK - Input, clock levels
`
`9
`
`SCEA Ex. 1052 Page 9
`
`

`
`ARM610 Data Sheet
`
`10
`
`SCEA Ex. 1052 Page 10
`
`

`
`4.0
`
`5.0
`
`6.0
`
`1.0
`
`2.0
`3.0
`
`Introduction
`1.1
`Block Diagram
`1.2
`Functional Diagram
`Signal Description
`Programmer's Model
`3.1
`Register Configuration
`3.2
`Operating Mode Selection
`3.3
`Registers
`3.4
`Exceptions
`3.5
`Reset
`Instruction Set
`4.1
`Instruction Set Summary
`4.2
`The Condition Field
`4.3
`Branch and Branch with link (B, BL)
`4.4
`Data processing
`4.5
`PSR Transfer (MRS, MSR)
`4.6
`Multiply and Multiply-Accumulate (MUL, MLA)
`4.7
`Single data transfer (LDR, STR)
`4.8
`Block data transfer (LDM, STM)
`4.9
`Single data swap (SWP)
`4.10
`Software interrupt (SWI)
`4.11
`Coprocessor Instructions on ARM610
`4.12
`Coprocessor data operations (CDP)
`4.13
`Coprocessor data transfers (LDC, STC)
`4.14
`Coprocessor register transfers (MRC, MCR)
`4.15
`Undefined instruction
`4.16
`Instruction Set Examples
`Configuration
`5.1
`Internal Coprocessor Instructions
`5.2
`Registers
`Instruction and Data Cache (IDC)
`6.1
`Cacheable Bit - C
`6.2
`Updateable Bit - U
`6.3
`IDC Operation
`6.4
`IDC validity
`6.5
`Read-Lock-Write
`6.6
`IDC Enable/Disable and Reset
`7.0 Write Buffer (WB)
`7.1
`Bufferable bit
`7.2
`Write Buffer Operation
`Coprocessors
`8.0
`9.0 Memory Management Unit (MMU)
`9.1
`MMU Program Accessible Registers
`9.2
`Address Translation
`
` Table of Contents
`
`3
`5
`6
`7
`17
`17
`17
`18
`21
`25
`27
`27
`28
`29
`31
`38
`42
`44
`49
`56
`58
`60
`60
`62
`65
`67
`68
`73
`73
`73
`77
`77
`77
`77
`78
`78
`78
`81
`81
`81
`83
`85
`85
`86
`
`xi
`
`SCEA Ex. 1052 Page 11
`
`

`
`Translation Process
`9.3
`Level One Descriptor
`9.4
`Page Table Descriptor
`9.5
`Section Descriptor
`9.6
`Translating Section References
`9.7
`Level Two Descriptor
`9.8
`Translating Small Page References
`9.9
`Translating Large Page References
`9.10
`9.11 MMU Faults and CPU Aborts
`9.12
`Fault Address & Fault Status Registers (FAR & FSR)
`9.13
`Domain Access Control
`9.14
`Fault Checking Sequence
`9.15
`External Aborts
`9.16
`Interaction of the MMU, IDC and Write Buffer
`9.17
`Effect of Reset
`10.0 Bus Interface
`10.1
`ARM610 Cycle Speed
`10.2
`Cycle Types
`10.3 Memory Access
`10.4
`Read/Write
`10.5
`Byte/Word
`10.6 Maximum Sequential Length
`10.7 Memory Access Types
`10.8
`Unbuffered Writes / Uncacheable Reads
`10.9
`Buffered Write
`10.10
`Linefetch
`10.11
`Translation fetches
`10.12
`Read - lock -write
`10.13 ARM610 Cycle Type Summary
`11.0 Boundary Scan Test Interface
`11.1
`Overview
`11.2
`Reset
`11.3
`Pullup Resistors
`11.4
`Instruction Register
`11.5
`Public Instructions
`11.6
`Test Data Registers
`11.7
`Boundary Scan Interface Signals
`12.0 DC Parameters
`12.1
`Absolute Maximum Ratings
`12.2
`DC Operating Conditions
`12.3
`DC Characteristics
`13.0 AC Parameters
`13.1
`Test Conditions
`13.2
`Relationship between FCLK & MCLK
`13.3 Main Bus Signals
`Physical Details
`
`14.0
`
` Table of Contents
`
`87
`88
`88
`89
`90
`91
`92
`93
`94
`94
`96
`97
`99
`99
`100
`101
`101
`101
`101
`102
`102
`102
`104
`104
`104
`104
`105
`106
`107
`109
`109
`110
`110
`110
`110
`114
`117
`121
`121
`121
`122
`123
`123
`123
`125
`127
`
`xii
`
`SCEA Ex. 1052 Page 12
`
`

`
` Table of Contents
`
`Pinout
`15.0
`16.0 Appendix - Backward Compatibility
`
`129
`131
`
`xiii
`
`SCEA Ex. 1052 Page 13
`
`

`
` Table of Contents
`
`xiv
`
`SCEA Ex. 1052 Page 14
`
`

`
` Table of Contents
`
`xv
`
`SCEA Ex. 1052 Page 15
`
`

`
`ARM710 Data Sheet
`
`xvi
`
`SCEA Ex. 1052 Page 16
`
`

`
`Programmer's Model
`
`3.0 Programmer's Model
`
`ARM610 supports a variety of operating configurations. Some are controlled by register bits and are known
`as the register configurations. Others may be controlled by software and these are known as operating modes.
`
`3.1 Register Configuration
`
`The ARM610 processor provides 4 register configurations which may be changed while the processor is
`running and which are detailed in Chapter 4.0 Instruction Set.
`
`The bigend bit, in the Control Register, sets whether the ARM610 treats words in memory as being stored
`in Big Endian or Little Endian format, see Chapter 5.0 Configuration. Memory is viewed as a linear collection
`of bytes numbered upwards from zero. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and
`so on.
`
`In the Little Endian scheme the lowest numbered byte in a word is considered to be the least significant byte
`of the word and the highest numbered byte is the most significant. Byte 0 of the memory system should be
`connected to data lines 7 through 0 (D[7:0]) in this scheme.
`
`In the Big Endian scheme the most significant byte of a word is stored at the lowest numbered byte and the
`least significant byte is stored at the highest numbered byte. Byte 0 of the memory system should therefore
`be connected to data lines 31 through 24 (D[31:24]).
`
`The lateabt bit in the Control Register, see Chapter 5.0 Configuration, sets the processor's behaviour when a
`data abort exception occurs. It only affects the behaviour of load/store register instructions and is discussed
`more fully in Chapter 3.0 Programmer's Model and Chapter 4.0 Instruction Set.
`
`The other two configuration bits, prog32 and data32 are used for backward compatibility with earlier ARM
`processors (see 16.0 Appendix - Backward Compatibility) but should normally be set to 1. This configuration
`extends the address space to 32 bits, introduces major changes in the programmer's model as described
`below and provides support for running existing 26 bit programs in the 32 bit environment. This mode is
`recommended for compatibility with future ARM processors and all new code should be written to use
`only the 32 bit operating modes.
`
`Because the original ARM instruction set has been modified to accommodate 32 bit operation there are
`certain additional restrictions which programmers must be aware of. These are indicated in the text by the
`words shall and shall not. Reference should also be made to the ARM Application Notes “Rules for ARM Code
`Writers” and “Notes for ARM Code Writers” available from your supplier.
`
`3.2 Operating Mode Selection
`
`ARM610 has a 32 bit data bus and a 32 bit address bus. The data types the processor supports are Bytes (8
`bits) and Words (32 bits), where words must be aligned to four byte boundaries. Instructions are exactly
`one word, and data operations (e.g. ADD) are only performed on word quantities. Load and store
`operations can transfer either bytes or words.
`
`17
`
`SCEA Ex. 1052 Page 17
`
`

`
`ARM610 Data Sheet
`
`ARM610 supports six modes of operation:
`(1)
`User mode (usr): the normal program execution state
`(2)
`FIQ mode (fiq): designed to support a data transfer or channel process
`(3)
`IRQ mode (irq): used for general purpose interrupt handling
`(4)
`Supervisor mode (svc): a protected mode for the operating system
`(5)
`Abort mode (abt): entered after a data or instruction prefetch abort
`(6)
`Undefined mode (und): entered when an undefined instruction is executed
`
`Mode changes may be made under software control or may be brought about by external interrupts or
`exception processing. Most application programs will execute in User mode. The other modes, known as
`privileged modes, will be entered to service interrupts or exceptions or to access protected resources.
`
`3.3 Registers
`
` The processor has a total of 37 registers made up of 31 general 32 bit registers and 6 status registers. At any
`one time 16 general registers (R0 to R15) and one or two status registers are visible to the programmer. The
`visible registers depend on the processor mode and the other registers (the banked registers) are switched in
`to support IRQ, FIQ, Supervisor, Abort and Undefined mode processing. The register bank organisation is
`shown in Figure 3: Register Organisation. The banked registers are shaded in the diagram.
`
` In all modes 16 registers, R0 to R15, are directly accessible. All registers except R15 are general purpose and
`may be used to hold data or address values. Register R15 holds the Program Counter (PC). When R15 is
`read, bits [1:0] are zero and bits [31:2] contain the PC. A seventeenth register (the CPSR - Current Program
`Status Register) is also accessible. It contains condition code flags and the current mode bits and may be
`thought of as an extension to the PC.
`
`R14 is used as the subroutine link register and receives a copy of R15 when a Branch and Link instruction
`is executed. It may be treated as a general purpose register at all other times. R14_svc, R14_irq, R14_fiq,
`R14_abt and R14_und are used similarly to hold the return values of R15 when interrupts and exceptions
`arise, or when Branch and Link instructions are executed within interrupt or exception routines.
`
`18
`
`SCEA Ex. 1052 Page 18
`
`

`
`Programmer's Model
`
`General Registers and Program Counter Modes
`
`User32
`
`FIQ32
`
`Supervisor32
`
`Abort32
`
`IRQ32
`
`Undefined32
`
`R0
`
`R1
`
`R2
`
`R3
`
`R4
`
`R5
`
`R6
`
`R7
`
`R0
`
`R1
`
`R2
`
`R3
`
`R4
`
`R5
`
`R6
`
`R7
`
`R0
`
`R1
`
`R2
`
`R3
`
`R4
`
`R5
`
`R6
`
`R7
`
`R8
`
`R0
`
`R1
`
`R2
`
`R3
`
`R4
`
`R5
`
`R6
`
`R7
`
`R8
`
`R0
`
`R1
`
`R2
`
`R3
`
`R4
`
`R5
`
`R6
`
`R7
`
`R8
`
`R0
`
`R1
`
`R2
`
`R3
`
`R4
`
`R5
`
`R6
`
`R7
`
`R8
`
`R8
`
`R9
`
`R10
`
`R11
`
`R12
`
`R13
`
`R14
`
`R8_fiq
`
`R9_fiq
`
`R10_fiq
`
`R11_fiq
`
`R12_fiq
`
`R13_fiq
`
`R14_fiq
`
`R15 (PC)
`
`R15 (PC)
`
`R9
`
`R10
`
`R11
`
`R12
`
`R13_svc
`
`R14_svc
`
`R15 (PC)
`
`R9
`
`R10
`
`R11
`
`R12
`
`R13_abt
`
`R14_abt
`
`R15 (PC)
`
`R9
`
`R10
`
`R11
`
`R12
`
`R13_irq
`
`R14_irq
`
`R15 (PC)
`
`R9
`
`R10
`
`R11
`
`R12
`
`R13_und
`
`R14_und
`
`R15 (PC)
`
`Program Status Registers
`
`CPSR
`
`CPSR
`
`CPSR
`
`CPSR
`
`CPSR
`
`CPSR
`
`SPSR_fiq
`
`SPSR_svc
`
`SPSR_abt
`
`SPSR_irq
`
`SPSR_und
`
` Figure 3: Register Organisation
`
`FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). Many FIQ programs will not need
`to save any registers. User mode, IRQ mode, Supervisor mode, Abort mode and Undefined mode each have
`two banked registers mapped to R13 and R14. The two banked registers allow these modes to each have a
`private stack pointer and link register. Supervisor, IRQ, Abort and Undefined mode programs which
`require more than these two banked registers are expected to save some or all of the caller's registers (R0 to
`R12) on their respective stacks. They are then free to use these registers which they will restore before
`returning to the caller. In addition there are also five SPSRs (Saved Program Status Registers) which are
`loaded with the CPSR when an exception occurs. There is one SPSR for each privileged mode.
`
`19
`
`SCEA Ex. 1052 Page 19
`
`

`
`ARM610 Data Sheet
`
`flags
`
`control
`
`31
`
`N
`
`30
`
`Z
`
`29
`
`C
`
`28
`
`V
`
`27
`
`.
`
`8
`
`.
`
`7
`
`I
`
`6
`
`F
`
`5
`
`.
`
`.
`
`4
`
`3
`
`2
`
`1
`
`0
`
`M4
`
`M3
`
`M2
`
`M1
`
`M0
`
`Overflow
`Carry / Borrow / Extend
`Zero
`Negative / Less Than
`
`Mode bits
`FIQ disable
`IRQ disable
`
` Figure 4: Format of the Program Status Registers (PSRs)
`
`The format of the Program Status Registers is shown in Figure 4: Format of the Program Status Registers
`(PSRs). The N, Z, C and V bits are the condition code flags. The condition code flags in the CPSR may be
`changed as a result of arithmetic and logical operations in the processor and may be tested by all
`instructions to determine if the instruction is to be executed.
`
`The I and F bits are the interrupt disable bits. The I bit disables IRQ interrupts when it is set and the F bit
`disables FIQ interrupts when it is set. The M0, M1, M2, M3 and M4 bits (M[4:0]) are the mode bits, and these
`determine the mode in which the processor operates. The interpretation of the mode bits is shown in Table
`2: The Mode Bits. Not all combinations of the mode bits define a valid processor mode. Only those explicitly
`described shall be used.
`
`The bottom 28 bits of a PSR (incorporating I, F and M[4:0]) are known collectively as the control bits. The
`control bits will change when an exception arises and in addition can be manipulated by software when the
`processor is in a privileged mode. Unused bits in the PSRs are reserved and their state shall be preserved
`when changing the flag or control bits. Programs shall not rely on specific values from the reserved bits
`when checking the PSR status, since they may read as one or zero in future processors.
`
`M[4:0]
`
` 10000
`
` 10001
`
` 10010
`
` 10011
`
` 10111
`
` 11011
`
`Mode
`
` Accessible register set
`
` usr
`
`fiq
`
`irq
`
`svc
`
`abt
`
`und
`
`PC, R14..R0
`
` CPSR
`
`PC, R14_fiq..R8_fiq, R7..R0
`
`CPSR, SPSR_fiq
`
`PC, R14_irq..R13_irq, R12..R0
`
`CPSR, SPSR_irq
`
`PC, R14_svc..R13_svc, R12..R0
`
` CPSR, SPSR_svc
`
`PC, R14_abt..R13_abt, R12..R0
`
`CPSR, SPSR_abt
`
`PC, R14_und..R13_und, R12..R0
`
` CPSR, SPSR_und
`
`Table 2: The Mode Bits
`
`20
`
`SCEA Ex. 1052 Page 20
`
`

`
`Programmer's Model
`
`3.4 Exceptions
`
`Exceptions arise whenever there is a need for the normal flow of program execution to be broken, so that
`(for example) the processor can be diverted to handle an interrupt from a peripheral. The processor state
`just prior to handling the exception must be preserved so that the original program can be resumed when
`the exception routine has completed. Many exceptions may arise at the same time.
`
`ARM610 handles exceptions by making use of the banked registers to save state. The old PC and CPSR
`contents are copied into the appropriate R14 and SPSR and the PC and mode bits in the CPSR bits are forced
`to a value which depends on the exception. Interrupt disable flags are set where required to prevent
`otherwise unmanageable nestings of exceptions. In the case of a re-entrant interrupt handler, R14 and the
`SPSR should be saved onto a stack in main memory before re-enabling the interrupt; when transferring the
`SPSR register to and from a stack, it is important to transfer the whole 32 bit value, and not just the flag or
`control fields. When multiple exceptions arise simultaneously, a fixed priority determines the order in
`which they are handled. The priorities are listed later in this chapter.
`
`3.4.1 FIQ
`
`The FIQ (Fast Interrupt reQuest) exception is externally generated by taking the nFIQ input LOW. This
`input can accept asynchronous transitions, and is delayed by one clock cycle for synchronisation before it
`can affect the processor execution flow. It is designed to support a data transfer or channel process, and has
`sufficient private registers to remove the need for register saving in such applications (thus minimising the
`overhead of context switching). The FIQ exception may be disabled by setting the F flag in the CPSR (but
`note that this is not possible from User mode). If the F flag is clear, ARM610 checks for a LOW level on the
`output of the FIQ synchroniser at the end of each instruction.
`
`When a FIQ is detected, ARM610 performs the following:
`(1)
`Saves the address of the next instruction to be executed plus 4 in R14_fiq; saves CPSR in SPSR_fiq
`(2)
`Forces M[4:0]=10001 (FIQ mode) and sets the F and I bits in the CPSR
`(3)
`Forces the PC to fetch the next instruction from address 0x1C
`
`To return normally from FIQ, use SUBS PC, R14_fiq,#4 which will restore both the PC (from R14) and the
`CPSR (from SPSR_fiq) and resume execution of the interrupted code.
`
`3.4.2 IRQ
`
`The IRQ (Interrupt ReQuest) exception is a normal interrupt caused by a LOW level on the nIRQ input. It
`has a lower priority than FIQ, and is masked out when a FIQ sequence is entered. Its effect may be masked
`out at any time by setting the I bit in the CPSR (but note that this is not possible from User mode). If the I
`flag is clear, ARM610 checks for a LOW level on the output of the IRQ synchroniser at the end of each
`instruction. When an IRQ is detected, ARM610 performs the following:
`(1)
`Saves the address of the next instruction to be executed plus 4 in R14_irq; saves CPSR in SPSR_irq
`(2)
`Forces M[4:0]=10010 (IRQ mode) and sets the I bit in the CPSR
`(3)
`Forces the PC to fetch the next instruction from address 0x18
`
`21
`
`SCEA Ex. 1052 Page 21
`
`

`
`ARM610 Data Sheet
`
`To return normally from IRQ, use SUBS PC,R14_irq,#4 which will restore both the PC and the CPSR and
`resume execution of the interrupted code.
`
`3.4.3 Abort
`
`An ABORT can be signalled by either the internal Memory Management Unit or from the external ABORT
`input. ABORT indicates that the current memory access cannot be completed. For instance, in a virtual
`memory system the data corresponding to the current address may have been moved out of memory onto
`a disc, and considerable processor activity may be required to recover the data before the access can be
`performed successfully. ARM610 checks for ABORT during memory access cycles. When successfully
`aborted ARM610 will respond in one of two ways:
`(1)
`If the abort occurred during an instruction prefetch (a Prefetch Abort), the prefetched instruction is
`marked as invalid but the abort exception does not occur immediately. If the instruction is not
`executed, for example as a result of a branch being taken while it is in the pipeline, no abort will
`occur. An abort will take place if the instruction reaches the head of the pipeline and is about to be
`executed.
` If the abort occurred during a data access (a Data Abort), the action depends on the instruction type.
` Single data transfer instructions (LDR, STR) are aborted as though the instruction had not executed
`if the processor is configured for Early Abort. When configured for Late Abort, these instructions
`are able to write back modified base registers and the Abort handler must be aware of this.
`(b) The swap instruction (SWP) is aborted as though it had not executed, though externally the read
`access may take place.
`(c) Block data transfer instructions (LDM, STM) complete, and if write-back is set, the base is updated.
`If the instruction would normally have overwritten the base with data (i.e. LDM with the base in
`the transfer list), this overwriting is prevented. All register overwriting is prevented after the Abort
`is indicated, which means in particular that R15 (which is always last to be transferred) is preserved
`in an aborted LDM instruction.
`
`(2)
`
`(a)
`
`Note that on Data Aborts the ARM610 fault address and fault status registers are updated.
`
`When either a prefetch or data abort occurs, ARM610 performs the following:
`
`(1)
`
`(2)
`(3)
`
`Saves the address of the aborted instruction plus 4 (for prefetch aborts) or 8 (for data aborts) in
`R14_abt; saves CPSR in SPSR_abt.
`Forces M[4:0]=10111 (Abort mode) and sets the I bit in the CPSR.
`Forces the PC to fetch the next instruction from either address 0x0C (prefetch abort) or address 0x10
`(data abort).
`
`To return after fixing the reason for the abort, use SUBS PC,R14_abt,#4 (for a prefetch abort) or SUBS
`PC,R14_abt,#8 (for a data abort). This will restore both the PC and the CPSR and retry the aborted
`instruction.
`
`The abort mechanism allows a demand paged virtual memory system to be implemented when suitable
`memory management software is available. The processor is allowed to generate arbitrary addresses, and
`when the data at an address is unavailable the MMU signals an abort. The processor traps into system
`
`22
`
`SCEA Ex. 1052 Page 22
`
`

`
`Programmer's Model
`
`software which must work out the cause of the abort, make the requested data available, and retry the
`aborted instruction. The application program needs no knowledge of the amount of memory available to
`it, nor is its state in any way affected by the abort.
`
`Note that there are restrictions on the use of the external abort pin. See Chapter 9.0 Memory Management Unit
`(MMU).
`
`3.4.4 Software interrupt
`
`The software interrupt instruction (SWI) is used for getting into Supervisor mode, usually to request a
`particular supervisor function. When a SWI is executed, ARM610 performs the following:
`(1)
`Saves the address of the SWI instruction plus 4 in R14_svc; saves CPSR in SPSR_svc
`(2)
`Forces M[4:0]=10011 (Supervisor mode) and sets the I bit in the CPSR
`(3)
`Forces the PC to fetch the next instruction from address 0x08
`
`To return from a SWI, use MOVS PC,R14_svc. This will restore the PC and CPSR and return to the
`instruction following the SWI.
`
`3.4.5 Undefined instruction trap
`
`When the ARM610 comes across an instruction which it cannot handle (see Chapter 4