ID
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`EP 0 067 556 B1
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`second inputs oi Times 1 And Times 2 Multiply Shifter (MULTSHI-T12) 20366 and Times 4 And Times 8
`Multiply Shifter (MULTSHFT48l 20368. Outputs of MULTSHI-T12 and MULTSHFTB are connected.
`respectively, to first and second inputs of First Multiplier Arithmetic and Logic Unit (MULTALU1) 20370.
`MULTALU1 20370’s output is connected to input of Multiplier Working Register (MWR) 20372. Output of
`MWR 20372 is connected to a_ first input of Second Multiplier Arithmetic and Logic Unit (MULTALU2) 20374.
`A second input of MULTALU2 20374 is connected from output of RFR 20336. Output of MULTALU2 is
`connected to a second input of FRS 20362. As described above, first input of FR5 20362 is connected from
`output of NIBSHF 20368. Output of FRS 20362 is connected to input of RFR 20336.
`As described above, output of RFR 20338 is connected to second input of MULTALU2 20374. to iirst
`input of MULTRF 20350, to first input of MULTRM 20334, and to second input of FROM 20324. Output of
`RFR 20338 is also connected to input of Leading Zero Detector (LZD) 20376 of MULTCNTL 20318. and to
`inputs of Exception Logic (ECPT) 20378, CONSIZE 20352, and TSTINT 20320.
`
`4. Exponent Logic 20316
`Referring to EXP 20316. as previously described EXP 20316 performs certain operations with respect to
`exponent fields of single and double precision floating point number in EU 10122 floating point operations.
`EXP 20316 includes a second portion of EU 10122's general "register file, shown herein as Exponent Register '
`File (EXPRFl 20380. Although indicated as individual register files, MULTRF 20350 and EXPRF 20380
`comprise, as in GRF 10354, a unitary register file structure with common, parallel addressing of
`corresponding registers therein.
`Output of EXPHF 20380 is connected to a second inpLt of INSELA 20330. Aflrst input of EXPRF 20380 is
`connected from output of EXRM 20332. As previously described, a first input of EXRM 20332 is connected
`from second output of OPB 20322 through EXPO Bus 20325. A second input of EXRM 20332 is connected
`from output Sle Register (SCALER) 20338. A second input of EXPRF 203% is connected from output of
`Sign Logic (SIGN) 20382. lnput of SIGN 20382 is connected from second output of SCALER 20338.
`INSELA 20330. INSELB 20348, Exponent ALU (EXPALU) 20384 and SCALER 20338 comprise EXP
`20316's arithmetic circuitry for manipulating exponent fields of floating point numbers. INSEU-\ 20330 and
`INSELB 20348 select. respectively, first and second inputs to EXPALU 20384. As previously described. a first
`input of |NSEl..A 20330 is connected from second output of OPB 203% through EXPO Bus 20325. Second
`input of INSELA 20330 is connected from output of EXPRF 20380. Output of INSEIA 20330 is connected to
`first input of EXPALU 20384. First input of INSELB 20348 is. as previously described, connected from a
`second output of mCRD 20346. Second input of INSELB 20348 is connected from output of OPB 20322
`through EXPO Bus 20325. Third input of INSELB 20348 is connected from output of SCALER 20338 and
`fourth input of INSELB 20348 is connected from output of l.ZD 20376. Output of INSELB 20348 is connected
`to second input of EXFALU 20348. Output of EXPALU 20348 is connected to input of SCALER 20338.
`As previously described. second output of SCALER 20338 is connected with input of SIGN 20382 and
`first output is connected to second input of EXRM 20332 and to third input of INSELB 20348. First output of
`SCALER 20338 is also connected to EXPO Bus 20325, to first input of EXOM 20326, and to a second input of
`MULTCNT 20364.
`
`5. Multiplier Control 20318
`As previously described, MULTCNTL 20318 provides certain control signals and information for
`controlling and coordinating operation of EXP 20316 and MULT 20314 in performing arithmetic operations
`on floating point numbers. MULTCNTL 20318 includes LZD 20376 and MULTCNT 20364. Input of LZD 20376
`is connected from output of RFR 20336 through FR Bus 20337. Output of LZD 20376 are connected to a
`second input of MULTCNT 20364 and to fourth input of INSELB 20348. A second input of MULTCNT 20364
`is connected from output of SCALER 20338. As previously described, control output of MULTCNT 20364 is
`connected to control inputs of N|BSHF 20358.
`»
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`.60
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`6. Test and Interface Logic 20&0
`Finally, TSTINT 20320 includes ECPT 20378, CONSIZE 20352, and Testing Condition Logic (TSTCON)
`20386. input of ECPT 20378 and first input of CONSlZE 20352 are connected from output of RFR 20336
`through FR Bus 20337. A second input of CONSIZE 20352 is connected from LENGTH Bus 20226. An output
`of CONSIZE 20352 is connected, together with other inputs from EU 10122 (not shown for clarity of
`presentation) to TSTCON 20386. Output of TSTCON 20386 (not shown for clarity of presentation) are
`connected to NAG 20340. TSTCON 20388 {and ECPT 20378 have outputs to and inputs from FU 10120's
`FUlNT 20298.
`Having described the overall structure of EU 10122 above, operation of EU 10122 will be described next
`below with aid of further diagrams which will be introduced as required. Finally, operation of TSTINT 20320
`will be described, including a description of the detailed control signal interface between EU 10122 and FU
`10120 through TSTlNT 20320 and FUINT 20298. In addition to defining the interface between EU 10122 and
`FU 10120, certain features of EU 10122 operation will be described wherein those operations are executed
`
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`Petitioner Apple Inc. - Ex. 1025, p. 4001
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`

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`' EP oos75se 31‘
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`in cooperation with MEM 10112 and FU 10120. For example, EU 1o122's Stack Mechanisms, comprising in
`part portions of MULTRF 20350 and EXPRF 20380, resides partly in MEM 10112 so that operation of EU
`10122's Stack Mechanisms requires cooperative operations by EU 10122, MEM 10112 and FU 10120.
`
`b. Execute Unit 10122 Operation (Fig. 255)
`'
`1. Execute Unit Control Logic 20310 (Fig. 255)
`Referring to Fig. 255, a more detailed block diagram of EUCL 20310 is shown. As described above.
`EUCL 20310 receives EU 10122 Dispatch Pointers through EUDIS Bus 20206 from EUSDT 20266 and FUCTL
`_20214. EU 10122 Dispatch Pointers select certain EU 10122 micnoinstruction sequences for executing EU
`10122 arithmetic operations as required to execute user's programs, that is SOPs, and to assist in handling
`JP 10114 Events. As described above, major elements of EUCL 20310 include COMO 20342, EUSITT 20344,
`mCRD 20346. and NAG 20340.
`'
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`a.a. Command Queue 20342
`Inputs of COMO 20342 are connected from EUDlS Bus 20206 to receive and store EU 10122 Dispatch
`pointers provided from EUSDT 20266. Each such EU 10122 Dispatch Poimer is comprised of two
`information fields. A first information field contains a 10 bit starting address of a corresponding sequence
`of microinstructions residing in EUSITT 20344. Second field of each EU 10122 Dispatch Pointer is a 6 bit
`field containing certain control information. such as information identifying data format of corresponding
`operands to be operated upon. In this case unit dispatch pointer control field bits specify whether operands
`to be operated upon comprise signed or unsigned integer, packed or unpacked decimal, or single or double
`precision floating point numbers.
`COMO 20342 is comprised of two one word wide by two word deep register files. A first of these
`register fields is comprised of SOP Command Oueue Control Store (COOS) 25510 and SOP Command
`Queue Address Store (COASl 25512. Together, COCS 25510 and COAS 25512 comprise a one word wide by
`two word deep register file for receiving and storing EU 10122 Dispatch Pointers corresponding to SOPs,
`that is Dispatch Pointers for initiating EU 10122 operations direcfly concerned with executing a user's
`program. Address fields of these SOPs are received in COAS 25512, while control fields are received and
`stored in COCS 25510. COMO 20342 is thereby capable of receiving and storing up to two sequential EU
`10122 Dispatch Pointers corresponding to user program SOPs Those SOP derived Dispatch Pointers are
`executed in the order received from FU 10120. EU 10122 is thereby capable of receiving and storing one
`currently executing SOP Dispatch Pointer and one pending SOP Dispatch Pointer. Further SOP Dispatch
`Pointers may be read into COMO 20342 as previous SOPs are executed.
`
`b.b. Command Queue Event Control Store 25514 and Command Queue Event Address Control
`Store 2516
`Command Queue Event Control Store lCOCE) 25514 and command Queue Event Address Control
`Store (COAE) 25516 are similar in function and operation to, respectively, COCS 25510 ad COAS 25512.
`COCE 25514 and COAE 25516 receive and store. however, EU 10122 Dispatch Pointers initiating EU 10122
`operations requested by FU 10120 as required to handle JP 10114 Events. Again, COCE 25514 and COAE
`25516 comprise a one word wide by two word deep register file. COAE 25516 receives and stores address
`fields of Event Dispatch Pointers, while COCE 25514 receives and stores corresponding control fields of
`Event Dispatch Pointers. Again, COMO 20342 is capable of receiving and storing up to two sequential Event
`Dispatch Pointers at a time.
`'
`'
`As indicated in Fig. 255, outputs of COAS 25512 and COAE 25516, that is address fields of EU 10122
`Dispatch Pointers are provided as inputs to Select Case Multiplexer (SCASE) 25518 and Starting Address
`Select Multiplexer (SAS) 25520 and NAG 20340. which will be described further below. Control field
`outputs of (2065 25510 and COCE 25514 are provided as inputs to OPB 20322, described further below.
`
`55
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`c.c. Execute Unit $—lnterpreter Table 20344
`Referring to EUSi'lT 20344, as described above EUSITT 20344 is a memory for storing sequences of
`microinstructions for controlling operation of EU 10122 in response to EU 10122 Dispatch Pointers received
`from FU 10120. These microinstruction sequences may, in general, direct operation of EU 1012210 execute
`arithmetic operations in response to SOPs of users programs, or aid direct execution of EU 10122
`operations required to service JP 10114 Events. EUSTTT 20344 may be, for example, a 60 bit wide by 1,280
`word long memory structured as pages of 128 words per page. A portion of EUSITT 20344’s pages may be
`contained in Read Only Memory, for example for storing sequence of microinstructions for handling JP
`10114 Events. Remaining portions of EUSl‘lT 20344 may be constructed of Random Access Memory, for
`example for storing sequences of microinstructions for executing EU 10122 operations in response to user
`program SOPs. This structure allows EU 10122 microinstruction sequences concerned with operation of JP
`10114's internal mechanisms, for example handling of JP 10114 Events. to be effectively permanently
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`Petitioner Apple Inc. - Ex. 1025, p. 4002
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`Petitioner Apple Inc. - Ex. 1025, p. 4002
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`an 0057 556 B1
`stored in EUSITT 20344. That portion of EUSITT 20344 constructed of Random Access MemOl'V 018V P9
`used to store sequences of micminstructions for executing SOPs. These Random Access Memories may be
`used as writable control store to allow sequences of microinstructions for executing SOPs of one or more
`S-Languages currently being utilized by CS 10110 to be written into EUSlTl' 20344 from MEM 10112 as
`required.
`As previously described, EUSITT 20344's second input is a Data (DATA) input connected from JPD Bus
`10142. EUSITT 20344's data input is utilized to write sequences of microinstructions into EUSl‘iT 20344
`from MEM 10112 through JPD Bus 10142. EUSITT 20344's first input is an address lADR) input connected
`from output of Address Driver (ADRD) 25522 and NAG 20340. Address inputs provided by ADRD 2552
`select word locations within EUSITT 20344 for writing of microinstructions into EUSl'lT 20344. or for
`reading of microinetructlons from EUSITT 20344 to mCRD 20346 to control operation of EU 10122.
`Generation of these address inputs to EUSITT 20344 by NAG 20340 will be described further below.
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`d.d. Microcode Control Decode Register 20346
`Output of EUSl'iT 20344 is connected to input of mCRD 20346. As previously described, mCRD 20346 is
`a register for receiving microinstructions from EUSITT 20344, and decoding logic for decoding those
`mlcrolnstructions and providing corresponding control signals to EU 10122. As indicated in Fig. 255,
`Diagnostic processor Micro-Program Register (DPmR) 25524 is a 60 bit register connected in par-allelwith
`output of EUSITT 20344 to input of mCRD 20346. DPmR 25524 may be loaded with 60 bit microinstructions
`by DP 10118. Diagnostic microinstructlons may thereby be provided directly to input of mCRD 20346 to
`provide direct microinstruction by microinstruction control of EU 10122.
`Outputs of mCRD 20346 are provided, in general, to all portions of EU 10122 to control detailed
`operations of EU 10122. Certain outputs of mCRD 20345 are connected to inputs of Next Address Source
`Select Multiplexer (NASSl 25526 and Long Branch Page Address Gate (LBPAGl 25528 and NAG 20340. As
`will be described further below, these outputs of mCFiD 23046 are used in generating address inputs to
`EUSI'lT 20344 when particular microinstructions sequences can for Jumps or Long Branches to other
`microinstruction sequences. Outputs of mCRD 20346 are also connected in parallel to inputs of Execution
`Unit Micro-lnstmction Parity Check Logic lEUmlPC) 25530. EUmlPC 25530 checks parity of all
`mlcroinstruction outputs of mCFlD 20346 to detected errors in mCRD 2034625 outputs.
`
`—
`e.e. Next Addrew Generator 20340
`As described above, read and write addresses to EUSITT 20344 provided by NAG 20340 through ADRD
`25522. Address inputs to ADRD 255R are provided from either NASS 25526 or Diagnostic Processor
`Address Register (DPAR) 25532. In normal operation. address inputs to EUSITT 20344 are provided from
`NASS 25526 as will be described momentarily. DP 10118, however, may load EUSITT 20344 addresses into
`DPAR 25532. These addresses may then be read from DPAR 25532 through ADRD 25522 to individually
`select address locations within EUSl'iT 20344. DPAR 25532 may be utilized. in particular, to provide
`addresses to allow stepping through of EU 10122 mlcroinstruction sequences microinstruction by
`microinstructicn.
`As described above, NASS 25526 is a multiplexer having inputs from three NAG 20340 address
`sources. NASS 25526's first address input is from Jump (JMP) output of mCRD 20346 and LBPAG 25523.
`These address inputs are utilized, in part, when a current microinstruction calls for a Jump or Long Branch
`to another microinstruction or microinstruction sequence. Second address source is provided from SAS
`25520 and. in general, is comprised of starting addresses of microinstruction sequences. SAS 25520 is a
`multiplexer having a first input from CQAS 25512 and COAE 25516, that is starting addresses of
`microinstruction sequences corresponding to SOPs or for servicing JP 10114 Events. A second SAS 25520
`input is provided from Sub—routine Return Address Stack (SUBRA) 25534. in general, and as will be
`described further below. SUBRA 25534 operates as a stack mechanism for storing current microinstruction
`addresses of interrupted microinstruction sequences. These stored addresses may subsequently be
`utilized to resume execution of those interrupted microinstructlon sequences. Third address source to
`NASS 25526 is provided from Sequential and Case Address Generator (SCAG) 25536. In general, SCAG
`25536 generates address to select sequential microinstructions within particular microinstruction
`sequences. SCAG 25536 also generates microinstruction address for microinstruction Case operations. As
`indicated in Fig. 255, outputs of SCAG 25536 and of SAS 25520 are bused together to comprise a single
`NASS 25526 input. Selection between outputs of SCAG 25536 and SAS 25520 are provided by control
`inputs (not shown for clarity of presentation) to SCAG 25536 and SAS 25520. Selection between NASS
`25526's address inputs is controlled by Next Address Source Select Control Logic (NASSC) 25538, which
`provides control inputs to NASS 25526. NASSC 25538 is effectively a multiplexer receiving control inputs
`from TSTCON 20386 and TSTINT 20320. As will be described further below. TSTCON 20386 monitors
`certain operating conditions or states within EU 10122 and provides corresponding inputs to NASSC 25533
`NASSC 25538 effectively decodes these control inputs from TSTCON 20386 to provide selection control
`input to NASS 25526.
`Having described overall structure and operation of NAG 20340, operation at NAG 20340 will be
`
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`Petitioner Apple Inc. - Ex. 1025, p. 4003
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`Petitioner Apple Inc. - Ex. 1025, p. 4003
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`er 0 067 555 31
`described in further detail next below.
`Fiefening first to NASS 25526's address inputs provided from JMP output of mCRD 20346 and LBPAG
`25528, this address source is provided to allow selection of a next microinstruction by a current
`microinstruction. JMP output of mCRD 20346 allows a current microinstruction to direct a Jump to another
`microinstruction within the same page of EUSITT 20344. NASS 25525's input through LBPAG 25528 is
`provided from another portion of mCRD 20346’: output specifying pages within EUSITT 20344. This input
`through LBPAG 25528 allows execution of Long Branch operations, that isjumps from a microinstruction in
`one page of EUSITT 20344 to a microinstruction in another page. In addition, NASS 25526’s input from JMP
`output of mCRD 20346 and through LBPAG 25528 is utilized to execute an idle, or Standby, routine when
`EU 1012 is not currently executing a microinstruction sequence requested by FU 10120. In this case, idle
`routine directs TSTCON 20386 to monitor EU 10122 Dispatch Pointer inputs to EU 10122 from FU 10120. If
`no EU 10122 Dispatch Pointers are present in COMO 20342, or none are pending, TSTCON 20386 will direct
`NASSC 25538 to provide control inputs to NASS 25526 to select NASS 25526's input from mCFiD 20346 and
`LBPAG 25528. idle routine will continually test for EU 10122 Dispatch pointer inputs until such a Dispatch
`Pointer is received into COMO 20342. At this time, TSTCON 20386 will detect the pending Dispatch Pointer
`and direct NASS 25538 to provide control outputs to NASS 25526 to select NASS 25526's input from, in
`general, SAS 25520. TSTCOND 20386 and NASSC 25538 will also direct NASS 25526 to select inputs from
`SAS 25520 upon return from a called microinstmction to a previously interrupted microinstruction
`sequence.
`
`As described above, SAS 25520 receives starting addresses from COMO 20342 and lrorn SUBRA
`255%. SAS 25520 will select the output of COAS 25512 or of COAE 25516 as the input to NASS 25526 when
`a new microinstruction sequence is to be initiated to execute a user's program SOP or to service a JP 10114
`Event. SAS 25520 will select an address output of SUBRA 25534 upon return from a called sub-routine to a
`previously executing but interrupted sub-routine. SUBRA 25534, as described above, is effectively a stack
`mechanism for storing addresses of currently executing microinstructions when those microinstruction
`sequences are interrupted. SUBRA 25534 is an 11 bit wide by 8 word deep register with certain registers
`dedicated for use In stacking Event Handling microinstruction sequences. other portions of SUBRA 25534
`are utilized for stacking of microinstruction sequences for executing SOPs. that
`is for stacking
`microinstruction sequences wherein a first microinstruction sequence calls for a second microinstruction
`sequence. SUBRA 25534 is not operated as a first-in-first out stack, but as a random access memory
`wherein address inputs selecting registers and SUBRA 25534 are provided by microinstmction control
`outputs of mCRD 20346. Operations of SUBRA 25534 as a stack mechanism is thereby controlled by the
`microinstruction sequences stored in EUSl'iT 20344. As indicated in Fig. 255, addresses of current
`rnicroinstructions of interruptedmicroinstruction sequences are provided to data input of SUBRA 25534
`from output of SCAG 25536, which will be described next below.
`sequential
`to select
`As described above, SCAG 25536 generates
`sequential addresses
`microinstructions within microinstruction sequences and to generate microinstruction addresses for Case
`operations. SCAG 25536 includes Next Address Register (NXTRD 25540, Next Address Arithmetic and Logic
`Unit (NAALU) 25542, and SCASE 25518. NAALU25542 is a 12 hit arithmetic and logic unit. Aflrst eleven bit
`input of NAALU 25542 is conneued from output of ADRD 255a and is thereby cunent address provided to
`EUSITIT 20344. A second four bit input to NAALU 25542 is provided front output of SCASE 25518. During
`sequential execution of a microinstruction sequence, output of SCASE 25518 is binary zeros and carry input
`of NAALU is forced to 1. Output of NAALU 25542 will thereby be and address one greater than the current
`microinstruction address provided to EUSITI’ 20344 and will thereby be the address of the next sequential
`microinstruction. As indicated in Fig. 255, SCASE 25518 receives an input from output of SCALER 20338.
`This input is utilized during Case operations and allows a data sensitive number to be selected as SCASE
`25518's output into second input of NAALU 25542. SCASE 2551_8_'s input from SCALER 20338 thereby
`allows NAG 20340 to perform microinstruction Case operations wherein Case Values are determined by the =
`contents of SCALER 20338.
`
`Next address outputs of NAALU 25542 are loaded into NXTR 25540, which is comprised of tri-state
`output registers. Next address outputs of NXTR 25540 are connected, in common with outputs of SAS
`25520, to second input of NASS 25526 as described above. During normal execution of microinstruction
`sequences,
`therefore, SCAG 25536 will, through NASS 25526 and ADRD 2552. select sequential
`microinstructions from EUSl1'T 20344. SCAG 25536 may also, as just described, provide next
`microinstruction addresses in microinstruction Case operations.
`In summary, NAG 20340 is capable of performing all usual microinstruction sequence addressing
`operations. For example, NAG 20340 allows
`selection of next microinstructions by current
`microinstructions, either for Jump operations or Long Branch operations, through NASS 25526's input
`from mCRD 20346's JMP or through LBPAG 25528. NAG 20340 may provide microinstruction sequence
`starting addresses through COMO 20342 and SAS 25520, or may provide return addresses to interrupted
`and stacked microinstruction sequences through SUBRA 25534 and SAS 25520. NAG 20340 may
`sequentially address microinstiuctions of a particular microinstruction sequence through operation of
`SCAG 25536, or may perform mciroinstruction Case operations through SCAG 25536.
`
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`Petitioner Apple Inc. - Ex. 1025, p. 4004
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`Petitioner Apple Inc. - Ex. 1025, p. 4004
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`EP 0 067 556 B1
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`2. Operand Buffer 20322
`Having described structure and operation of EUCL 20310, structure and operation of OPB 20322 will be
`described next below. As previously described, OPB 20322 receives operands, that is data, from MEM
`10112 and FU 10120 through MOD Bus 10144 and JFD Bus 10142. OPB 20322 may then perform certain
`operand format translations to provide data to MULT 20314 and EXP 20316 in the formats most efficiently
`utilized by MULT 20314 and EXP 20316. As previously described, EU 10122 may perform arithmetic
`operations on integer, packed and unpacked decimal, and single or double precision floating point
`numbers.
`In summary, therefore, OPB 2032 is capable of accepting integer, single and double precision floating
`point, and packed and unpacked decimal operands from MEM 10112 and FU 10120 and providing
`appropriate fields of those operands to MULT 20314 and EXP 20316 in the formats most efficiently utilized
`by MULT 20314 and EXP 20316. in doing so, OPB 20322 extracts exponent and rnantissa fields from single
`and double precision floating point operands to provide exponent and mantissa fields of these operands to,
`respectively, EXP 20316 and MULT 20314, and also unpacks, or converts. unpacked decimal operands to
`packed decimal operands most afficiently utilized by MULT 20314.
`Having described structure and operation of OPB 20322, structure and operation of MULT 20314 will be
`described next below.
`
`3. Multiplier 20314 (Figs. 257. 258)
`MULT 20314, as previously described, performs addition, subtraction. multiplication, and division
`operations on mantissa fields of single and double precision floating point operands, integer operands, and
`decimal operands. As described above with reference to OPB 20322, OPB 20322 converts unpacked decimal
`operands to packed decimal operands to be operated upon by MULT 20314. MULT 20314 is thereby
`effectively capable of performing all arithmetic operations on unpacked decimal operands.
`
`a.a. Multiplier 20314 Data Paths and Memory (Fig. 257)
`Referring to Fig. 257, a more detailed block diagram of MULT 20314's data paths and memory is
`shown. As previously described, major elements of MULT 20314 include memory elements comprised of
`MULTRF 20350 and CONST 20360, operand input and result output multiplexing logic including MULTIM
`20328 and MULTRM 20334, and arithmetic operation logic. MULT 20314's operand input and result output
`multiplexing logic and memory elements will be dwcribed first, followed by description of MU LT 20314's
`arithmetic operation logic.
`_
`As previously described, input data, including operands, is provided to MULT 20314's arithmetic
`operation logic through MUL‘l1N Bus 20354. MUL11N Bus 20354 may be provided with data from three
`sources. A first source is CONST 20360 which is a 512 word by 32 bit wide Read Only Memory. CONST
`20360 is utilized to store constants used in arithmetic operations. In particular, CONST 20360 stores zone
`fields for unpacked decimal. that is ASCI character, operands. As previously described, unpacked decimal
`"operands are received by OPB 20322 and converted to packed decimal operands for more efficient
`utilization by MULT 20314. As such. final result outputs generated by MULT 20314 from such operands are
`in packed decimal format. As will be described below, MU LT 20314 may be utilized to convert these packed
`decimal results into unpacked decimal results by insertion of zone fields. As indicated in Fig. 257, address
`inputs are provided to CONST 20360 from EXPO Bus 20325 and from output of mCRD 20346. Selection
`between these address inputs is provided through CONST Address Multiplexer (CONSTAM) 291 0. CONST
`20360 addresses will, in general, be provided from EUCL 20310 but alternately may be provided from EXPO
`Bus 20325 for special operations.
`Operand data is provided to MULTIN Bus 20354 through MUL1'lM 20328, which is a dual input, 64 bit
`multiplexer. A first input of MULTIM 20328 is provided from OP0 Bus 20323 and is comprised of operand
`information provided from OPB 20322. OPO Bus 20323 is a 56 bit wide bus and operand data appearing
`thereon may be comprised of 32 bit integer operands; 32 bit packed decimal operands, either provided
`directly from OPB 20322 or as a result of OPB 20322‘s conversion of an unpacked decimal to a packed
`decimal operand; 24 bit single precision operand rnantissa fields; or 56 bit double precision floating point
`operand mantissa fields. As previously described, certain OPO Bus 20323 may be zero or sign extension
`filled, depending upon the particular operand.
`Second input of MULTIM 20328 is provided from MULTRF 20350. MULTRF 20350 is a 16 word by 64 bit
`wide random access memory. As indicated in Figs. 203 and 257, MULTFIF 20350 is connected between
`output of RFR 20336. through FR Bus 20337, and to input of MULT 20314's arithmetic operation logic
`through MULTIM 20328 and MULTIN Bus 20354. MULTRF 20350 may therefore be utilized as a scratch pad
`memory for storing intennediate results of arithmetic operations,
`including reiterative arithmetic
`operations. In addition, a portion of MULTRF 20350 is utilized. as in GHF 10354, as an EU 10122 Stack
`Mechanism slmilarto MIS 10368 and M05 10370 in FU 10120. Operation of EU 10122 Stack Mechanism will
`be described in a following descripion of EU 10122's interfaces to MEM 10112 and FU 10120. Address
`inputs (ADR) of MULTRF 20350 are provided. ,fror_n_.l\‘liultlpller. Register File Address Multiplexer
`(MULTRFAM) 25712.
`-
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`Petitioner Apple Inc. - Ex. 1025, p. 4005
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`Petitioner Apple Inc. - Ex. 1025, p. 4005
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`EP 0 067 556 B1
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`MULTRFAM 2912 is a dual four bit multiplexer comprised, for example, of SN74S258s. in addition to
`address inputs to MULTRF 20350, MULTRFAM 25712 provides address inputs to EXPRF 20380. As
`previously described. MULTRF 20350 and EXPRF 20380 together comprise an EU 10122 general register file
`similar to GRF 10354 and FU 10120. As such. MULTRF 20350 and EXPRF 20380 are addressed in parallel to
`read and write parallel entries from and to ‘MULTRF 20350 and EXPRF 20380. Address inputs to MULTRFAM
`25712 are provided, first, from outputs of mCRD 20346, thus providing microinstrucflon control of
`addressing of MULTRF 20350 and EXPRF 20380. Second address input to MULTRFAM 2912 is provided
`from output of Multiplier Register File Address Counter (MULTRFAC) 25714.
`MULTRFAC 26714 is a four bit counter and is used to generate sequential addresses to MULTRF 20350
`and EXPRF 20380. initial addresses are loaded into MULTRFAC 2914 from Multiplier Register File Address
`Counter Multiplexer (MULTRFACM) 2916. MULTRFACM 2916 is a dual four bit multiplexer. Inputs to
`MULTRFACM 25716 are provided. first, from outputs of mCRD 20346. This input allows microinstruction
`selection of an initial address to be loaded into MULTRFAC 2914 to be subsequently used and generating
`sequential MULTRF 20350 and EXPRF 20380 addresses. Second address input to MULTRFACM 25716 is
`provided from OPQ Bus 20323. MULTRFACM 2916's input from OPQ Bus 20323 allows a single address. or
`a starting address of a sequence of addresses, to be selected through JPD Bus 10142 or MOD Bus 10144, for
`example from MEM 10112 or FU 10120.
`lntenhediate and final result outputs of MULT 20314 arithmetic logic are provided to data inputs of
`MULTRF 20350 directly from FR Bus 20337 and from MULTRM 20334. inputs to MULTRM 20334, in turn. are
`provided from FR Bus 20337 and from output of CONSIZE 20352 and TSTINT 20320.
`FR Bus 20337 is a 64 bit bus connected from 64 bit output of RFR 20336 and carries final and
`intermediate results of- MULT 20314 arithmetic operations. As will become apparent in a following
`description of MULT 20314 arithmetic operation logic, RFR 20336 output. and thus FR Bus 20337, are 64 bits
`wide. Sixty-four bits are provided to insure retention of all significant data bits of certain MULT 20314
`arithmetic operation lntennediate results, in particular operations involving double precision floating point
`64 bit mantissa fields. In addition, as will be described momentarily and has been previously stated, MULT
`20314 may comrert a final result in packed decimal format into a final result in unpacked decimal format. in
`this operation. a single 32 bit, or one word, packed decimal result is convened into a 64 bit. or two word.
`unpacked decimal format by insertion of zone fields.
`As described above, two parallel data paths are provided to transfer information from FR Bus 20337
`into MULTRF 20350. First path is directly from FR Bus 20337 and second path is through Unpacked Decimal
`Multiplexer (UPDM) 2918 of MULTRM 2034. Direct path is utilized for thirty-two bits of information
`comprising bits 0 to 23 and bits 56 to 63 of FR Bus 20337. Data path through UPDM 2918 may comprise
`either bits 24 to 55 of FR Bus 20337, which are connected into a first input of UPDM 25718, or bits 40
`through 55 which are connected to a second input of UPDM 25718. Single precision floating point numbers
`are 32 bit numbers plustwo or more guard bits and are thus written into MULTRF 20350 through bits 0 to 23
`of the direct path into MULTRF 20350 and through first input (bits 24 to 55) of UPDM 2918. Double
`precision floating point numbers are 5 bits wide, plus guard bits, and thus utilize the direct path into
`MULTRF 20350 and the path through first input of UPDM 25718. Bits 56 to 63 of direct path are utilized for
`guard bits of double precision floating point numbers. Both integer and packed decimal numbers utilize
`bits 24 through 55 of FR Bus 20337, and are thus written into MULTRF 20350 through first Input of UPDM
`25718. As previously described, bits 0 to 23 of these operands are filled by sign extension.
`
`a.a.a. Container Size Check
`As stated above, MULTRM 20334 has an input from CONSlZE 20357. As will be described below with
`reference to TSTINT 20320, CONSIZE 20352 performs a "container size" check upon each store back of
`results from EU 10122 to MEM 101 12. CONSIZE 20352 compares the number of significant bits in a result to
`be stored back to the logical descripto