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`United States Patent [19]
`Lloyd et al.
`
`[11]
`[45]
`
`4,131,919
`Dec. 26, 1978
`
`[54] ELECTRONIC STILL CAMERA
`[75] Inventors: Gareth A. Lloyd; Steven J. Sasson,
`both of Rochester, N.Y.
`Eastman Kodak Company,
`Rochester, N.Y.
`[21] Appl. No.: 798,956
`[22] Filed:
`May 20, 1977
`
`[73] Assignee:
`
`[51] Int. C1.2 ............................................. .. H04N 5/79
`[52] US. Cl. ........................................ .. 360/9; 360/35;
`.
`358/127; 358/134; 358/213
`[58] Field of Search ................... .. 360/9, 10, 8, 35, 33;
`179/2 TV; 358/127, 134, 213, 85, 133, 78
`References Cited
`U.S. PATENT DOCUMENTS
`
`[56]
`
`3,858,232 12/ 1974 Boyle ................................... .. 357/24
`3,911,467 10/1975 Levine
`358/213
`
`. . . . .. 360/37
`6/1976 Lemke . . . . .
`3,962,725
`...... .. 360/9
`4/1977 Pandey
`4,016,361
`4,057,830 11/1977 Adcock ........ .; ...................... .. 360/35
`Primary Examiner—Bernard Konick
`Assistant Examiner-Alan Faber
`Attorney, Agent, or Firm-D. P. Monteith
`
`ABSTRACT
`[57]
`Electronic imaging apparatus, preferably an electronic
`still camera, employs an inexpensive information
`recording medium such as audio-grade magnetic tape
`for “capturing” scene images. The camera includes a
`charge coupled device comprised of an array of photo
`sensitive elements which form a charge pattern corre
`sponding to an optical image projected onto the ele
`ments during an exposure interval. A charge transfer
`circuit converts the charge pattern into a high fre
`quency pulsed electrical signal immediately following
`the exposure interval to remove the charge from the
`device in a short period of time to maintain unwanted
`“dark current” at a low level. Each pulse represents the
`image-forming light projected onto a particular photo
`sensitive element. A high speed analog-to-digital con
`verter converts these pulses to multi-bit digital words in
`real time. A digital buffer memory temporarily stores -
`these words, then retransmits them at a rate that is com
`patible for recording on the audio-grade tape. The
`image can be displayed on a conventional television
`receiver by reading the recorded words from the tape
`and converting them to a format compatible with the
`signal-receiving circuitry of the television.
`
`8 Claims, 4 Drawing Figures
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`U.S. Patent Dec. 26, 1978
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`Sheet 1 of 2
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`4,131,919
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`88
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`PRIOR ART
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`ELECTRONIC STILL CAMERA
`BACKGROUND OF THE INVENTION
`Field of the Invention
`This invention relates in general to electronic imag
`ing apparatus and in particular, to an electronic still
`camera that employs a non-volatile reuseable storage
`medium for recording scene images.
`Description of the Prior Art
`Conventional cameras employ a shutter for exposing
`for a limited duration photographic ?lm located at a
`?lm exposure plane. Film processing solutions are re
`quired to produce a visible image of trhe photographed
`scene. As is well known, processed photographic ?lm
`may not be reused.
`‘
`Recently, considerable effort has been given to the
`development of solid-state elements for imaging pur
`poses. Such elements offer an advantage over photo
`graphic ?lm in that, theoretically, they can be reused
`any number of times for imaging.
`A solid-state imaging element of the type known as a
`charge transfer device can include a semiconductive
`substrate doped with majority carriers and covered
`with a thin insulating ?lm upon which is located an
`array of electrically conductive electrodes. A depletion
`region or potential well is formed within the semicon
`ductor under electrodes biased by a voltage of the
`proper polarity. The use of a charge transfer device
`involves the basic concept of forming a charge pattern
`consisting of packets of minority carriers in the poten
`tial wells. In the course of an optical imaging process,
`photons incident upon the semiconductor generate mi
`nority carriers within these potential wells in propor
`tion to the amount of light impinging upon the semicon
`ductor in the near vicinity of each well. These packets
`can be transferred through the semiconductor by se
`quentially biasing the electrodes. The potential wells
`e?'ectively “move” through the semiconductor sweep
`ing the minority carriers along within the wells. At an
`appropriate location these packets may be detected, for
`example, by removing them sequentially from the semi
`conductor by means of a reverse-biased diode coupled
`to transfer electrodes. An arrangement for read-out of
`45
`information from a charge transfer device is disclosed in
`IEEE Transactions 0n Electron Devices, Vol. ED-20,
`No. 6, June 1973, in an article entitled “interlacing In
`Charge Coupled Imaging Devices”, by Carlo H. Se
`
`25
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`2
`that includes a charge transfer device, and recording
`apparatus that employs an inexpensive information
`recording medium which is non-volatile and reuseable,
`such as a magnetic tape, disc or drum. The camera also
`includes a conventional shutter mechanism for exposing
`the transfer device to re?ected scene light for a duration
`related to scene brightness. The rate of read-out of the
`signals produced by the charge transfer device is syn
`chronized with the speed of the recording apparatus
`since the transfer device output is connected directly to
`the input of the recording apparatus. These signals are
`read-out at a relatively slow speed to record a scene
`image on the storage medium that is employed. It takes
`approximately one second to output scene information
`from the charge transfer device. For “stop-action” pho
`tography an exposure interval of approximately 1/20
`second or less is needed. Accordingly, the charge trans
`fer device is used both for imaging and until scene infor
`mation is read-out, for data storage.
`That camera suffers from the disadvantage that the
`charge pattern related to the incident illumination will
`be adversely affected by thermally generated minority '
`carriers. Not only would it be expected that signi?cant
`dark current would be produced with a l-second stor
`age interval, but it could also be expected that the “dark
`current” would be nonuniform. This is because the
`storage interval for any potential well, and accordingly
`the number of thermally generated minority carriers in
`that well, is dependent upon whether or not that poten
`tial well is among the ?rst or the last to sweep through
`the semiconductor to an output transfer electrode. Fur
`thermore, saturation of some potential wells may occur
`if too many minority carriers are thermally generated.
`Excess minority carriers would spread to adjacent po—
`tential wells to be added to minority carriers in non.
`saturated potential wells.
`SUMMARY OF THE INVENTION
`An object of the present invention is to provide im
`proved electronic imaging apparatus.
`In accordance with the above object, the present
`invention is addressed to an electronic still camera
`which includes a solid-state imaging device that pro
`duces a charge pattern corresponding to an optical
`image projected onto an imaging surface during an
`exposure interval. Charge transfer means converts such
`charge pattern into a high frequency pulsed electrical
`signal within a relatively brief time after termination of
`the exposure interval. Electrical signal transforming
`means receives data corresponding to this electrical
`signal in real time, then retransmits such data at a sub
`stantially slower rate to recording apparatus. This
`slower data rate permits recording of signals corre
`sponding to the optical image on an inexpensive record
`ing medium such as audiograde magnetic tape.
`The invention, and its objects and advantages, will
`become more apparent in the detailed description of a
`preferred embodiment presented below.
`BRIEF DESCRIPTION OF THE DRAWINGS
`In the detailed description of a preferred embodiment
`of the invention presented below, reference is made to
`the accompanying drawings in which:
`FIG. 1 pictorially represents an electronic still cam
`era in accordance with the teachings of the present
`invention;
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`As with conventional photographic ?lm, to obtain a
`scene image having a proper contrast, the imaging ele
`ment must not be overexposed, or, in other words, the
`potential wells must not be saturated with minority
`carriers during the exposure interval. However, even in
`the absence of illumination, the regions constituting the
`potential wells tend to saturate with the passage of time
`by means of the thermal generation of minority carriers.
`Carriers generated in this manner constitute an un
`wanted signal commonly known as a “dark current”. It
`60
`is important that this signal be only a small fraction of
`the signal produced by incident illumination, particu
`larly if the dark current is non-uniform over the imaging
`area.
`U.K. Pat. No. 1,440,792, entitled ELECTRONIC
`65
`STILL PICTURE CAMERA, and US. Pat. No.
`4,057,830 which corresponds thereto and is entitled
`Electronic Photography System, disclose a camera for
`electronically recording “stop-action” or still pictures
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`FIG. 2 is a schematic block diagram of a solid-state
`When a CCD is used as an imaging device, charge
`image sensor, and signal processing circuitry in the
`carriers are produced by light quanta absorbed in the
`silicon, the number of carriers being proportional to the
`camera of FIG. 1;
`-
`amount of radiant energy reaching the silicon. During
`FIG. 3 is a drawing of waveforms to help explain the
`operation of the solid-state image sensor and signal
`the so-called “integration time”, comparable to the
`processing circuitry of FIG. 2; and
`-
`exposure time in conventional camera art, the CCD
`address circuit applies voltages to the gate electrode
`FIG. 4 is a perspective view of apparatus for display
`array to provide a pattern of photosites having potential
`ing pictures of scenes recorded by the camera of FIG. 1.
`wells which attract charged minority carriers. A charge
`pattern will form in the potential wells under the vari
`ous photosites nearest to ‘where the charges are pro
`duced. The number of charge carriers which ‘accumu
`late in each potential well during the integration time is
`proportional ,to the amount of radiant energy reaching
`that well and this, in turn, is proportional to the radia
`tion intensity and the duration of the integration time.
`Thus, a spatial pattern of carriers corresponding to an
`optical image is produced by the .CCD. For further,
`more detailed-descriptions of CCD’s, reference is made
`to one of the numerous publications on such devices,
`US. Pat. No. 3,858,232, entitled INFORMATION
`STORAGE DEVICES, the disclosure of which is in
`corporated herein by reference. ,
`,
`‘By the, proper manipulation of voltage potentials to
`the, interconnected rows (or columns) of electrodes
`following this integration time, this charge pattern can
`be shifted to one point of the CCD, where, by means of
`a suitable output connection the charge collected can be
`removed sequentiallyv into the aforementioned data
`readout register. This stream of charge then constitutes
`an electrical current'which is an analog replica of the
`light projected onto-the CCD. Such a current is caused
`to ?ow through an output load to generate a train of
`voltage pulses, each pulse representing one small area of
`the projected image with pulse amplitude being propor
`tional to'the amount of radiation reaching a particular
`
`35
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`photosite. ,
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`With our presently .preferred CCD apparatus, an
`image is formed in two separate, interlaced ?elds, each
`?eld containing one-half thetotal number of photosites.
`Photosites are formed in the ?rst ?eld for 25 millisec
`onds (ms), then photosites are formed in the second. ?eld
`for the next 25ms interval, the total “exposure interval”
`being SOms. While charge packetsvare formed in the
`second ?eld, the charge pattern in thev?rst field is read
`out and converted to a train of voltage pulses, the pulse
`repetition rate being inversely proportional to the inter
`val used for read-out. For detailed descriptions of CCD
`interlacing techniques and apparatus, reference is made
`to US. Pat. No. 3,911,467, entitled .INTERLACED
`READOUT .OF CHARGE STORED IN CHARGE
`COUPLED IMAGESENSING ARRAY, and to the
`aforementioned article by C. H. Sequin.
`-
`Since the ?elds are interlaced, scene information is
`reorganized so asnot to be presented for display in the
`same interlaced timing format. Apparatus for data reor
`ganization is provided by the aforementioned data re
`trieval apparatus.
`-
`-A type 201 CCD, manufactured by the Fairchild
`Camera and Instrument Company (FCI), includes a 100
`X 100 photosite array. For that CCD, an optical image
`may be represented by a CCD output pulse train of
`lO-thousand pulses. Four pulses of such a train are de
`noted A in FIG. 2.
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`‘Two of the clock signals associated with CCD 19 are
`illustrated schematically in FIG. 3. Waveform 22 con
`stitutes a master clock signal and is used to signal the
`beginning and end of a pulse train that represents an
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`DESCRIPTION OF A PREFERRED
`EMBODIMENT
`The present description will be directed in particular
`to elements forming part of, or cooperating more di
`rectly with, apparatus in accordance with the present
`invention. It is to be understood elements not speci?
`cally shown or described may take various forms well
`known to those having skill in the art.
`'
`There is shown in ‘FIG. 1 of the drawings an elec
`tronic still camera, designated generally by ‘the numeral
`10. As with conventional still cameras of the type that
`employ photographic ?lm for “capturing” light from a
`scene being photographed, camera 10 includes a hous
`ing 12, a view?nder 14, and a taking lens 15 (shown in
`FIG. 2) located within a lens barrel 16. A diaphragm
`mechanism 17 (shown in FIG. 2), coupled to an expo
`sure control circuit 18 (also shown in FIG. 2), forms ‘a
`variable aperture aligned with lens 15 to control the
`amount of scene light transmitted through'the lens.
`Diaphragm control is automatic and is provided by
`means, well known in the art, that controls the lens
`aperture in accordance with the intensity of re?ected
`scene light, the control being effected by the current
`produced by a photoconductive element, such as a pho
`tocell, of circuit 18. Photoconductively controlled dia
`phragm mechanisms are well known in the art and are
`disclosed in several patents, one of which is US. Pat.
`No. 3,962,707 ?led in the name of F. M. Galbraith, Jr.
`and commonly assigned herewith. ,
`/
`Unlike conventional still cameras that employ photo
`graphic ?lm, camera 10 employs a solid-state image
`sensor 19 (shown in FIG. 2), located at the focal plane
`of lens 15, and a record storage medium, such as, for
`example, reuseable magnetic tape, for recording electri
`cal signals corresponding to scene images projected
`onto the imaging surface of sensor 19. The tape may, for
`example, be located in a magnetic tape cassette 20,
`which is located in a cassette-receiving chamber 21.
`Chamber 21 is accessible through a camera door (not
`shown) and includes means (also not shown) for remov
`ably mounting the cassette 20 in the chamber. Cassette
`20 is adapted to be connected to suitable data retrieval
`apparatus, as referred to hereinafter, to obtain visual
`displays of recorded scenes.
`Sensor 19 constitutes a charge transfer device and, in
`particular, is a charge coupled device (CCD), which
`produces a pattern of charge carriers that is an analog
`representation of an optical image focused onto an im
`aging surface of the CCD. As is known in the art, a
`CCD may include a silicon substrate covered by oxi
`dized silicon, with an array of closely spaced conduct
`ing pads on the silicon dioxide surface. The pads serve
`as gate electrodes and may, for example, be formed by
`selectively doping a layer of transparent polysilicon
`material. These gate electrodes are interconnected in
`rows (or columns), which are electrically connected to
`both a CCD address circuit for sequentially applying
`gate electrode voltages, and to a data readout register.
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`ple, commence in timed relation to the capacitor being
`image projected onto the CCD during one “exposure
`charged to such level Photoconductively controlled
`interval", e.g. 50ms. For a pulse train duration of, for
`timing circuits are well known in the art and are dis
`example, 50ms, waveform 22 would be a 20 cycle per
`closed in many patents, one of which is US. Pat. No.
`second (Hz) signal. (The duration of such a pulse train
`3,672,267, entitled SEQUENTIAL CONTROL FOR
`and an exposure interval need not be the same.) Wave
`CAMERA DIAPHRAGM AND SHUTTER, and
`form 23 is a high-frequency signal that is used to syn
`commonly assigned herewith.
`chronize the operation of signal processing circuitry,
`An important feature of our invention is, however,
`denoted generally 24, with the occurrence of each pulse
`that read-out of the charge pattern for each ?eld occurs
`in the CCD output signal, as explained in detail herein
`rapidly so that the CCD is not employed for any signi?
`after. If 10,000 pulses are produced in a 50ms interval,
`cant period of time as a storage device.
`waveform 23 would be a ZOO-thousand Hz signal.
`Referring now to FIG. 2, there is shown a schematic
`In accordance with our invention, light from a scene
`diagram of signal processing circuitry 24 for obtaining
`to be recorded is “captured” electronically in the fol
`still pictures of scenes imaged onto CCD 19. Circuit 24
`lowing manner. A camera operator ?rst actuates a
`includes generally a power control circuit 25, and im
`power control member to apply electrical power to
`age-sensor apparatus 26, including CCD 19, for produc
`circuitry 24. At that instant, CCD address circuits cause
`ing a high frequency pulsed electrical signal corre
`the CCD to commence producing its pulsed output
`sponding to an imaged scene, each pulse in the signal
`signals, a pulse train being produced for each exposure
`having an amplitude proportional to the amount of light
`interval. In addition, light-sensitive exposure control
`impinging on a particular photosite of the CCD. A
`20
`circuit 18 positions diaphragm 17 to form a lens aper
`circuit 27 constitutes an electronic shutter to control the
`ture in accordance with the level of ambient light. No
`signal produced by CCD 19 that is to be recorded. An _
`CCD output pulse train is processed, however, until a
`analog-to-digital (A/D) converter circuit 28 converts in
`second control member is actuated. Once such actua
`real time the signal transmitted by circuit 27 into multi
`tion occurs, a CCD output signal, representing an opti
`bit digital words. Buffer circuitry 29 functions to re
`cal image projected onto an imaging surface during one
`ceive and temporarily store such words in real time,
`exposure interval, is processed. Each CCD pulse for the
`then transmits them at a rate that is substantially lower
`interval is digitized in real time to form a digital word,
`than the real time rate at which these words are loaded
`i.e., a total of 10,000 digital words for the aforemen
`into the buffer. Circuit 24 also includes recording appa~
`tioned type 201 CCD, and such words are advanta
`ratus 30 having a data recording speed that is compati
`geously stored in a high-speed buffer memory. These
`ble with the rate that data is transmitted from buffer 29.
`digital words are sequentially retransmitted, preferably,
`As with a conventional still camera that employs
`after the buffer memory receives the last digital word,
`photographic ?lm to obtain a “photograph” lens barrel
`at a rate that is substantially lower than the CCD pulse
`16 (FIG. 1) is pointed at a scene visible through view
`output rate. This low signal rate permits inexpensive
`?nder 14. Electrical power is provided for circuitry 24
`recording apparatus to be used for recording scene
`from a battery 31 upon actuation of a momentary, push
`information.
`button switch S1 mounted on housing 12, as shown in
`With our presently preferred camera apparatus, the
`FIG. 1. When switch S1 is closed, the baseemitter junc
`scene information for the ?rst ?eld is stored in the
`tion of transistor 32 is forwardly biased to turn the
`buffer memory during the time the charge pattern for
`transistor ON, and collector current ?ows to turn signal
`the second ?eld is formed. Accordingly, the total time
`processing circuitry‘24 ON. At the same time, a bias
`used to “capture” a single scene image and store it in the
`signal is produced on conductor 33 that is applied to a
`buffer memory is approximately 75ms. Scene informa
`set-reset ?ip ?op 34. When this happens, flip ?op 34
`tion is transferred from the buffer to the recording appa
`assumes a set condition and produces at its output 35 a
`ratus in approximately 23 seconds.
`high-level voltage to thereby turn transistor 37 ON.
`With this arrangement, CCD dark current is main
`When a voltage signal above a predetermined level is
`tained at a low level since the CCD is not employed for
`applied to its input 36, ?ip flop 34 switches'into its reset
`information storage in the same sense as is the imaging
`condition and its output 35 produces a low-level voltage
`device employed in the electronic camera disclosed in
`to turn transistor 37 OFF. When this occurs, with
`the aforementioned UK. patent 1,440,792. Further
`switch S1 in its open position, transistor 32 is turned
`more, there is no need to employ expensive recording
`OFF to,remove electrical power from circuitry 24.
`apparatus, such as broadband video apparatus. In fact,
`Image-sensor apparatus 26 includes a CCD address
`recording apparatus having relatively slow recording
`circuit 38, which causes signals 22 and 23 in the form of
`or data-write speeds, such as for example, audio-grade
`clock pulses to be applied to CCD gate electrodes in a
`magnetic recording apparatus, may be utilized to reli
`known manner to produce the aforementioned pulsed
`ably and accurately record information transmitted
`electrical output signal. This output signal is produced
`from the buffer memory.
`during a brief interval immediately following the inte
`It shall be understood that an “integration interval”
`gration time for each of the aforementioned two ?elds
`and the time used to output scene data from the CCD
`so that dark current is maintained at a low level. In a
`for one ?eld need not be predetermined nor of the same
`preferred embodiment, FCI type 201 CCD is employed
`duration. For example, an integration interval and/or
`using a 25ms integration time and 25ms readout interval
`exposure interval could be controlled by a light-sensi
`for each ?eld, the total readout interval being 50ms for
`tive integrating circuit, the control being effected by the
`the signal representing an optical image.
`time required to charge a capacitor to a predetermined
`Image-sensor apparatus 26 also includes a video am
`level by a current through a photoresistive element.
`pli?er 40 to ?lter out noise in the CCD output signal, as
`The capacitor and photoresistor constitute an integrat
`illustrated diagrammatically by the signal waveform B
`ing circuit having a variable time constant related to the
`at the output of ampli?er 40. Since CCD’s typically are
`intensity of the light impinging on the photoresistor.
`sensitive to infrared (IR) radiation, image-sensor appa
`Read-out of scene data from the CCD could, for exam
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`ratus 26 may further include an IR ?lter 41 interposed
`delayed by circuit 48 to synchronize the operation of
`along the optical axis of camera 10 between lens 15 and
`sample-and-hold circuit 46 with the occurrence of each
`CCD 19. Filter 41 blocks IR radiation so the charge
`pulse in waveform B so that pulses are extended at the
`pattern produced by CCD 19 is more closely related to
`proper point in time and with the correct amplitude.
`impinging radiation in the visible spectrum. Factors
`Waveform C is applied to A/D converter 28 which
`affecting CCD performance are discussed in IEEE
`converts each extended pulse into a 4-bit digital word
`having a magnitude representative of pulse amplitude.
`Transactions On Electron Devices, Vol. ED-l8, No. 11,
`November 1971, page 986, entitled “Charge-Coupled
`Converter 49 produces these bits sequentially, the most
`Imaging Devices: Design Considerations”, by G. F.
`signi?cant bit is produced ?rst on output 49a, and the
`least signi?cant bit is produced last on output 49d. A
`Amelio et al.
`.
`As soon as electrical power is applied to circuit 24,
`start-conversion signal is supplied on conductor 50 to
`CCD 19 immediately begins to produce its pulsed elec
`permit converter 49 to commence each signal conver
`trical output signals. For successive 50ms exposure
`sion operation in synchronism with the occurrence of
`intervals families of pulse trains are generated with each
`each waveform C pulse. This is done by means of signal
`pulse train representing the optical image formed dur
`23 which is delayed a predetermined amount by a delay
`ing one such interval. Until momentary, pushbutton
`circuit 51.
`'
`switch S2, mounted on camera 10, is depressed, how
`A digital latch 54 is provided to ensure that the bits
`ever, circuit 27 is effectively disabled, and image data is
`representing each digital word are not changing during
`not transmitted to apparatus 30 for recording. Circuit
`signal transmittal to buffer circuitry 29. A/D converter
`27, in effect, operates as an electronic shutter or gate.
`28 produces an end-of-conversion (EOC) signal on con
`However, unlike a conventional camera shutter which
`ductor 56 once each least signi?cant bit is produced, to
`operates to control the time during which light is al
`signal latch 54 to transmit a digital word to buffer 29.
`lowed to reach a light-sensitive medium, i.e. film, this
`Buffer circuitry 29 constitutes means for receiving
`electronic shutter controls the signal, representing an
`signals in the form of digital words from A/D converter
`optical image, that is to be recorded. The reason circuit
`28 in real time, and transmitting such words at a rate
`27 is effectively disabled immediately after power is
`that is substantially lower than the rate at which these
`applied to circuitry 24 is to permit CCD 19 to clear
`words are received from the A/D converter. Since
`itself of thermal charge prior to recording an image
`digital words representing a single optical image are
`signal. With out presently preferred CCD apparatus, we
`loaded into memory 58 within 50ms, while approxi
`have found that approximately one-half second is
`mately 23 seconds are used to transmit such words from
`needed to clear the CCD of such charge after power is
`the memory to recording apparatus 30, buffer 29 oper
`applied.
`ates to reduce by a factor of approximately 460 the rate
`Circuit 27 operates as follows: Momentary closure of
`that digital words are transmitted to apparatus 30 from
`switch 8; causes a bistable circuit 42 to produce a logic
`the buffer compared to the rate such words are trans
`“1” signal at its output 43. A ?ip ?op 44 produces both
`mitted from the CCD into the buffer. To accomplish
`logic “1” and “0” signals at its output following the .
`this, the buffer 29 includes a highspeed digital memory
`occurrence of odd numbered and even numbered
`58 for temporarily storing words as they are accumu
`pulses, respectively, in the aforementioned 20Hz signal
`lated prior to transmittal from the buffer to recording
`22. Accordingly, an AND gate 45, which conducts in
`apparatus 30. Preferably, buffer 29 is operated to trans
`response to logic “1” signals at each of its inputs, pro
`mit stored words after memory 58 has received the last
`duces a logic “1” output signal following the occur
`word. This is done to simplify the operation of buffer 29
`rence of the ?rst odd numbered pulse in signal 22, after
`and does not operate to signi?cantly increase the time
`switch S2 is actuated. Thelogic “1'” signal turns ON a
`between when the signal is produced by CCD 19 and
`conventional sample-and-hold circuit 46. Circuit 46
`when such signal is recorded by apparatus 30 since all
`serves to extend the duration of each pulse in waveform
`45
`words are loaded into memory 58 within 75ms after an
`B for the period between the trailing edge of one pulse
`exposure interval commences. It shall be understood,
`and the leading edge of the next pulse. Accordingly,
`however, that it is within the spirit and scope of our
`sample-and-hold circuit 46 produces an electrical signal
`invention that signal transferral from memory 58 can
`having a series of contiguous pulses. Such a signal is
`commence as soon as the ?rst digital word is loaded into
`denoted by the letter C in FIG. 2. When the output
`memory.
`signal produced by gate 45 returns to a logic “0” state,
`Buffer 29 operates as follows: The aforementioned
`such as when the next pulse (an even numbered pulse) in
`EOC signal produced on conductor 56 is also applied to
`signal 22 is applied to flip flop 44, circuit 46 is turned
`a memory address counter 60 included within buffer 29.
`OFF. At that time, however, 50ms have passed and an
`Counter 60 serves a record keeping function for mem
`electrical signal representative of a full scene image has
`ory 58 by providing an addressenable signal along input
`been transmitted through sample-and-hold circuit 46.
`address line 61 to control where in memory either write
`When the output of gate 45 is a logic “0”, a logic “1”
`or read operations are to occur. Address counter 60 is
`signal occurs at the output of a bistable circuit 47. This
`initialized to ZERO when AND gate 45 switches its
`logic “1” operates to reset circuit 42 so that its output
`output either from a logic “0” to a logic “1” or from a
`returns to its normal, logic “0” state. This is done to
`logic “1” to a logic “0”. When an EOC signal is pro
`prevent the output of gate 45 re-enabling circuit 46
`duced, counter 60 increments its count by one to permit
`upon the occurrence of the next odd numbered pulse in
`the memory location corresponding to that count or
`waveform 22, without the reactuation of switch S2.
`address to receive a digital word for storage.
`The aforementioned high frequency signal 23 from
`A memory control circiut 62 provides command
`CCD address circuit 38 is used to synchronize the oper
`signals to memory 58 to control whether information is
`65
`ation of sample-and-hold circuit 46 with waveform B. A
`to be written into a read from memory. Control circuit
`delay circuit 48 delays signal 23 to allow for CCD read
`62 is enabled to produce memory write-control and
`out and signal delay through ampli?er 40. Signal 23 is
`read-control signals on conductor 63a when the output
`
`60
`
`50
`
`55
`
`Ex. GOOG 1020
`
`

`
`20
`
`25
`
`4,131,919
`10
`9
`commences to be read from memory 58 to be recorded
`vof gate 45 is a logic “I” and a logic “0”, respectively.
`on the tape once both tape recorder motor 76 is operat
`These write-control and read-control signals turn input
`ing above a predetermined speed, and the last digital
`write-logic and read-logic gates (not shown) ON in
`word has been stored in buffer 29. Since motor 76 does
`' memory 58 to permit data to be written or read, respec
`not reach such speed instantaneously following the
`tively, from memory at the address corresponding to
`actuation of switch 8;, motor speed monitoring circuit
`the count provided by counter 60. Such write-control
`77 is provided to produce a voltage signal having an
`and read-control signals are produced when data-ready
`amplitude proportional to motor speed. This voltage
`signals are provided on input conductor 63c. These
`signal is applied to the input of voltage—sensitive trigger
`data-ready signals occur either when the aforemen
`ci