CMOS Video Cameras
`
`G. Wang, D. Renshaw, P. B. Denyer and M. Lu
`University of Edinburgh
`Department of Electrical Engineering
`Mayfield Road
`Edinburgh, EH9 3JL, UK.
`
`Abstract
`A sirrgle chip CMOS video camera is presented.
`~lorrg ic~irll desigrl reclzriiqite and characterization
`~ ~ ~ s t r i r s . The diip comprises a 312X 287 pixel
`phoro~iiorie orray togetlier with all the necessary
`serrsir~g, addressing and an~plifying circuitry, as
`11:ell us a 1.000 gate logic processor. which
`inrplenrerrts synchronization timing to deliver a
`frrll)r-fornratted composite video signal and a
`fitrrher 1,000 gate logic processor, which imple-
`nierlrs arrtomaric exposure control over a wide
`rarrge. There are also simple solutions for y
`corrediorr arrd tesl.
`
`transistor. The layout of the sensor is custom
`designed to make it as compact as possible.
`At the top (Figure 1) is the 2,000 gate logic pro-
`cessor, laid out using a semi-custom standard-
`cell compiler. Half of these gates generate syn-
`chronization timing,
`including
`line-sync and
`frame-sync signals to format a 6251inel50Hz
`standard composite video output. The other
`half of the gates are included to electronically
`control exposure over a wide range (40,000:1),
`enabling the use of a single fixed-aperture lens.
`The chip measures 7.58n1m x 7.56riinr , using 1.5
`pm, 2 level metal CMOS technology.
`
`1. Introduction
`We introduce a new capability that extends the
`CMOS ASIC marketdace in a sector of high
`
`I
`
`from electronic cameras to 'smart' vision sys-
`tcms.
`C:~rnen~ arid vision systems addressed by today's
`CCD technology appear cumbersome, power-
`hungry and expensive. The experimental work
`reported here demonstrates that high-quality
`image sensors can be implemented entirely in
`commodity ASIC CMOS technology, operating
`from single 5v supplies.
`The reported chip is a highly-integrated CMOS
`VLSI camera, shown in Figure 1. Most of the
`core area is a 312X 287 pixel image sensor array,
`together with the necessary sensing, addressing
`and amplifying circuitry. The output signal can
`be either linear or y corrected. y correction is
`achieved by a simple solution which uses the
`nonlinear l,,-vGS characteristic of an MOS
`
`Figure 1. Photo-micrograph of single chip
`."idea
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`A video camera has been built using this chip
`along with a 6 MHz clock source, a 5 volt
`power supply, plus one bipolar transistor and a
`small number of
`resistors and capacitors
`rcquired to match the line impedance to the
`monitor and decouple the power supply. The
`picture quality is subjectively excellent, and
`compares well with commercially available cam-
`eras.
`
`2. Image Sensor Block
`The architecture of the image sensor is shown in
`Figure 2. The light sensing area consists of a
`312x287 diode array matrix, schematically indi-
`cated by the columns and rows of individual
`photodiodes. The pixel size is 19.6pn1 x 16pti1 ,
`giving a light sensing area of 6.12mnt ~4.59nlnz.
`This corresponds to the standard 112" format.
`
`cal shift register. At the top of each column is -a
`sense amplifier. The sensed information is read
`out sequentially along the x-direction under con-
`trol of a horizontal shift register. At the end of
`the path there is an output amplifier [1,2].
`The sense amplifier is a single-ended differential
`charge integrator. Its performance demands an
`accurate capacitor, formed by metalllmetal2
`and metalllpoly. However, commodity ASIC
`CMOS technology sometimes can not guarantee
`the resulting capacitance values. We designed a
`gain-controllable integrator, shown in Figure. 3,
`which allows wide range of programmable varia-
`tion of the capacitance value.
`
`nain
`
`-1
`
`k s a i n control transistors I
`1 I
`
`-
`
`vref ID
`
`-
`
`self
`compensation
`
`-
`
`Figure 3.
`
`Integrator with programmable gain
`and self compensation
`
`The main concern in the output stage design is
`the read-out speed required to achieve high
`resolution. A 6 MHz clock was chosen for this
`design; this gives a horizontal resolution of 312
`pixels. The resultant picture quality is assured
`by a two stage output buffer with sample and
`hold function.
`
`3. Automatic Exposure Control
`The device automatically controls its exposure
`over a range of 40,000:l. Control is achieved
`by varying the integration time prior to reading
`each row of pixels. The integration time can bc
`as long as one field, or as short as threc cyclcs
`of the pixel clock(about SOOns).
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`CVO -- composite video output
`
`Figure 2. Architecture of the image sensor
`
`'I'he photodiodes are accessed on the basis of
`sequential selection of each row through a verti-
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`The exposure is set by monitoring the video
`stream and estimating the fractions of each pic-
`ture which are very white and very black. On
`the basis of this information, the device decides
`whether the picture contrast is acceptable, or too
`white, or too dark. If necessary, the exposure
`time is then changed, in the appropriate direc-
`tion.
`
`4. Generation of the Video Format Signal
`Figure 4 shows a block diagram for the genera-
`tion of
`the video formatted signal. The y
`corrected image data is multiplexed with the
`sync-level and blanking-level, controlled by tim-
`ing control signals, which are provided from the
`timing block. A bipolar
`transistor
`video
`(emitter follower) is needed to provide a low
`impedance output.
`
`.-
`
`timing
`
`in Figure 5.
`
`Vdd
`
`Corrected
`output
`
`input +(-'
`Linear
`
`Figure 5. Gamma corrector
`
`SPICE simulation was carried out and a simula-
`tion result is shown in Figure 6. A theoretical
`curve of ideal y correction ( y =0.45) is also
`shown in Figure 6.
`
`Sync I
`level
`
`1 Blanking
`level
`
`Figure 4. Generation of the video output
`
`5; Simple Solulion for y Correction
`to be y
`'I'hc analogue
`image data needs
`corrected, to compensate for the nonlinearity of
`monitor tubes 131. This is usually implemented
`using discrete components e.g. a ladder-network
`of diodes,
`resistors and
`reference voltages.
`Unfortunately, this is not suitable for i n n g a -
`tion. In this design y correction is achieved by
`a simple solution which uses the nonlinear ID-
`VGS characteristic of an MOS FET, as shown
`
`Figure 6. Gamma correction curves
`
`6. Simple Solution for Test
`
`Special consideration has bee11 given to make it
`possible to carry o u t digital wafcr test which is
`as complete as possible. The analogue parts arc
`also tested by making them produce digital out-
`puts, so avoiding a requirement for full analo-
`gue test. The test includes bit-line tests and
`word-line tests,, Only a 0.78% increase in chip
`area was required to implement the on chip
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`liaraware necessary for this .form of tteSting (Fig-
`ure 2). The individual photo pixels may be
`tested if a sufficiently long vector set is allow-
`able.
`The chip can also self-generate a checkerboard
`pattern which may be displayed on a monitor
`screen, or captured by a frame grabber. This
`pattern can be used not only to find defective
`pixels, but also to check analogue performance
`parameters, such as read out speed and unifor-
`mity.
`
`7. Eliminating Noise
`Complete guard rings are put around all analo-
`gue parts to minimize interference from the digi-
`tal parts. Routing is arranged with priority to
`analogue output and analogue power supplies.
`Analogue power supplies and digital supplies are
`separated, and supplies to different analogue
`parts are divided where necessary.
`'I'here are two sources of fixed pattern noise:
`tlireshold variation in the MOS pixel access
`transistors causing speckles, and mismatches
`betwecn
`the column sense amplifiers causing
`vertical stripes. The Solution t o the pixel thres-
`hold variation is to reduce the pixel reset voltage
`below (Vdd-Vt) so that the reset voltage is
`insensitive to the variation of the threshold Vt.
`Column fixed pattern noise arises mostly from
`offset mismatches in the coIumn sense amplif-
`iers. We have successfully eliminated this prob-
`lem by automatically compensating each amplif-
`ier to give zero offset during each line synchron-
`ization interval.
`
`8. Characterization
`An ol~tical test measurement set-up was used to
`cliaractcrize the camera. The following table
`summarize the measured results of the perfor-
`mance characterization experiments. The param-
`ctcrs of typical nionochrorne CCD cameras are
`also givcn for comparison.
`
`* as fraction of saturation at room temperature,
`20msec integration time
`
`9. Conclusions
`We have developed several design techniques to
`achieve a single chip camcra. in unmodif'icd
`CMOS
`technology. which matchcs
`the
`performance of CCD cameras. Thc tlesign has
`proven that three technical barriers which most
`greatly
`influence ncw product development;
`cost, power consumption and size, are all
`dramatically reduced over
`today's solid-state
`camera technologies.
`
`10. Acknowledgements
`We acknowledge support received from the
`Science and Engineering Research Council
`(Grant GR/F 36538 IED2/1/1159).
`
`11. References
`[I] D. Renshaw, et, a]., "ASIC Vision", Proc.
`IEEE
`Custom
`Integrated
`Circuits
`Conference! 19!30, pp 3038-3041.
`[Z] D. Renshaw, et. a].,
`Image
`"ASIC
`Sensors",
`Proc.
`IEEE
`International
`Symposium on Circuits and Systems, 1990,
`pp 7.3.1-7.3.4.
`[3] Eugenc Trundlc,
`'I'clevision and Video
`Engineers Pockct Book, Heinemann, 1987.
`
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`

`
`Advancing Technology
`for Humaniiy
`
`DECLARATION OF GERARD P. GRENIER
`
`I, Gerard P. Grenier, do hereby state that:
`
`1. I am c ~ ~ e n t l y Senior Director of Publishing Technologies for the Institute of Electrical
`and Electronics Engineers (IEEE), 445 Hoes Lane, Piscataway, New Jersey.
`
`2. I have been asked to confirm certain dates regarding the following article (the "Article"):
`
`G. Wang, et al., "CMOS Video Cameras," Euro ASIC '91, Paris, France, May 27-3 1,
`1991.
`
`3. A true and correct copy of the Article accompany this declaration as Exhibit A.
`
`4. IEEE is a neutral third party to the dispute in this IPR.
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`available to attendees of the conference. The Article is currently available for public
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`8. I have reviewed the IEEE records relating to the Article.
`
`9. IEEE's records confirm the following:
`
`a) "CMOS" Video Cameras" was presented as part of Euro SIC '91 which occurred May
`27-31, 1991.
`
`b) IEEE has registered this conference with U.S. Copyright Office.
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`I declare under penalty of perjury that the foregoing statements are,,true and correct,-
`
`Executed on:
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`Wang, G. ; Dept. of Electr Eng , Edinburgh Univ., UK ; Renshaw, D. ; Denyer, P.B. ; Lu, M.
`
`Abstract
`
`Authors
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`References
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`Cited By
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`Keywords
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`A single chip CMOS video camera is presented, along with design technique and characterization
`results. The chip comprises a 312*287 pixel photodiode array together with all the necessary sensing,
`addressing and amplifying circuitry, as well as a 1000 gate logic processor, which implements
`synchronization timing to deliver a fully-formatted composite video signal and a further 1000 gate logic
`processor, which implements automatic exposure control over a wide range. There are also simple
`solutions for gamma correction and test.<>
`
`Published in:
`Euro ASIC '91
`
`Date of Conference:
`27-31 May 1991
`
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`Meeting Date :
`27 May 1991-31 May 1991
`
`Print ISBN:
`0-81 86-2185-0
`
`INSPEC Accession Number:
`4367802
`
`Conference Location :
`Paris, France
`
`Digital Object Identifier :
`10.1 109/EUASIC.1991.212885
`
`Publisher:
`IEEE
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