United States Patent [19]
`Grants et al.
`
`[11]
`[45]
`
`4,281,392
`Jul. 28, 1981
`
`[54] MEMORY CIRCUIT FOR PROGRAMMABLE
`MACHINES
`
`[75] Inventors: Valdis Grants, Lyndhurst; Ron
`Schultz, Willoughby; Timothy E.
`McAdams, Willowick, all of Ohio
`[73] Assignee: Allen-Bradley Company, Milwaukee,
`Wis.
`[21] Appl. No.: 35,068
`[22] Filed:
`May 1, 1979
`[51] Int. Cl.3 ...................... .. G06F 13/06; GllC 5/06;
`GllC 7/00; GllC 9/00
`[52] US. Cl. .................................................. .. 364/900
`[58] Field of Search
`364/200 MS File, 900 MS File;
`37l/2l; 324/73 R
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5/ 1977 Kaufman et al. .................. .. 364/200
`4,025,903
`4,055,802 l0/l977
`Panousis et a1.
`371/2!
`Primary Examiner-—Gareth D. Shaw
`Assistant Examiner—C. T. Bartz
`Attorney, Agent, or Firm—Quarles & Brady
`[5?]
`ABSTRACT
`A memory circuit receives memory modules which
`may vary in their size and their type. The memory
`circuit includes a decoder circuit which receives size
`feedback signals from each memory module which
`enables it to automatically assign each module the ad
`dress space it requires. If the size of a memory module
`is changed, the decoder circuit reassigns the address
`space to accommodate the new module. Type feedback
`signals generated by each memory module enable the
`memory circuit to apply the proper control signals and
`enable the proper supporting circuitry when the mem
`ory module is addressed.
`
`3,967,251
`3,969,618
`
`6/1976 Levine ............................... .. 364/200
`9/1976 Strubel et al. ....................... .. 371/21
`
`9 Claims, 4 Drawing Figures
`
`DATA IN
`BU FFERS
`
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`
`DATA OUT
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`MODULE
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`
`7E.
`
`55
`
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`HOlV'l p SSBHOOV
`
`SCEA Ex. 1052 Page 1
`
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`SCEA EX. 1052 Page 2
`
`SCEA Ex. 1052 Page 2
`
`
`
`

`
`U.S. Patent
`
`Jul. 23, 1981
`
`Sheet 2 of3
`
`4,281,392
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`DECODER
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`ADDRESS
`
`SCEA EX. 1052 Page 3
`
`SCEA Ex. 1052 Page 3
`
`
`
`
`
`
`
`
`
`
`

`
`US. Patent Jul. 28, 1981
`
`Sheet 3 of3
`
`4,281,392
`
`SCEA Ex. 1052 Page 4
`
`

`
`1
`
`MEMORY CIRCUIT FOR PROGRAMMABLE
`MACHINES
`
`5
`
`4,281,392
`2
`signal which it generates causes the decoder circuit to
`enlarge the address space gap to the required size.
`Another object of the invention is to provide a mem
`ory circuit into which memory modules of differing
`types can be inserted without alteration of the circuitry.
`when a random access memory module is inserted in
`place of a read-only memory module, the type feedback
`signal which it generates enables parity circuitry. The
`parity circuitry includes a parity generator which
`writes a parity bit into the random access memory dur
`ing write operations and which checks the parity of
`data read from the random access memory. Ths cir
`cuitry is automatically disabled when a read-only mem
`ory is employed.
`Another object of the invention is to enable memory
`modules of differing sizes and types to be intermixed in
`the same memory circuit. The feedback signals gener
`ated by each memory module indicate to the circuitry
`its size and type, and the circuitry automatically allo
`cates the proper amount of address space and enables
`the proper control signals and supporting circuitry
`when the memory module is addressed.
`The foregoing and other objects and advantages of
`the invention will appear from the following descrip
`tion. In the description, reference is made to the accom
`panying drawings which form a part hereof, and in
`which there is shown by way of illustration a preferred
`embodiment of the invention. Such embodiment does
`not necessarily represent the full scope of the invention,
`however, and reference is made therefore to the claims
`herein for interpreting the scope of the invention.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is an electrical block diagram of a programma
`ble controller which employs the memory circuit of the
`present invention;
`FIGS. 2A and 2B are electrical schematic diagrams
`of the memory circuit which incorporates the present
`invention; and
`FIG. 3 is a perspective view with parts cut away of a
`memory module which forms part of the circuit of FIG.
`2A.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`The memory circuit of the present invention is em
`ployed in a programmable controller. Referring to FIG.
`1, this programmable controller is structured around an
`eight-bit bidirectional data bus 1 and includes a control
`ler processor 2 which directs the ?ow of data thereon
`by means of control lines and a sixteen-bit address bus 3.
`A memory circuit 4 connects to both the data bus I and
`the address bus 3 and an eight-bit data word may be
`written into an addressed line or read out of an ad
`dressed line of the memory 4 in response to control
`signals applied to “data strobe" and “WE" control lines
`16 and 28. The memory 4 may include anywhere from
`1K to 16K lines of memory which store working regis
`ters 7, an I/O image table 8, a timers, counters and data
`storage 9 and a control program 10.
`The control program portion 10 of the memory cir
`cuit 4 stores a series or programmable controller type
`instructions such as those de?ned in U.S. Pat. No.
`3,942,158. Each controller instruction is stored on two
`8-bit memory lines and when it is read out through the
`data bus 1 to the controller processor 2, an operation
`code therein directs the processor 2 to perform a desig
`
`BACKGROUND OF THE INVENTION
`The ?eld of the invention is programmed machines
`which store programs and other data in addressable
`memory devices, and particularly, machines in which
`the user can readily add or exchange memory devices of
`various sizes and types.
`In programmable machines such as programmable
`controllers the user employs a program panel to de
`velop a control program which is stored in a memory
`device such as a random access memory (RAM) or a
`read-only memory (ROM). The control program which
`is developed may be very short in some applications
`(less than 1K memory lines) while in other applications
`it may become quite lengthy (16K memory lines or
`more). Also, some portions of the control program may
`be ?xed, and thus suitable for employing read-only
`memory devices, whereas other portions may undergo
`periodic change and be more suitably stored in read/
`write memory devices. It is desirable, therefore, to
`allow the user ?exibility in the size of the memory he
`may use and the type of memory devices he may em
`ploy.
`Nearly all programmed machines have a limited
`amount of address space and most of this space is occu
`pied by memory devices. In both microprocessor-based
`and minicomputer-based machines, for example, a 16-bit
`address bus is employed which provides a 64K address
`space. Although address expansion techniques are well
`known, these require additional hardware and more
`execution time. In providing a flexible system in which
`the user may interchange memory devices of varying
`sizes, therefore, it is important that the available address
`space be efficiently used.
`
`35
`
`SUMMARY OF THE INVENTION
`The present invention is a memory circuit for a pro
`grammable machine in which memory devices in the
`form of memory modules of various sizes and types may
`be used without alteration of the circuit. More speci?
`cally, the memory circuit includes a decoder circuit
`which connects to selected leads in the machine's ad
`dress bus and which connects to size feedback lines that
`connect to the memory modules and which indicate to
`the decoder circuit the size of the memory modules
`being used. The decoder circuit is responsive to signals
`on the machine's address bus to provide signals which
`enable the memory modules in such manner that they
`occupy a contiguous address space regardless of the size
`of the memory devices employed in them. Also, gates
`are provided for receiving signals from each memory
`module on type feedback lines and for enabling the
`proper supporting circuitry for each memory module as
`it is addressed.
`A general object of the invention is to provide a
`memory circuit into which memory modules of differ
`ing sizes can be inserted without alteration of the cir
`cuitry or waste of address space. When a memory mod
`ule is inserted in place of a memory module of larger
`size, the size feed-back signal which it generates alters
`the decoder circuit operation such that the address
`space allocated to other memory modules is shifted to
`close the gap in address space which would otherwise
`occur. On the other hand, if a small memory module is
`replaced by a larger memory module, the size feedback
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`SCEA Ex. 1052 Page 5
`
`

`
`10
`
`20
`
`25
`
`30
`
`35
`
`4,281,392
`3
`4
`through the control program requires approximately
`nated function. The control program is prepared and
`twenty milliseconds (the exact time depends on the
`entered into the memory circuit 4 by the end user and
`the size of the memory circuit 4 will, therefore, depend
`length of the control program and the types of instruc
`upon the length of the user’s control program.
`tions contained therein) and after each such scan, an
`The control program is loaded into the memory cir
`I/O scan routine is executed to couple data between the
`I/O interface racks 20-23 and the I/O image table 8 in
`cuit 4 and edited by means of a program panel 12 which
`couples to the data bus 1 through a universal asynchro
`the memory circuit 4. The U0 image table 8 stores an
`input status data word and an output status data word
`nous receiver/transmitter (UAR/T) 13 and a set of
`bidirectional data gates 14. Data is received from the
`for each I/O card in the interface racks 20-23. Each
`program panel 12 serially through a cable 17 and the
`data word in the [/0 image table 8 is thus associated
`received eight-bit word is gated onto the data bus 1 by
`with a speci?c card in one of the I/O interface racks
`the UAR/T 13 and data gates 14. Such data may in
`20-23. Each input status word is an image of the state of
`eight sensing devices connected to its associated I/O
`clude control program instructions to be stored in the
`memory circuit 10 or edit commands. Data is also gated
`card and each output status word is an image of the
`from the data bus 1 to the UAR/T l3, and this data is
`desired state of any operating devices connected to its
`latched in the UAR/T 13 and serially transmitted to the
`associated I/O card.
`program panel 12. Such output data may include con
`The U0 scan is made after each scan, or execution, of
`trol program instructions stored in the memory circuit
`the control program stored in the memory circuit 4.
`4. Such data is processed by the program panel 12 to
`The U0 scan is a programmed sequence in which out
`display a "rung diagram" that visually indicates to the
`put status words are sequentially coupled from the U0
`image table 8 to their associated [/0 cards and input
`user the functions which are carried out by the control
`status words are sequentially coupled from the I/O
`program.
`The programmable controller is connected to the
`cards to their associated memory locations in the I/O
`machine, or system being controlled, through l/O inter
`image table 8. The V0 scan is performed once every
`face racks 20-23. Each interface rack 20-23 includes an
`control program scan (approximately once every
`l/O adapter card 24 and up to eight eight-bit input or
`twenty milliseconds) and thus the I/O image table 8 is
`output cards (not shown in the drawings) that are re
`kept up to date with changing conditions on the ma
`ceived in four slots 0-3. That is, each slot 0-3 may
`chine or process being controlled.
`include two eight-bit I/O modules, or cards--a low and
`The controller processor 2 operates on data in the
`a high. Each input card contains eight input circuits for
`I/O image table 8 rather than data received directly
`receiving digital signals that indicate the status of sens
`from the I/O interface racks 20-23. This allows the
`ing devices such as limit switches on the machine being
`processor to operate at maximum speed to execute the
`controlled, and each output card contains eight output
`control program in a minimum amount of time while at
`circuits for controlling operating devices on the ma
`the same time minimizing the data rates in the [/0 data
`bus 32 and the I/O address bus 25. The latter consider
`chine such as motor starters and solenoids. Input and
`output circuits illustrated in respective US. Pat. Nos.
`ation is important, since lower data rates allow the use
`3,643,115 and 3,745,546 may be employed for this pur
`of more effective noise immunity circuits which are so
`pose although numerous circuits are available to inter
`necessary in an industrial environment.
`face wih the many types of sensing devices and operat
`Numerous types of controller processors 2 are known
`ing devices which may be encountered in industrial
`to the art. The hardwired processor disclosed in US.
`application.
`Pat. No. 3,942,158 may be employed, the microproces
`sor based processor disclosed in US. Pat. No. 4,118,792
`Data is coupled to or from a particular card in one of
`the U0 interface racks 20-23 by addressing it through
`may be employed, or the micro-programmed processor
`disclosed in copending US. patent application Ser. No.
`a ?ve-bit I/O address bus 25. Two bits select the appro
`priate I/O interface rack 20-23 and the remaining three
`026,012 filed on Apr. 2, 1979 may be employed. Regard
`bits identify the card being addressed. The U0 adapter
`less of the type of processor employed, it will generate
`data on the data bus 1 for storage in the memory circuit
`card 24 on each I/O interface rack 20-23 includes
`10 and it will read data from the memory circuit 10. The
`means for recognizing when its rack is being addressed
`(not shown in the drawings) and it includes a three-bit
`processor 2 also generates an address on the address bus
`decoder (not shown in the drawings) for enabling the
`3 to select a line in the memory circuit 4 from which
`appropriate card. Reference is made to US. Pat. No.
`data is to be read or into which data is to be written and
`it generates the necessary control signals on the control
`4,118,792 entitled “Malfunction Detection System for a
`Microprocessor Based Programmable Controller” for a
`bus 11.
`Referring to FIGS. 2 and 3, the memory circuit of the
`more detailed description of the I/O adapter cards 24.
`Data is coupled between the controller processor 2
`present invention is physically located on a separate
`and the I/O interface racks 20-23 through an eight-bit
`circuit board that is accessible to the user. Four memory
`modules 30-33, each containing memory devices of a
`I/O data bus 32 and a set of eight l/O data gates 33.
`When a read operation is performed, eight bits of data
`?xed size and type may be plugged into the memory
`are gated onto the I/O data bus 32 by the addressed I/O
`circuit 4. Each memory module 30-33 includes an insu
`card and this data is coupled to the data bus 1 by the [/0
`lating case 34 that encloses a circuit board 35 which is
`data gates 33. Conversely, when a write operation is
`received in an edge connector 37 on the main memory
`performed, an eight-bit output data word is coupled
`circuit board 62. The module circuit board 35 will re
`ceive nine one-bit by lK or one-bit by 4K memory chips
`from the controller processor 2, through the I/O data
`mounted in dual-in~line packages 36. Eight of these
`gates 33 and to an addressed output card in one of the
`memory chips store data and the ninth stores a parity
`V0 interface racks 20-23.
`bit, therefore, the ninth memory chip is not required
`The control program stored in the memory circuit 4
`when read-only memory chips are employed. The
`is repeatedly executed, or scanned, by the controller
`memory chip leads are soldered to metal foils on the
`processor 2 when in the ‘*run" mode. Each scan
`
`40
`
`45
`
`50
`
`55
`
`65
`
`SCEA Ex. 1052 Page 6
`
`

`
`20
`
`25
`
`30
`
`35
`
`5
`module circuit board 35 which in turn connects them to
`terminals on the edge connector 37. These connections
`will vary depending upon the size and type of memory
`chips used, however, the terminals on all four edge
`connectors serve the same functions so that modules are
`interchangeble. For a detailed description of the mem
`ory modules 30-33, reference is made to U.S. Pat. No.
`4,138,711, issued on Feb. 6, 1979, and entitled “Static
`Control Device for Printed Circuit Package."
`Referring particularly to FIGS. 2A and 2B, each
`memory module 30-33 is coupled to the 8-bit data bus 1
`through data in buffers 38 and a data out latch 39. The
`eight leads in the data bus 1 connect through the data in
`buffers 38 to corresponding leads in a data in bus 40 and
`the eight leads in the data in bus 40 in turn connect to
`the “data in” terminals on each of the four edge connec
`tors 37. The circuit board 35 within each memory mod
`ule 30-33 makes the connections between these eight
`data in terminals and the data input lead on each of the
`eight memory chips 36. A ninth lead in the bus 40 is
`driven by a parity generator and it connects to the ninth
`memory chip 36 in each memory module 30-33. It
`should be apparent that the physical layout of the main
`memory circuit board 62 need not be changed to ac
`commodate memory chips of various types. Instead,
`regardless of the pin arrangement on the memory chips
`36, the memory module circuit board 35 is constructed
`to make the necessary connections to the data in bus 40.
`The data out latch 39 receives output data read from
`the memory modules 30-33 through a data out bus 41
`which connects to each of the four edge connectors 37.
`Eight leads in the data out bus 41 carry data, and the
`ninth is a parity bit. This data is latched in the data out
`latch 39 when a logic high voltage is applied to a con
`trol lead 42 and the eight data bits are then generated on
`the data bus 1 when a logic low voltage is applied to a
`control line 43. The parity bit is also stored in the data
`out latch 39, but it is generated on a parity line 44.
`The address space occupied by the memory circuit
`can range from 4K to 16K. To address a location, or
`memory line, in this address space, leads ABO-AB13 in
`the address bus 3 are connected to inputs on four 4-bit
`address latches 45-48. An address on the controller
`address bus 3 is stored in these latches 45-48 when a
`logic high voltage is applied to a control line 49. The
`45
`twelve outputs from address latches 45-47 connect
`through a bus 50 to twelve address input terminals 51 on
`each memory module 30-33. The 12-bit address on this
`bus 50 can select one of 4K lines of memory, however,
`when a memory module 30-33 contains only IX of
`50
`memory not all of the bits are used. Instead, the module
`circuit board 35 is designed to only connect the ten least
`signi?cant leads (A0-A9) in the bus 50 to the memory
`chips 36 in that 1K module. It is a principle objective of
`the present invention that in such case the remaining 3K
`55
`of address space (represented by bits A10 and All) is
`not wasted. This is accomplished in part by connecting
`address bus leads A810 and A811 not only to the latch
`47, but also to the address latch 48 along with leads
`AB12 and A813.
`The four outputs on the address latch 48 connect to
`the four most signi?cant address terminals on a 256 by
`4 decoder PROM 52. The signals on address bus leads
`AB10-AB13 are thus applied to the decoder PROM 52
`which operates as a programmable decoder circuit. The
`65
`decoder PROM 52 is “programme " by “memory size
`feedback signals” which appear on lines 53-56 and
`which are applied to its four least signi?cant address
`
`4,281,392
`6
`terminals. The memory size feedback lines 53-56 are
`pulled to a logic high voltage through resistors con
`nected to a positive d.c. supply terminal 57 and they
`connect to size terminals 58-61 on the respective mem
`ory modules 30-33. When 1K memory chips 36 are
`employed in a memory module 30-33, its circuit board
`35 is wired such that the size terminal 58-61 is con
`nected to circuit ground. On the other hand, when 4K
`memory chips 36 are employed in a memory module,
`the size terminal 58-61 is left unconnected and the size
`feedback line 53-56 to which it connects remains at a
`logic high voltage. The logic state of the size feedback
`lines 53-56 thus indicates to the decoder circuit the size
`of each memory module 30-33 which is employed by
`the user.
`When combined with the most signi?cant address bus
`leads AB10-AB13, the memory size feedback signals on
`the lines 53-56 form an 8-bit address which is applied to
`the decoder PROM 52 and which selects one of its 256
`lines. The contents of the selected line is read out at a set
`of four decoder PROM output terminals 65. A set of
`four NAND gates 66-69 connect to the decoder PROM
`output terminals 65 and each of these in turn drives a
`chip select (CS) and strobe (STR) terminal on one of the
`respective memory modules 30-33. Second inputs on
`the NAND gates 66-69 are commonly connected to a
`STROBE control line 70 which is driven to a logic high
`voltage after an address is clocked into the address
`latches 45-48.
`The decoder PROM 52 is programmed to generate a
`logic high voltage at one of the output terminals 65
`when it is addressed. As a result, one of the four mem
`ory modules 30-33 is enabled through its chip select
`(CS) and strobe (STR) terminals when an address
`within the 16K address range of the memory circuit
`appears on the address bus 3. The particular memory
`module enabled is determined by address bus leads
`ABl0-AB13 and the state of the size feedback lines
`53-56.
`The size feedback signals insure that the entire mem
`ory space is efficiently used even though 1K and 4K
`memory modules are intermixed.
`Referring particularly to FIG. 2A and Table l, the
`16K address space is divided into 1K segments by the
`address bus signals AB10-AB13 which are applied to
`the four most signi?cant address input terminals on the
`decoder PROM 52. For each 1K segment of address
`space there is an associated set of sixteen lines in the
`decoder PROM 52 and one of these sixteen lines is
`selected by the four-bit memory size feedback signal
`which is applied to the four least sign?cant address
`input terminals on the decoder PROM 52. As a result,
`the memory modules 30-33 occupy a contiguous ad
`dress space which may vary in size from 4K (i.e., four
`1K memory modules) to 16K (i.e., four 4K memory
`modules).
`
`40
`
`60
`
`TABLE I
`
`DECODER
`PROM
`ADDRESS
`(HEXA
`DECIMAL)
`00
`10
`20
`30
`40
`50
`so
`
`CONTENTS
`01010101010101010101010101010101
`020102 0102 01 02 01 0201 02 0102 0102 01
`040lO20l040l020l04-0l020l040l020l
`08010201040102010801020104010201
`000202020402020201102020204020202
`00040402m04040201104040204040402
`0008080208[1404020808080208040402
`
`SCEA Ex. 1052 Page 7
`
`

`
`7
`TABLE I-continued
`
`CONTENTS
`00000002000404020008080208040402
`00000004000404040008030408040404
`00000008000808040008080808080804
`00000000000000040000000800080804
`00000000000000040000000800080804
`00000000000000080000000800080808
`00000000000000000000000000000008
`00000000000000000000000000000008
`00000000000000000000000000000008
`
`DECODER
`PROM
`ADDRESS
`(HEXA
`DECIMAL)
`70
`so
`9o
`A0
`B0
`C0
`DO
`ED
`F0
`
`WHERE:
`OI enables memory module 30
`O2 enables memory module ll
`()4 enables memory module 32
`()8 enables memory module 33
`
`25
`
`35
`
`4,281,392
`8
`signals are employed to select the appropriate control
`signals for each memory module 30-33.
`Referring particularly to FIGS. 2A and 2B, the type
`feedback lines 72-75 are applied to the respective input
`terminals on a set of AND gates 89-92. Second inputs
`on the AND gates 89-92 connect through lines 65' to
`corresponding outputs on the decoder PROM 52 and
`when a ‘memory module containing RAM chips is en
`abled, one of the AND gates 89-92 is enabled. As a
`result, a logic low voltage is generated by a NOR gate
`93 and applied to one input of an AND gate 95. The
`output of the AND gate 95 is connected to the D input
`of a flip-?op 94 and a second input is connected to an
`“ODD” output on a parity generator 98. The ?ip-?op
`94 is clocked by a signal on a parity strobe control line
`96.
`The parity generator 98 is a commercially available
`integrated circuit which has a set of eight data input
`terminals connected to the eight leads in the data in bus
`40. An inverter gate 99 connects to the "EVEN" output
`100 on the parity generator 98 and the output of this
`inverter gate 99 drives the parity bit lead in the data in
`bus 40. The parity line 44 from the data out latch 39 is
`coupled to a parity bit input 101 on the parity generator
`98 by a NAND gate 102. The parity bit on the line 44 is
`applied to the parity generator 98 at the same moment
`an 8-bit byte of data is read out of the data out latch 39
`onto the data bus 1.
`When data is written into a RAM memory module
`30-33, a parity bit is generated by the parity generator
`at its output 100 and stored with the data. When data is
`read from a RAM memory module 30-33, the parity bit
`stored with that data is applied to the input 101 on the
`parity generator 98. If an error has occurred, the flip
`flop 94 is clocked and its Q output goes low to clock a
`second ?ip-?op 103. A 6 output on the second ?ip-?op
`103 drives a light emitting diode 104 to provide a visual
`indication that a parity error has occurred and a Q
`output on the flip-?op 103 is coupled through an in
`verter gate 105 to a parity error control line 106. The
`line 106 connects to the processor 2 and the parity error
`signaled thereon generates an interrupt or otherwise
`halts normal operation of the programmable controller.
`The type feedback signals on the lines 72-75 serve to
`enable the supporting circuitry required by random
`access memory modules. When a read-only memory
`module is inserted by the user however, this supporting
`circuitry is disabled because it would provide incorrect
`indications. This enabling and disabling of the parity
`generator circuit occurs automatically and it enables
`RAM and ROM memory modules to be intermixed.
`It should be apparent that the memory circuit of the
`present invention offers a great convenience to the user
`by enabling him to insert memory modules 30-33 of
`varying sizes and types. The circuit automatically ac
`commodates the memory modules and insures that
`available address space is efficiently used. It should also
`be apparent that although the present invention is par
`ticularly suited for programmable controllers, that it is
`also useful in other digital systems where memory mod
`ules of varying sizes and types are used.
`We claim:
`1. A memory circuit which comprises:
`a set of memory modules, each module having ad
`dress terminals for receiving a multi-bit address
`code, each module having a data terminal, each
`module having an enable terminal for receiving an
`
`40
`
`It should be apparent that although the memory cir
`cuit of the preferred embodiment occupies up to 16K of
`address space and accepts only 1K or 4K memory sizes,
`that the invention may be applied with equal advantage
`to other con?gurations. For example, the entire 64K
`address space provided by the l6-lead address bus 3
`may be managed by the circuit of the present invention
`and other sizes of memory modules can be employed. In
`either case, the size of the decoder PROM 52 would be
`expanded to accommodate additional memory modules
`and more address leads in the address bus 3. Also,
`where more than two sizes of memory modules are
`employed, additional size feedback lines would be re
`quired from each module to couple the additional infor
`mation to the decoder PROM 52.
`Referring to FIGS. 2A and 28, either read-only
`memory chips or static random access memory chips
`(RAM) can be employed in the memory modules 30-33.
`This presents two problems which are solved by a set of
`“type feedback lines” 72-75 that eminate from the re
`spective memory modules 30-33. More speci?cally,
`when a RAM chip is employed a write enable input
`terminal (WE) on each memory module 30-33 must be
`driven and a parity bit must be generated when data is
`written into a RAM chip or checked when data is read
`from a RAM chip. In addition, the timing of the write
`enable control signal differs when a 4K RAM chip is
`employed rather than a lK RAM chip.
`Referring particularly to FIG. 2A, the WE control
`terminals on the memory modules 30-33 are commonly
`connected to the output of a NOR gate. One input on
`the NOR gate 77 is driven by a first AND gate 78 that
`receives a write enable signal on a 1K WE control line
`79. The second input on the NOR gate 77 is driven by
`a second AND gate 80 that receives a write enable
`signal on a 4K WE control line 81. Both AND gates 78
`and 80 are driven by a NOR gate 82 which indicates at
`any moment in time whether a 1K or 4K memory mod
`ule is being addressed. This indication is provided by a
`set of four AND gates 83-86, each of which has one
`input connected to a size feedback line 58-61 and a
`second input connected to a decoder PROM output
`terminal 65. Consequently, when a 1K memory module
`is enabled by the decoder PROM 52 the AND gate 78
`is also enabled and the write enable signal on the lK
`WE control line 79 is applied to that memory module.
`On the other hand, when a 4K memory module is ad
`dressed and enabled, the AND gate 80 is enabled and
`the write enable signal on the 4K WE control line 81 is
`applied to that memory module. Thus, the size feedback
`
`45
`
`60
`
`65
`
`SCEA Ex. 1052 Page 8
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`

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`enable signal which enables the module to respond
`to the multi-bit address code and couple data
`through the data terminal, and each module having
`means for generating a size feedback signal which
`is indicative of the number of separate, contiguous
`addresses required by the memory module; and
`a decoder circuit having a ?rst input connected to
`receive at least one bit of the multi-bit address code
`applied to said memory modules and a set of sec
`ond inputs each of which second inputs is con
`nected to receive the size feedback signal from a
`respective one of said memory modules, and in
`which said decoder circuit includes a set of output
`terminals, each of which is connected to a respec
`tive one of said memory module enable terminals;
`wherein said decoder circuit is operable in response
`to an applied address code and the size feedback
`signals generated by said memory modules to gen
`erate an enable signal at selected ones of its output
`terminals and to thereby enable each memory mod
`ule when an address is applied to the memory mod
`ule which lies within its allocated address space.
`2. The memory circuit as recited in claim 1 in which
`said decoder circuit includes a programmable read-only
`memory having address terminals connected to receive
`said size feedback signals and output terminals at which
`said enabling signals are generated.
`3. The memory circuit as recited in claim 1 in which
`the memory modules each contain a write enable termi
`nal and in which gate means connect to receive a plural
`ity of separate write enable control signals, and said gate
`means is connected to said decoder circuit output termi
`nals and is responsive to the enabling signals thereon to
`select one of said write enable control signals and cou
`ple it to said memory module write enable terminals.
`4. A memory circuit for a programmable machine
`which comprises:
`a set of memory module connector means;
`an address bus containing m leads, each of which
`connects with each of said memory module con
`nector means in said set, and n leads which do not;
`a decoder circuit for selectively enabling memory
`modules, which memory modules are each at
`tached to a respective one of the memory module
`connector means in said set of memory module
`connector means, said decoder circuit including:
`a. ?rst input terminals for receiving address signals o