Unlted States Patent ' [19]
`Clayton
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,656,605
`Apr. 7, 1987
`
`[54] SINGLE IN-LINE MEMORY MODULE
`[75] Inventor:
`JNmFIeS E‘ Clayton’ Londonderry’
`'
`'
`[73] Assigneer Wang Laboratories, 1119., Lowell,
`MASS-
`[21] Appl. N0.: 873,879
`_
`[22] Flledl
`J1111- 12, 1936
`
`[63]
`
`Related U-S- Application Data
`Continuation of Ser. No. 528,817, Sep. 2, 1983, aban-
`doned'
`[51] Int. Cl.4 ............................................ .. G11C 13/00
`[52] U.S. Cl. .................................... .. 365/52; 365/189;
`357/72
`[58] Field of Search ............... .. 365/52, 189, 200, 202;
`357/72, 75
`
`[56]
`
`_
`References cued
`U.S. PATENT DOCUMENTS
`3,599,146 8/1971 Weisbecker ....................... .. 365/200
`3,972,033 7/1976 Cislaghi et al. .
`365/200
`
`FOREIGN PATENT DOCUMENTS
`
`1439333 6/1976 United Kingdom .
`1557684 12/1979 United Kingdom .
`
`OTHER PUBLICATIONS
`Lowe, L., “Module Fills Board with 8 Times the Mem
`ory”, Electronics, Jul. 14, 1983, pp. 50-52.
`Electronic Designs Inc., “EDH—4256—15/20 262,
`144><l Bit Dynamic Random Access Memory”, Data
`Sheet’ APg- 198,1-
`_
`Electromc Designs Inc., “EDH 4816 16,384X8 B1t
`Dynamic Random Access Memory”, Data Sheet, Nov.
`1981.
`Electronic Designs Inc., “EDH 8808 8,192X 8 Bit Static
`Random Access Memory”, Data Sheet, 1932
`Primary Examiner-Terrell W. Fears
`Attorney, Agent, or Firm-Michael H. Shanahan;
`Kenneth L- Milik
`
`ABSIRACI
`[57]
`What is disclosed is a memory module to and from
`which multibit binary words are stored and read out.
`Each multibit binary word comprises a standard word
`size and another memory bit that may be used for .pur
`P°ses such as Parity checking The mdules may be
`mounted on a printed circuit mother board from which
`power, control signals and binary words are applied to
`and taken from the module.
`
`1 Claim, 2 Drawing Figures
`
`U23
`
`U34 U35
`
`U96 U37 U98 U39
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`SCEA Ex. 1051 Page 1
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`U. S. Patent Apr. 7, 1987
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`Sheet 1 of 2
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`4,656,605
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`SCEA EX. 1051 Page 2
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`SCEA Ex. 1051 Page 2
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`U. s. Patent Apr. 7, 1987
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`Sheet2 of2
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`4,656,605
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`SCEA Ex. 1051 Page 3
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`

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`1
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`SINGLE IN-LINE MEMORY MODULE
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`4,656,605
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`2
`word to be store in or read out of memory chips 10-17
`for each read or write operation.
`In accordance with the preferred embodiment of my
`invention I provide an extra memory chip 18 similarly
`connected in parallel with memory chips 10-17, the
`read/write control leads of which are interconnected
`with the control leads 29 connected to memory chips
`10-17 with the exception of the column address select
`lead 31. Memory chip 18 has a data input lead 28 and a
`separate data output lead 32 as distinguished from mem
`ory chips 10-17 which respectively use common input
`/ output data leads 20-27 for both data input and output.
`A total of ten input/ output data leads 20-28 and 32 are
`therefore provided on the edge of the memory module
`30 as shown and eight bit binary words plus and extra
`ninth bit for functions such as parity checking are stored
`in or read out of the memory module 30. A separate
`column address select lead 31 is provided for memory
`chip 18 to enable independent operation for the parity
`function.
`When it is desired to store a binary word made up of
`an eight bit byte/ word with a ninth parity bit in a spe
`ci?c address location in memory chips 10-17 and 18, the
`binary bits are applied to terminals on the edge of mem
`ory module 30 which are connected to common input
`/output leads 20-27 and to input lead 28. Each of the
`nine binary bits is thereby applied to the input respec
`tively of memory chips 10-18. A signal is then applied
`to control lead 29 at a terminal on the edge of memory
`module 30, which control lead 29 is connected to the
`read/write control input of chips 10-18. Finally, a mul
`tibit binary address is applied to the multiple address
`leads 19 also on the edge of memory module 30, which
`addressing leads are connected to the addressing inputs
`of each of memory chips 10-18. In response to all the
`above signals applied to the appropriate terminals of
`memory module 30, the binary word on input/output
`leads 20-27 and the extra binary bit on input lead 28 are
`stored respectively in memory chips 10-17 and 18 at the
`address indicated by the binary number on address leads
`19.
`Similarly, when it is desired to read a binary word out
`of memory module 30, a read signal is applied to read/
`write control lead 29 and a binary address is applied to
`address leads 19. In response thereto, the binary word
`stored in memory module 30 at the indicated address is
`read out of memory chips 10-17 and 18 respectively
`onto input/output leads 20-27 and output lead 32.
`Referring to FIG. 2, there is shown a physical layout
`of my memory module 30. The nine memory chips
`10-18 are mounted on a substrate 31 that may be a
`printed circuit board (glass-epoxy) or ceramic. The
`memory chips 10-18 may be dynamic RAMs (D-RAM)
`advantageously packaged in small plastic leaded chip
`carriers available from Texas Instruments and soon
`from other companies such as National Semiconductor,
`Motorola, and AMD. Also mounted on the substrate of
`module 30 are small ceramic decoupling capacitors
`33-40, having a value bewteen 0.1 and 0.22 ufd, and
`connected between each of memory chips 10-18 to
`suppress transient voltage spikes. By using the small
`D-RAMs and small capacitors, module 30 may have
`physical dimensions in the order of three-quarter inch
`by three inches while providing large memory capacity.
`Sixty-four thousand words on the module are presently
`possible and two hundred ?fty-six thousand bytes are
`feasible with the physical dimensions of module 30 only
`being slightly larger.
`
`5
`
`10
`
`The present application is a continuation of U.S. pa
`tent application Ser. No. 528,817 ?led Sept. 2, 1983 by
`James E. Clayton for a SINGLE IN-LINE MEMORY
`MODULE, subsequently abandoned.
`BACKGROUND OF THE INVENTION
`This invention relates to memories and more particu
`larly to modular memories providing storage and re
`trieval of binary words.
`What is disclosed is a memory module to and from
`which multibit binary words are stored and read out.
`Each multibit binary word comprises a standard byte
`size and one or more other memory bits that may be
`used for purposes such as parity checking. The modules
`may be mounted on a printed circuit mother board from
`which power, control signals and binary words are
`applied to and taken from the module.
`
`20
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`25
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`SUMMARY OF THE INVENTION
`The present invention is a memory module on which
`a plurality of memory components each storing or read
`ing one binary bit at a time have their power, control,
`input/output and other access leads interconnected so
`there is only one set of these leads available at terminals
`of the module. A ?rst plurality of these memories pro
`vide for one binary word being input or output to the
`memory module at a time. In addition, I add another
`individual memory intended for purposes such as parity
`checking and error correction. This additional memory
`has its power and control leads interconnected with the
`other memories within the module, but has separate
`input/output lead(s) and column address select leads to
`enable independent accessing or addressing of the par
`ity memory.
`
`DESCRIPTION OF THE DRAWING
`My invention will be understood on reading the fol
`lowing detailed description in conjunction with the
`drawing in which:
`-
`FIG. 1 is an electrical block diagram of my novel
`memory module; and
`45
`FIG. 2 is a mechanical layout drawing of the memory
`module.
`
`DETAILED DESCRIPTION
`In FIG. 1 is seen the electrical block diagram of my
`50
`invention. In one embodiment of my invention, the
`embodiment shown in FIG. 1, eight individual memory
`chips 10-17, each capable of storing a zero or a one
`binary bit at each memory location, are accessed by a
`multi-bit address applied to address leads 19 which
`55
`comprises eight leads. With this embodiment of my
`invention, single input/output leads 20-27 are provided
`respectively to each of memory chips 10-17 to provide
`a total of eight input/output leads making up an eight
`bit binary word. Control lead 29 connected to one input
`of each of memory chips 10-17 on the module 30 indi
`cates whether a read or write operation is being per
`formed at the location identi?ed by the address present
`on the eight address leads 19 which are interconnected
`to the addressing inputs of each of chips 10-17.
`In a manner well known in the art the concurrent
`addressing and control of chips 10-17 which are con
`nected in parallel permits an eight bit byte or binary
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`SCEA Ex. 1051 Page 4
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`4,656,605
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`3
`a data input and output, a control input and an
`With my invention the input, output and control of
`address input interconnected with those of the
`the memory elements 10-18 on module 30 may be ac
`eight memory chips, and a control input to provide
`complished via only thirty terminals on the edge of the
`writing in or reading out of the ninth memory chip
`module. Use of module 30 in lieu of memory chips in
`at times other than when said bytes of digital infor
`conventional dual in line terminal packages normally
`mation are written into or read out of the eight data
`mounted in rows and columns on a printed circuit board
`memory chips to thereby facilitate said error detec
`enables an eight-fold density increase over previous
`tion and correction operation;
`circuit assembly technology,
`an epoxy-glass printed circuit board substrate having
`In addition, by having an extra memory chip parity
`a length and width adequate for mounting thereon
`may be checked. By having separate control of the extra
`only in a single row said nine memory chips and for
`memory chip a system designer has more ?exibility in
`designing parity operation.
`interconnecting the control inputs and the address
`inputs of the memory chips so that bytes of digital
`While what has been described hereinabove is the
`information may be input to or output from the
`preferred embodiment of my invention, it will be obvi
`memory chips one at a time;
`ous to those skilled in the art that numerous changes
`the substrate including thirty terminals for providing
`may be made without departing from the spirit or scope
`access to the data inputs and outputs, control in
`of the invention. More than one bit may be used for
`puts, and-address inputs of the nine memory chips
`parity checking or other purposes. In addition, rather
`to enable reading and writing of bytes of digital
`than using discrete memory chips, the unpackaged dies
`information into and out of the eight memory chips
`may be mounted on a substrate to implement my inven
`and to enable reading and writing of error detec
`tion in a hybrid integrated circuit package or in a large
`tion and correction information into and out of the
`scale integrated circuit package.
`eight memory chips;
`I claim:
`support means for supporting the memory module at
`1. A memory module for installation on a printed
`an angle with respect to the printed circuit mother
`circuit motherboard comprising:
`board when the memory module is installed
`eight data memory chips for storing digital data, each
`thereon; and
`having a data input and output, a control input, and
`eight decoupling capacitors, mounted on said sub
`an address input, and each being packaged in a
`plastic leaded chip carrier;
`strate and connected between the nine memory
`chips, for supressing transient voltage spikes be
`a ninth memory chip for storing error detection and
`tween said memory chips.
`correction information associated with the eight
`data memory chips, said ninth memory chip having
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