`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`In re Patent of: Morton et al.
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`U.S. Patent No.: 7,296,121
`Issue Date:
`Nov. 13, 2007
`Appl. Serial No.: 10/966,161
`Filing Date: Oct. 15, 2004
`Title: REDUCING PROBE TRAFFIC IN MULTIPROCESSOR SYSTEMS
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`Case Nos.: IPR2015-00159
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`IPR2015-00161
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`IPR2015-00163
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`IPR2015-00172
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`DECLARATION OF DR. ROBERT HORST
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`1. My name is Dr. Robert Horst. I am the Chief Technology Officer,
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`Robotics of AlterG, and I am an independent consultant at HT Consulting. I have
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`been asked to offer technical opinions relating to U.S. Patent No. 7,296,121, and
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`prior art references relating to its subject matter. My current curriculum vitae is
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`attached and some highlights follow.
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`2.
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`I earned my M.S. (1978) in electrical engineering and PhD (1991) in
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`computer science from the University of Illinois at Urbana-Champaign after
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`earning my B.S. (1975) in electrical engineering from Bradley University. During
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`my master’s program, I designed, constructed and debugged a shared memory
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`parallel microprocessor system. During my doctoral program, I designed and
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`simulated a massively parallel, multi-threaded task flow computer.
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`3.
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`After receiving my bachelor’s degree and while pursuing my master’s
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`degree, I worked for Hewlett-Packard Co. While at Hewlett-Packard, I designed
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`the micro-sequencer and cache of the HP3000 Series 64 processor. From 1980 to
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`1999, I worked at Tandem Computers which was acquired by Compaq Computers
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`in 1997. While at Tandem, I was the designer and architect of several generations
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`of fault-tolerant computer systems and was the principle architect of the NonStop
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`Cyclone superscalar processor. Since leaving Compaq in 1999, I have worked
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`with several technology companies, including 3Ware and Network Appliance, and
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`have focused in the areas of computer design and biomedical devices.
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`4.
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`At HP, Tandem, Compaq, 3Ware and Network Appliance my
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`computer design work was done using computer aided design (CAD) tools, with
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`most designs specified in a hardware description language. In fact, the designs
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`used integrated circuits and some involved the creation of new ASICs (application
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`specific integrated circuits) that were manufactured using masks based on the
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`netlists produced by the CAD software.
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`5.
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`I have authored over 30 publications, including: “The Risk of Data
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`Corruption in Microprocessor-based Systems,” Proc. 23rd International
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`Symposium on Fault-tolerant Computing, June 1993; and “Reliable Design of
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`High-speed Cache and Control Store Memories,” Proc. 19th Int. Symp. Fault-
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`Tolerant Computing, June 1989. In 1998, the University of Illinois department of
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`Electrical and Computer Engineering awarded me the Distinguished Alumni
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`Award for “Pioneering Contributions to Fault-tolerant Computer Architecture.”
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`And, in 2001, I was named IEEE Fellow “for contributions to the architecture and
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`design of fault tolerant systems and networks.”
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`6.
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`I am a named inventor on 78 issued U.S. patents. These patents
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`include U.S, Patent No. 5,751,932, entitled “Fail-fast, fail-functional, fault-tolerant
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`multiprocessor system” and U.S. Patent No. 5,390,355, entitled “Computer
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`architecture capable of concurrent issuance and execution of general purpose
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`multiple instructions.”
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`7.
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`I am familiar with the content of U.S. Patent No. 7,296,121 (the “‘121
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`patent”). Additionally, I have reviewed the following: U.S. Patent Application
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`Publication Number 2002/0053004 to Pong (“Pong”); David Chaiken et al.,
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`“Directory-Based Cache Coherence in Large-Scale Multiprocessors,” Computer
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`vol. 24, issue 9 (Jun 1990) (“Chaiken”); Daniel Lenoski et al., “The Directory-
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`Based Cache Coherence Protocol for the DASH Multiprocessor,” ISCA ‘90
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`Proceedings of the 17th annual international symposium on Computer
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`Architecture, pp. 149-159 (May 1990) (“Stanford DASH”); U.S. Patent Number
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`6,490,661 to Keller et al (“Keller”); Jose Duato et al., INTERCONNECTION
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`NETWORKS – AN ENGINEERING APPROACH (1997) (“Duato”); Michael John
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`Sebastian Smith, APPLICATION-SPECIFIC INTEGRATED CIRCUITS (1997) (“Smith”);
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`U.S. Patent No. 7,698,509 to Koster et al. (“Koster”); U.S. Patent No. 7,315,919 to
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`O’Krafka et al. (“O’Krafka”); U.S. Patent No. 6,338,122 to Baumgartner et al.
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`(“Baumgartner”); Anant Agarwal et al., “An Evaluation of Directory Schemes for
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`Cache Coherence,” Conference Proceedings of 15th Annual International
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`Symposium on Computer Architecture (1988); Louis G. Johnson,
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`“Multiprocessors,” ECEN 6253 Lecture Notes (April 28, 2003); Luca Benini and
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`Giovanni De Micheli, “Networks on chips: a new SoC paradigm,” Computer vol.
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`35, issue 1 (Jan. 2002) (“Benini”); “HyperTransport™ Technology I/O Link - A
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`High-Bandwidth I/O Architecture” (Jul. 20, 2001) (“HyperTransport”); U.S.
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`Publication No. 2005/0228952 to Mayhew et al. (“Mayhew”); and U.S. Patent No.
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`6,662,277 to Gaither (“Gaither”). I have also reviewed the two Notices of
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`Allowances included in the prosecution history of the ‘121 patent.
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`8.
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`Counsel has informed me that I should consider these materials
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`through the lens of one of ordinary skill in the art related to the ‘121 patent at the
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`time of the earliest purported priority date of the ‘121 patent, and I have done so
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`during my review of these materials. I believe one of ordinary skill as of
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`November 4, 2002 (the priority date of U.S. Patent No. 7,003,633, to which the
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`‘121 patent claims continuation-in-part priority) would have a bachelor’s degree in
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`electrical engineering, computer engineering, or computer science and at least two
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`years of experience in the design of multiprocessor systems. I base this on my own
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`personal experience, including my knowledge of colleagues and others at the time.
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`I have no financial interest in either party or in the outcome of this
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`9.
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`proceeding. I am being compensated for my work as an expert on an hourly basis.
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`My compensation is not dependent on the outcome of these proceedings or the
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`content of my opinions.
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`10. My opinions, as explained below, are based on my education,
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`experience, and background in the fields discussed above.
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`11. This declaration is organized as follows:
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`I.
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`II.
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`Brief Overview of Relevant Technology (page 5)
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`Brief Overview of the ‘121 Patent (page 8)
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`III. Terminology (page 11)
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`IV. Legal Standards for Prior Art (page 19)
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`V.
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`Pong and Combinations Based on Pong (page 25)
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`VI. Chaiken and Combinations Based on Chaiken (page 51)
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`VII. Stanford DASH and Combinations Based on Stanford DASH
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`(page 67)
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`VIII. Koster and Combinations Based on Koster (page 104)
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`IX. Conclusion (page 123)
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`I.
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`Brief Overview of Relevant Technology
`12. A shared-memory multiprocessor is a computer system in which
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`multiple processors share memory. Memory (and I/O devices) are shared by each
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`of the processors via a bus or interconnection network. Ex. 1013, p. 1. “Each
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`processor has access to its own memory and all the memory of all the other
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`processors.” Id. “Memory becomes a common resource which must be shared
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`between execution threads running simultaneously (really simultaneously, not time
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`shared) on different processors in the multiprocessor system.” Id.
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`13. One way to increase the speed of a multiprocessor is to associate a
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`cache memory with each processor. See, e.g., Ex. 1020, 1:11-42, 3:47 to 4:2.
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`Cache memories are significantly faster than standard main memory because main
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`memory is generally implemented with external DRAM (dynamic random access
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`memory), while caches are generally implemented with internal or external static
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`RAM which is much faster, but also have significantly smaller capacity than main
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`memory implemented with DRAM. See id. Each processor may have a cache
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`memory to store a copy of only a portion of the data stored in main memory (e.g.,
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`the portion most recently or most commonly accessed by the processor). See id.
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`Moreover, because threads executed simultaneously across the processors within
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`the multiprocessor share memory, more than one processor may store a copy of a
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`particular memory location in its cache. See id.
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`14. Each of these simultaneously executed threads has the ability to cause
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`its processor to both read the data stored in cache and write modified data back into
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`its cache. This leads to the possibility for inconsistencies between the copies of the
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`data stored in the cache memories. For example, in the case where multiple
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`processors store a copy of a memory location in their caches and one of them
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`updates the copy stored in its cache, two or more caches could have inconsistent
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`copies of the data, resulting in cache incoherency. The updated copy of the
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`memory location stored in the updating processor’s cache is known as a “dirty”
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`copy of the memory location, because it differs from what is in main memory. See
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`Ex. 1012, p. 280. The other processors that are storing copies of the updated
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`memory location must be notified in some manner of the existence of a dirty copy,
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`and thus of an update, to prevent the other processors from operating with/on stale
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`data.
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`15. A number of schemes have been proposed for maintaining coherency
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`between the caches within a shared-memory multiprocessor. As described by
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`Anant Agarwal et al. in “An Evaluation of Directory Schemes for Cache
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`Coherence” (Ex. 1012):
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`A cache coherency protocol is the mechanism by which the coherency
`of the caches is maintained. Maintaining coherency entails taking
`special action when one processor writes to a block of data that exists
`in other caches. The data in the other caches, which is now stale, must
`be either invalidated or updated with the new value, depending on the
`protocol. Similarly, if a read miss occurs on a shared data item and
`memory has not been updated with the most recent value (as would
`happen in a copy-back cache), that most recent value must be found
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`and supplied to the cache that missed. These two actions are the
`essence of all cache coherency protocols. The protocols differ
`primarily in how they determine whether the block is shared, how
`they find out where block copies reside, and how they invalidate or
`update copies.
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`Id.
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`16. Two classes of these cache coherency protocols are “snoopy-based”
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`and “directory-based.” See id. In snoopy-based protocols, “each cache in the
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`system must watch all coherency transactions to determine when consistency-
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`related actions should take place for shared data.” See id. On the other hand,
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`directory-based protocols “keep a separate directory associated with main memory
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`that stores the state of each block of main memory.” See id. This directory is
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`referenced and, if necessary, updated to account for coherency transactions that
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`occur and to trigger corresponding consistency-related actions for shared data.
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`Some systems combine aspects of from each of these protocols, so there isn’t a
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`bight-line boundary between them.
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`II.
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`Brief Overview of the ‘121 Patent
`17. The ‘121 patent is directed to “techniques for improving data access
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`and cache coherency in systems having multiple processors connected using point-
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`to-point links.” Ex. 1001, 2:39-42. According to the ‘121 patent, “cache
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`coherency problems arise because multiple copies of the same data can co-exist in
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`systems having multiple processors and multiple cache memories.” Id. at 1:35-38.
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`“For example, a frequently accessed data block corresponding to a memory line
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`may be loaded into the cache of two different processors.” Id. at 1:38-40. In such
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`an example, “if both processors attempt to write new values into the data block at
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`the same time, different data values may result.” Id. at 1:40-42. A cache
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`coherency mechanism attempts to “address such problems in multiprocessor
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`systems.” Id. at 1:46-48.
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`18. Within the broader paradigm of cache coherence protocols, the ‘121
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`patent specifically focuses on “reducing probe traffic in multiprocessor systems.”
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`Ex. 1001, title. “Any mechanism for filtering or reducing the number of probes
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`and requests transmitted to various nodes is referred to herein as managing
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`probes.” Id. at 5:50-52. According to the ‘121 patent, managing probes may
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`entail, for example, “characterizing a request to determine if a probe can be
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`transmitted to a reduced number of entities.” Id. at 5:52-55. FIG. 18 (reproduced
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`below) illustrates one implementation of a system that manages probes with a
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`“probe filtering unit” (PFU).
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`19.
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`“System 1800 includes processing nodes 1802a-1802d, one or more
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`Basic I/O systems (BIOS) 1804, a memory subsystem comprising memory banks
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`1806a-1806d, and point-to-point communication links 1808a-1808e.” Id. at 26:64
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`to 27:1. The ‘121 patent describes the operation of the probe filtering unit with
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`regard to FIG. 20. In particular, the process begins when a processing node sends
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`a read request for a memory line to the probe filtering unit. Id. at 28:25-29. “The
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`PFU accepts the probe and looks up the address [of the memory line] in its
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`directory of shared cache states (2008).” Id. at 28:29-31.
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`20. When “the directory lookup determines the cache line may be cached
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`in the system (2010), the PFU sends out a probe only on links corresponding to the
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`nodes that may contain the cache line.” Id. at 28:50-53. This contrasts with
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`“typical implementations” in which a processing node “broadcasts probes to
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`various nodes in a system” without “knowledge of the cache line state.” Id. at
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`5:56-59.
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`III. Terminology
`21.
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`I have been informed that claim terminology must be given the
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`broadest reasonable interpretation during an IPR proceeding. I have been informed
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`that this means the claims should be interpreted as broadly as their terms
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`reasonably allow, but that such interpretation should not be inconsistent with the
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`patent’s specification and with usage of the terms by one of ordinary skill in the
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`art. Counsel has also informed me that this may yield interpretations that are
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`broader than the interpretation applied during a District Court proceeding, such as
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`the pending Memory Integrity, LLC v. Apple, Inc. litigation.
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`22.
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`I have been informed that it would be useful to provide some guidance
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`in this proceeding with respect to certain terms, and have been asked to consider
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`the terms below and corresponding constructions. As part of that, for each term
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`addressed below, I considered each term’s context within the claim, each term’s
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`use within the specification, and my understanding of how one of ordinary skill in
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`the art would understand the term around the time of the purported invention.
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`I have considered whether a broadest reasonable interpretation of
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`23.
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`“processing node” would be broad enough to cover “an interconnectable computer
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`subsystem comprising at least one processor.” I believe that it would, because
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`such an interpretation is not inconsistent with the ‘121 patent’s specification and
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`the understanding one of ordinary skill in the art would ascribe to this term when
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`looking for the broadest reasonable construction.
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`24. For example, the ‘121 patent describes that “the terms node and
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`processor are often used interchangeably herein,” And it explains “that according
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`to various implementations, a node (e.g., processors 202a-202d) may comprise
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`multiple sub-units, e.g., CPUs, memory controllers, I/O bridges, etc.” Ex. 1001,
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`6:52-57. FIG. 19 illustrates one example implementation of such a processing
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`node. See Ex. 1001, 27:25-28. Based on these descriptions and my understanding
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`of the ‘121 patent generally, it is apparent to me that a “processing node,” as that
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`term is used in the ‘121 patent, includes at least one processor.
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`25. The ‘121 patent further describes these processing nodes as end-points
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`within a larger interconnected system. Ex. 1001, 27:32-40. In independent claims
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`1, 16, and 25, the processing nodes are “interconnected by a first point-to-point
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`architecture” and are included in “a computer system” and, hence, each processing
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`node is a computer subsystem.
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`26. Furthermore, other references in the same field of art as the ‘121
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`patent use the word “processing node” in accordance with its common usage and,
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`therefore, in a manner consistent with the above-noted interpretation. For
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`example, Baumgartner describes a “data processing system that speculatively
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`forwards a read request to a remote processing node,” and states that “[p]rocessing
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`nodes 8a-8n may each include M (M ≥ 1) processors 10, a local interconnect 16,
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`and a system memory 18 . . . .” (emphasis added). Ex. 1011, 3:17-19 and FIG. 1.
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`27.
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`I have considered whether a broadest reasonable interpretation of
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`“probe” would be broad enough to cover “a mechanism that elicits a response from
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`a node to maintain cache coherency in a system.” I believe that it would, because
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`such an interpretation is not inconsistent with the ‘121 patent’s specification and
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`the understanding one of ordinary skill in the art would ascribe to this term when
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`looking for the broadest reasonable construction. In fact, the ‘121 patent defines
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`the term “probe” in nearly the exact same manner. Ex. 1001, 5:45-47 (“A
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`mechanism for eliciting a response from a node to maintain cache coherency in a
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`system is referred to herein as a probe.”). The broad usage of the term throughout
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`the rest of the ‘121 patent is consistent with the above interpretation. For example,
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`the ‘121 patent uses the term “probe” to describe messages used for snooping
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`cache, as well as messages that carry information for maintaining cache coherency
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`in a system. Ex. 1001, 5:47-48 (“In one example, a mechanism for snooping a
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`cache is referred to as a probe.”) and 11-66-67 (“any message for snooping a cache
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`can be referred to as a probe.”) and 11: 20-23 (“While probes and probe responses
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`carry information for maintaining cache coherency in the system, read responses
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`can carry actual fetched data.”). Though some embodiments described in the ‘121
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`patent contrast “probes” with other types of messages, I understand these to simply
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`be examples and not definitions. See Ex. 1001, 9:21-33.
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`28.
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`I have considered whether a broadest reasonable interpretation of
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`“probe filtering information” would be broad enough to cover “any criterion that
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`can be used to reduce the number of clusters or nodes probed.” I believe that it
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`would, because such an interpretation is not inconsistent with the ‘121 patent’s
`
`specification and the understanding one of ordinary skill in the art would ascribe to
`
`this term when looking for the broadest reasonable construction. In fact, the ‘121
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`patent defines the term “probe filtering information” in nearly the exact same
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`manner. Ex. 1001, 14:50-52 (“[a]ny criterion that can be used to reduce the
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`number of clusters or nodes probed is referred to herein as probe filter
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`information.”).
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`29. Moreover, the remainder of the ‘121 patent specification uses the term
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`“probe filtering information” consistent with this interpretation. For example, the
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`‘121 patent specification points out that FIG. 8 shows a diagram representing probe
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`filter information, and points out that the FIG. 8 probe filtering information “can be
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`used to reduce the number of transactions in a multiple or single cluster system.”
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`Ex. 1001, 14:48-50. Similarly, according to claim 3, the probe filtering
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`information may comprise a cache coherence directory which includes entries
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`corresponding to memory lines stored in the selected cache memories. Ex. 1001,
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`31:12-16.
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`30.
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`I have considered whether a broadest reasonable interpretation of
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`“states associated with selected ones of the cache memories” would be broad
`
`enough to cover “any modes or conditions of selected ones of the cache
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`memories.” I believe that it would, because such an interpretation is not
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`inconsistent with the ‘121 patent’s specification and the understanding one of
`
`ordinary skill in the art would ascribe to this term when looking for the broadest
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`reasonable construction.
`
`31.
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`In particular, the ‘121 patent does not limit the term “state” to a
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`specific type of state, such as standard coherence protocol states. See Ex. 1001,
`
`14:30-36. In fact, the ‘121 patent notes that “[t]he techniques of the present
`
`invention can be used with a variety of different possible memory line states.” See
`
`id. Moreover, the dictionary definition of the term “state” is a “mode or condition
`
`of being.” Ex. 1015, p. 1145. Presence is one example of a type of state. See Ex.
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`1015, p. 919 (defining “presence” as “the fact or condition of being present”
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`(emphasis added)). The ‘121 patent uses the term “state” consistent with the
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`dictionary definition. For example, the ‘121 patent describes that a “directory of
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`shared states . . . indicates where particular memory lines are cached within the
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`cluster.” Ex. 1001, 28:29-34.
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`32. Furthermore, the Chaiken reference (Ex. 1004), which is in the same
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`field of art as the ‘121 patent, uses the word “status,” which speaks to a “state,” in
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`a manner that is consistent with the above-noted interpretation and that further
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`supports the assertion that presence is one example of a type of state: “The full-
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`map protocol uses directory entries with one bit per processor and a dirty bit. Each
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`bit represents the status of the block in the corresponding processor’s cache
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`(present or absent).” Ex. 1004, p. 50 (emphasis added).
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`33.
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`I have considered whether a broadest reasonable interpretation of
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`“transmit the probes only to selected ones of the processing nodes” would be broad
`
`enough to cover “transmit each of the multiple probes only to one or more selected
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`processing nodes.” I believe that it would, because such an interpretation is not
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`inconsistent with the ‘121 patent’s specification and the understanding one of
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`ordinary skill in the art would ascribe to this term when looking for the broadest
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`reasonable construction.
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`34.
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`In particular, claims 1 and 16 recite that multiple “probes” are
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`transmitted to “selected ones of the processing nodes.” Because the claims
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`describe the transmission of plural “probes” instead of a single “probe,” the claim
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`language does not require that a single probe be transmitted to more than one
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`selected processing node, despite the claims’ use of the plural form of “selected
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`ones.” Rather, each probe could be transmitted to a single selected processing
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`node and still satisfy the requirements of claims 1 and 16. For example, if probe A
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`is transmitted to a selected processing node X and probe B is transmitted to a
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`selected processing node Y, probes (i.e., probes A and B) are transmitted only to
`
`selected ones of the processing nodes (i.e., processing nodes X and Y) despite the
`
`distribution of the nodes among plural processing nodes.
`
`35.
`
`I have considered whether a broadest reasonable interpretation of
`
`“cache coherence controller” would be broad enough to cover “any mechanism or
`
`apparatus that can be used to provide communication between multiple processing
`
`nodes while maintaining cache coherence.” I believe that it would, because such
`
`an interpretation is not inconsistent with the ‘121 patent’s specification and the
`
`understanding one of ordinary skill in the art would ascribe to this term when
`
`looking for the broadest reasonable construction.
`
`36. For example, the ‘121 patent specification points out with regard to
`
`FIG. 2, which shows a diagram of a multiple processor cluster that includes a
`
`cache coherence controller, that the cache coherence controller may be connected
`
`to processors within the cluster and with other clusters of processors. Ex. 1001,
`
`7:10-12 (In such a configuration, “cache coherence controller 230 communicates
`
`Page 17 of 123
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`U.S. Patent No. 7,296,121
`with both processors 202a-d as well as remote clusters using a point-to-point
`
`protocol.”)
`
`37. Though FIGS. 4-12 focus on such inter-cluster communications, the
`
`‘121 patent also describes the use of the cache coherence controller for filtering
`
`intra-cluster communications. See Ex. 1001, 25:24-57, 26:36-57. Specifically, the
`
`‘121 patent specification describes that “the filtering of probes within a cluster, i.e.,
`
`local probe filtering, may be implemented in systems having multiple clusters as
`
`well as systems having a single cluster of processors.” Ex. 1001, 26:36-39. Thus,
`
`a cache coherence controller may filter probes between clusters and/or between
`
`processors within a single cluster.
`
`38.
`
`I have considered whether a broadest reasonable interpretation of
`
`“cache coherence directory” would be broad enough to cover “a mechanism that
`
`facilitates the tracking of where particular memory lines are being cached.” I
`
`believe that it would, because such an interpretation is not inconsistent with the
`
`‘121 patent’s specification and the understanding one of ordinary skill in the art
`
`would ascribe to this term when looking for the broadest reasonable construction.
`
`For example, the ‘121 patent describes that, “according to some embodiments, a
`
`cache coherence directory is a mechanism that facilitates the tracking by that cache
`
`coherence controller of where particular memory lines within its cluster’s memory
`
`are being cached in remote clusters.” Ex. 1001, 18:43-47. Similarly, the ‘121
`
`Page 18 of 123
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`U.S. Patent No. 7,296,121
`patent describes that the cache coherence directory “indicates the existence and
`
`location of any remotely cached copies of the memory.” Ex. 1001, 21:7-8.
`
`39.
`
`I have considered whether a broadest reasonable interpretation of “the
`
`probes,” as used in claim 8, would be broad enough to cover “probes received by
`
`the probe filtering unit from the processing nodes.” I believe that it would,
`
`because such an interpretation is not inconsistent with the ‘121 patent’s
`
`specification and the understanding one of ordinary skill in the art would ascribe to
`
`this term when looking for the broadest reasonable construction. The only
`
`previous recitation of “probes” in either claim 8 or claim 1, from which claim 8
`
`depends, regards probes received by the probe filtering unit from the processing
`
`nodes. Therefore, I believe one of ordinary skill in the art would understand claim
`
`8 to simply require transmission of probes received by the probe filtering unit
`
`(from the processing nodes) to only the probe filtering unit (as opposed to, for
`
`example, the processing nodes broadcasting those probes received by the probe
`
`filtering unit to other processing nodes).
`
`IV. Legal Standards for Prior Art
`40.
`
`I understand that a patent or other publication must first qualify as
`
`prior art before it can be used to invalidate a patent claim.
`
`41.
`
`I understand that a U.S. or foreign patent qualifies as prior art to an
`
`asserted patent if the date of issuance of the patent is prior to the invention of the
`
`Page 19 of 123
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`U.S. Patent No. 7,296,121
`asserted patent. I further understand that a printed publication, such as an article
`
`published in a magazine or trade publication, qualifies as prior art to an asserted
`
`patent if the date of publication is prior to the invention of the asserted patent.
`
`42.
`
`I understand that a U.S. or foreign patent also qualifies as prior art to
`
`an asserted patent if the date of issuance of the patent is more than one year before
`
`the filing date of the asserted patent. I further understand that a printed
`
`publication, such as an article published in a magazine or trade publication,
`
`constitutes prior art to an asserted patent if the publication occurs more than one
`
`year before the filing date of the asserted patent.
`
`43.
`
`I understand that a U.S. patent qualifies as prior art to the asserted
`
`patent if the application for that patent was filed in the United Stated before the
`
`invention of the asserted patent.
`
`A.
`
`Legal Standards for Anticipation
`
`44.
`
`I understand that documents and materials that qualify as prior art can
`
`be used to invalidate a patent claim as anticipated or as obvious.
`
`45.
`
`I understand that, once the claims of a patent have been properly
`
`construed, the second step in determining anticipation of a patent claim requires a
`
`comparison of the properly construed claim language to the prior art on a
`
`limitation-by-limitation basis.
`
`46.
`
`I understand that a prior art reference “anticipates” an asserted claim,
`
`Page 20 of 123
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`U.S. Patent No. 7,296,121
`and thus renders the claim invalid, if all elements of the claim are disclosed in that
`
`prior art reference, either explicitly or inherently (i.e., necessarily present).
`
`47.
`
`I understand that anticipation in an inter partes review must be shown
`
`by a preponderance of the evidence.
`
`B.
`
`Legal Standards for Obviousness
`
`48.
`
`I understand that even if a patent is not anticipated, it is still invalid if
`
`the differences between the claimed subject matter and the prior art are such that
`
`the subject matter as a whole would have been obvious at the time the invention
`
`was made to a person of ordinary skill in the pertinent art.
`
`49.
`
`I understand that a person of ordinary skill in the art provides a
`
`reference point from which the prior art and claimed invention should be viewed.
`
`This reference point prevents one from using his or her own insight or hindsight in
`
`deciding whether a claim is obvious.
`
`50.
`
`I also understand that an obviousness determination includes the
`
`consideration of various factors such as (1) the scope and content of the prior art,
`
`(2) the differences between the prior art and the asserted claims, (3) the level of
`
`ordinary skill in the pertinent art, and (4) the existence of secondary considerations
`
`such as commercial success, long-felt but unresolved needs, failure of others, etc.
`
`51.
`
`I understand that an obviousness evaluation can be based on a
`
`combination of multiple prior art references. I understand that the prior art
`
`Page 21 of 123
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`
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`Case Nos.: IPR2015-00159, IPR2015-00161, IPR2015-00163, and IPR2015-00172
`U.S. Patent No. 7,296,
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