Trials@uspto.gov
`571.272.7822
`
`
`Paper No. 16
`
` Filed: May 11, 2015
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC.,
`SAMSUNG ELECTRONICS CO. LTD,
`SAMSUNG ELECTRONICS AMERICA, INC., and
`AMAZON.COM, INC.,
`Petitioner,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`____________
`
`Case IPR2015-00172
`Patent 7,296,121 B2
`____________
`
`
`
`Before JENNIFER S. BISK, NEIL T. POWELL, and KERRY BEGLEY,
`Administrative Patent Judges.
`
`BEGLEY, Administrative Patent Judge.
`
`
`
`DECISION
`Denying Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
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`

`

`IPR2015-00172
`Patent 7,296,121 B2
`
`Apple Inc., HTC Corporation, HTC America, Inc., Samsung
`
`Electronics Co. Ltd., Samsung Electronics America, Inc.,1 and Amazon.com,
`Inc. (collectively, “Petitioner”) filed a Petition requesting inter partes review
`of claims 1–9, 11, 12, and 16–24 of U.S. Patent No. 7,296,121 B2 (Ex. 1001,
`“the ’121 patent”). Memory Integrity, LLC (“Patent Owner”) filed a
`Preliminary Response to the Petition. Paper 11 (“Prelim. Resp.”).
`Pursuant to 35 U.S.C. § 314(a), an inter partes review may not be
`instituted unless “the information presented in the petition . . . and any
`response . . . shows that there is a reasonable likelihood that the petitioner
`would prevail with respect to at least 1 of the claims challenged in the
`petition.” Having considered the Petition and the Preliminary Response, we
`determine that there is not a reasonable likelihood that Petitioner would
`prevail in establishing that the challenged claims of the ’121 patent are
`unpatentable. Therefore, we deny institution of inter partes review.
`I. BACKGROUND
`A. THE ’121 PATENT
`The ’121 patent relates to techniques to reduce memory transaction
`
`traffic and to improve data access and cache coherency in systems with
`multiple processors connected using point-to-point links. Ex. 1001, 1:22–
`25, 2:39–47. The ’121 patent explains that cache coherency problems can
`arise in a system with multiple processors, each with an individual cache
`memory, because the system may contain multiple copies of the same data.
`Id. at 1:26–38. For example, if the caches of two different processors have a
`
`1 The Petition also lists Samsung Telecommunications America, LLC
`(“STA”) as a petitioner. Paper 6 (“Pet.”), 1. After the filing of the Petition,
`however, STA merged with and into Samsung Electronics America, Inc.
`Paper 10. Thus, STA no longer exists as a separate corporate entity. Id.
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`copy of the same data block and both processors “attempt to write new
`values into the data block at the same time,” then the two caches may have
`different data values and the system may be “unable to determine what value
`to write through to system memory.” Id. at 1:37–45.
`
`The ’121 patent discloses a computer system with processing nodes,
`each with a cache memory, connected by a point-to-point architecture. Id. at
`[57], 2:48–62. The system also includes a “probe filtering unit” that can
`receive a probe, “[a] mechanism for eliciting a response from a node to
`maintain cache coherency in a system,” from a processing node. Id. at [57],
`2:52–65, 5:45–47. The probe filtering unit then can evaluate the probe
`based on probe filtering information, specifically “[a]ny criterion that can be
`used to reduce the number of clusters or nodes probed,” and can transmit the
`probe to selected processing nodes. Id. at [57], 2:52–3:5, 14:50–52; see id.
`at 28:29–58, 29:43–46. The probe filtering unit also may be operable to
`accumulate responses from the selected processing nodes and to respond to
`the node from which the probe originated. Id. at 3:5–8, 28:59–67, 29:46–51.
`Figure 18 of the patent is reproduced below.
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`
`Figure 18 is a diagrammatic representation of a multiple processor
`system with a probe filtering unit. Id. at 3:61–63, 26:58–27:20, Fig. 18.
`Specifically, Figure 18 depicts multiple processor system 1800 with
`processing nodes 1802a–d interconnected by point-to-point communication
`links 1808a–e. Id. at 26:58–27:1. System 1800 also includes probe filtering
`unit 1830 as well as I/O switch 1810, one or more Basic I/O systems
`(“BIOS”) 1804, I/O adapters 1816, 1820, and a memory subsystem with
`memory banks 1806a–d. Id. at 3:61–63, 26:58–27:20, Fig. 18.
`B. ILLUSTRATIVE CLAIM
`Claims 1 and 16 are the only independent claims challenged in the
`Petition. Claim 1 is illustrative of the claimed subject matter and recites:
`1. A computer system comprising a plurality of processing
`nodes interconnected by a first point-to-point architecture,
`each processing node having a cache memory associated
`therewith,
`the computer system further comprising a probe filtering unit
`which is operable to receive probes corresponding to memory
`lines from the processing nodes and to transmit the probes only
`to selected ones of the processing nodes with reference to probe
`filtering information representative of states associated with
`selected ones of the cache memories.
`Id. at 30:65–31:7 (line breaks added).
`C. ASSERTED PRIOR ART
`The Petition relies upon the following prior art references, as well as
`the supporting Declaration of Robert Horst, Ph.D. (Ex. 1014):
`U.S. Patent No. 6,490,661 B2 (filed Dec. 21, 1998) (issued Dec. 3,
`2002) (Ex. 1006, “Keller”);
`Daniel Lenoski et al., The Directory-Based Cache Coherence
`Protocol for the DASH Multiprocessor, in THE 17TH ANNUAL
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`INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE 148 (1990)
`(Ex. 1005, “Stanford DASH”);
`JOSÉ DUATO ET AL., INTERCONNECTION NETWORKS (1997) (Corrected
`Ex. 1007, “Duato”);
`
`MICHAEL JOHN SEBASTIAN SMITH, APPLICATION-SPECIFIC INTEGRATED
`CIRCUITS (1997) (Ex. 1008, “Smith”); and
`ADVANCED MICRO DEVICES, INC., HYPERTRANSPORT TECHNOLOGY
`I/O LINK (2001) (EX. 1018, “HYPERTRANSPORT”).
`D. ASSERTED GROUNDS OF UNPATENTABILITY
`Petitioner asserts the following grounds of unpatentability. Pet. 3.
`Challenged Claim[s]
`Basis
`Reference[s]
`1–3, 8, 11, 12, 16, 19, 20, and 22
`§ 102 Stanford DASH
`4–6
`§ 103 Stanford DASH and Keller
`7
`§ 103 Stanford DASH and
`HyperTransport
`§ 103 Stanford DASH and Duato
`§ 103 Stanford DASH and Smith
`
`9
`17–24
`
`II. ANALYSIS
`A. CLAIM INTERPRETATION
`We begin our analysis by addressing the meaning of the claims. The
`Board interprets claims using the “broadest reasonable construction in light
`of the specification of the patent in which [they] appear[].” 37 C.F.R.
`§ 42.100(b); see In re Cuozzo Speed Techs., LLC, 778 F.3d 1271, 1279–82
`(Fed. Cir. 2015). We presume a claim term carries its “ordinary and
`customary meaning,” which is “the meaning that the term would have to a
`person of ordinary skill in the art in question” at the time of the invention.
`In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007) (citation
`and quotations omitted). This presumption, however, is rebutted when the
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`patentee acts as his own lexicographer by giving the term a particular
`meaning in the specification with “reasonable clarity, deliberateness, and
`precision.” In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994).
`Petitioner and Patent Owner each proffer proposed constructions of
`several claim terms. On this record and for purposes of this decision, we
`determine that only the claim terms addressed below require construction.2
`1. “probe” (claims 1–3, 6, 8, 9, 11, 12, 16, 17, 19, 20, 22, and 24)
`Petitioner points out that the ’121 patent defines the term “probe,”
`
`which is recited in challenged claims 1–3, 6, 8, 9, 11, 12, 16, 17, 19, 20, 22,
`and 24, and argues that the term should be construed as “a mechanism that
`elicits a response from a node to maintain cache coherency in a system.”
`Pet. 6–7. Patent Owner does not address Petitioner’s assertions.
`We note that Petitioner’s proposed construction slightly differs from
`the definition of “probe” in the ’121 patent, which uses the language “a
`mechanism for eliciting a response,” as opposed to “a mechanism that elicits
`a response” in Petitioner’s proposed construction. Id. (emphases added); see
`Ex. 1001, 5:45–47. Petitioner has provided no reason for the difference in
`wording. Therefore, for purposes of this decision, we adopt as the broadest
`reasonable construction of “probe” the express definition of the term in the
`’121 patent: “[a] mechanism for eliciting a response from a node to
`maintain cache coherency in a system.” Ex. 1001, 5:45–47.
`
`2 We note that Petitioner proposes a construction of “transmit the probes
`only to selected ones of the processing nodes,” as recited in claims 1 and 16.
`Pet. 10–11. As detailed below, our denial of the Petition turns on this
`limitation. Nonetheless, we need not address Petitioner’s proposed
`construction, because it involves an aspect of the claim language (i.e.,
`whether each probe must be transmitted to more than one selected
`processing node) that does not impact our analysis. See id.
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`2. “probe filtering information” (claims 1, 3, 6, and 16)
`Petitioner argues that the ’121 patent expressly defines “probe
`
`filtering information,” as recited in challenged claims 1, 3, 6, and 16.
`Pet. 7–8. Patent Owner does not respond to this argument. We agree that
`the ’121 patent defines the term “probe filter information.” Ex. 1001,
`14:50–52. On the record before us, we adopt this definition as the broadest
`reasonable construction of the claim term “probe filtering information”:
`“[a]ny criterion that can be used to reduce the number of clusters or nodes
`probed.” Id.
`
`3. “cache coherence controller” (claim 3)
`Petitioner also correctly contends that the ’121 patent defines “cache
`
`coherence controller,” as recited in claim 3. Pet. 11–12. Patent Owner does
`not address this assertion. For purposes of this decision, we adopt this
`express definition as the broadest reasonable construction of “cache
`coherence controller”: “[a]ny mechanism or apparatus that can be used to
`provide communication between multiple processor clusters while
`maintaining cache coherence.” Ex. 1001, 7:2–5.
`B. ASSERTED ANTICIPATION GROUND
`We turn to the asserted grounds. Petitioner argues that Stanford
`
`DASH anticipates claims 1–3, 8, 11, 12, 16, 19, 20, and 22 of the
`’121 patent. Pet. 18–36.
`
`1. Stanford DASH
`Stanford DASH discusses the DASH system, a scalable shared-
`
`memory multiprocessor developed at Stanford University. Ex. 1005, 148.
`The DASH system uses a “bus-based snoopy scheme . . . to keep caches
`coherent within a cluster” and a “distributed directory-based coherence
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`protocol” to maintain “inter-[cluster] cache consistency.” Id.; see id. at 152.
`In other words, the DASH system uses two different cache-coherency
`protocols, one to maintain cache coherency within a cluster (bus-based
`snoopy protocol) and another to maintain cache coherency between clusters
`(distributed directory-based coherence protocol). See id. at 148. Stanford
`DASH explains that the use of a bus-based snoopy protocol to maintain
`cache coherency within a cluster was a design choice. See id. at 152.
`The DASH system consists of a number of clusters connected through
`a “high-bandwidth low-latency interconnection network,” such as meshes or
`hypercubes. Id. at 148–49. Each cluster consists of a modified version of
`the Silicon Graphics POWER Station 4D/240, “a commercial bus-based
`multiprocessor” that has four high-performance processors. Id. Each
`4D/240 system is “supplemented” with a directory board. Id.
`
`The directory board “maintain[s] the cache coherence across the
`nodes and serv[es] as the interface to the interconnection network.” Id.
`at 150, Fig. 3. Figure 3 of Stanford DASH is reproduced below.
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`Figure 3 is a block diagram illustrating the directory board. Id. As shown in
`Figure 3, the directory board “consists of five major subsystems”:
`(1) directory controller, (2) pseudo-CPU, (3) reply controller, (4) network
`interface (mesh routing chips), and (5) hardware monitoring logic
`(performance monitor). Id. The first subsystem, the directory controller, or
`“DC,” “initiates out-bound network requests and replies.” Id. at 150. The
`directory controller “contains the directory memory corresponding to the
`portion of main memory present within the cluster.” Id. The directory
`memory is organized as an array of directory entries with one entry,
`consisting of a state bit and a bit vector of pointers, for each memory block.
`Id. at 150–51. The second subsystem, the pseudo-CPU, or “PCPU,”
`“buffer[s] incoming requests and issu[es] such requests on the cluster bus.”
`Id. at 150. The third subsystem, the reply controller, “tracks outstanding
`requests made by the local processors and receives and buffers the
`corresponding replies from remote clusters.” Id. The fourth subsystem, the
`network interface, “consists of a pair of meshes,” one that handles request
`messages and another that handles reply messages. Id. The fifth subsystem,
`hardware monitoring logic, samples “directory board and bus events from
`which usage and performance statistics can be derived.” Id.
`
`Stanford DASH explains how the DASH system processes read
`requests, with reference to a local cluster, a home cluster, and a remote
`cluster. Id. at 151–54. The local cluster is the cluster that “contains the
`processor originating a given request.” Id. at 151. The home cluster is the
`cluster that “contains the main memory and directory for a given physical
`memory address.” Id. A remote cluster “is any other cluster.” Id. Figure 4
`of Stanford DASH is reproduced below.
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` Figure 4 illustrates the flow of a read request for a block of data in a “dirty-
`remote state,” i.e., “in a modified state” in the cache of a “remote cluster.”
`Id. at 152, Fig. 4. At the local cluster, the requesting processor, after
`checking whether the block of data is present in its cache, “issues a read
`request on the bus” in the local cluster. Id. “If the read request cannot be
`satisfied by the local cluster,” the request is sent to the home cluster (Step 1
`in Figure 4). Id.
`“When the read request reaches the home cluster,” the pseudo-CPU in
`the directory board “issue[s]” the request “on that cluster’s bus,” i.e., “reads
`[the] home bus.” Id.; see id. at Fig. 3. “This causes the directory to look up
`the status of the memory block.” Id. at 152. “If the block is in the dirty-
`remote state,” the directory controller in the directory board, which contains
`the directory memory, “forward[s]” the read request “to the owning, dirty
`cluster,” i.e., “the remote cluster that has a dirty copy of the data” (Step 2 in
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`Figure 4). Id. at 152, Fig. 4; see id. at Fig. 3 (showing arrow from “request
`network”/“mesh routing chip” only into Pseudo-CPU, arrows from Pseudo-
`CPU only to bus, and arrows into Directory Controller only from bus).
`The remote cluster “sends out two messages in response” to the read
`request. Id. at 152, Fig. 4. First, a “message containing the data is sent
`directly to” the local cluster (Step 3a in Figure 4). Id. Second, a “sharing
`writeback request is sent to the home cluster” (Step 3b in Figure 4). Id.
`“The sharing writeback request writes the cache block back to memory and
`also updates the directory.” Id.
`
`Stanford DASH also explains how read-exclusive requests flow
`through the DASH system. Id. at 153–54, Fig. 5. “The flow of a read-
`exclusive [request] is similar to that of a read request.” Id. at 153.
`2. Discussion
`Having considered the arguments and evidence before us, we are not
`
`persuaded that Petitioner has made a sufficient showing that Stanford DASH
`discloses a “probe filtering unit . . . operable . . . to transmit the probes only
`to selected ones of the processing nodes with reference to probe filtering
`information representative of states associated with selected ones of the
`cache memories”—as recited in independent claims 1 and 16. Ex. 1001,
`31:1–7, 32:7–16. In addressing this limitation, Petitioner argues that
`Stanford DASH’s “directory board of the home cluster,” read requests and
`read-exclusive requests, clusters, and directory memory with directory
`entries correspond to the recited “probe filtering unit,” “probes,” “processing
`nodes,” and “probe filtering information,” respectively. Pet. 22–28, 33–34.
`Petitioner focuses on Stanford DASH’s disclosure that when a read request
`reaches the home cluster, the directory board “looks up the status of that
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`memory block” in the directory memory and if the memory block is in the
`dirty-remote state, the directory board “forward[s]” the request to the
`“owning, dirty cluster.” Id. at 25–27 (quoting Ex. 1005, 150); see Ex. 1014
`¶ C-12. Petitioner also relies on the similar processing of read-exclusive
`requests by the directory board of the home cluster. See Pet. 28; Ex. 1014
`¶¶ C-19–C-20, C-23.
`
`Patent Owner, however, argues that the directory board of the home
`cluster in Stanford DASH does not transmit probes only to selected
`processing nodes with reference to probe filtering information, because the
`directory board of the home cluster—specifically, its pseudo-CPU
`subsystem—broadcasts all received requests to all processors in the cluster
`by issuing the requests on the bus, without any filtering or reference to the
`directory memory. Prelim Resp. 15–19, 23–25. Patent Owner argues that
`when a request is received by the home cluster in the DASH system, the
`pseudo-CPU in the directory board forwards the request to the cluster’s bus.
`Id. Then, the directory controller in the directory board receives the request
`from the bus and consults the directory memory to forward the request to
`specific clusters. Id. Patent Owner points out that the pseudo-CPU’s
`broadcast of requests on the bus is part of the bus-based snoopy protocol
`used to maintain cache coherency within clusters—an express and
`intentional design choice in the DASH system. Id. at 15, 23.
`We agree with Patent Owner that Petitioner’s arguments—which
`focus on filtering actions that are performed by the directory controller in the
`directory board of the home cluster—overlook that another subsystem in the
`directory board—the pseudo-CPU—issues all read and read-exclusive
`requests on the bus of the home cluster as part of the bus-based snoopy
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`protocol for intra-cluster cache coherency. See Ex. 1005, 148, 152.
`Stanford DASH makes explicit the differing roles of the pseudo-CPU and
`the directory controller in explaining the functions of these two subsystems
`in the directory board. Specifically, Stanford DASH states that the pseudo-
`CPU “buffer[s] incoming requests and issu[e]s such requests on the cluster
`bus,” whereas the directory controller “contains the directory memory” and
`“initiates out-bound network requests and replies.” Id. at 150; see Pet. 24.
`Likewise, Stanford DASH’s Figure 3, which illustrates the subsystems in the
`directory board, illustrates that “request[s]” proceed from the mesh routing
`chip into the pseudo-CPU, which “[f]orward[s] remote CPU request[s] to
`[the] local MPBUS.” Ex. 1005, Fig. 3 (depicting arrow from “request
`network”/“mesh routing chip” only into Pseudo-CPU and arrows from
`Pseudo-CPU only to bus); see Prelim. Resp. 24–25 (annotated Figure 3 of
`Stanford DASH). Then, from the bus, requests enter the directory controller,
`which contains the “[d]irectory” and which “[f]orward[s] local requests to
`remotes.” Ex. 1005, Fig. 3 (showing arrows into Directory Controller only
`from bus); see Prelim. Resp. 24–25.
`
`In discussing the flow of both read and read-exclusive requests,
`Stanford DASH again emphasizes the role of the pseudo-CPU in the
`directory board of the home cluster to issue these requests on the bus. In
`particular, with respect to read requests, Stanford DASH states: “When the
`read request reaches the home cluster, it is issued on that cluster’s bus. This
`causes the directory to look up the status of that memory block.” Ex. 1005,
`152. Figure 4, illustrating the flow of a read request, explicitly states that it
`is the pseudo-CPU that issues the request on the bus, i.e., “reads the home
`bus.” Id. at 150, Fig. 4; see Pet. 27. Similarly, for read-exclusive requests,
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`upon reaching the home cluster, “the read-exclusive request is echoed on the
`bus.” Ex. 1005, 153. Figure 5, which depicts the flow of a read-exclusive
`request, explains that it is the pseudo-CPU that “issues” the read-exclusive
`request “on [the] home bus.” Id. at 150, Fig. 5; see Ex. 1014 ¶ C-20.
`In sum, Stanford DASH discloses that the pseudo-CPU in the
`directory board of the home cluster issues read and read-exclusive requests
`on the cluster’s bus—without consulting the directory memory in the
`directory controller to filter the requests. Therefore, even if another
`subsystem of the directory board—the directory controller—refers to the
`directory memory to filter these requests in sending them to another cluster,
`the directory board of the home cluster cannot disclose the relevant
`limitation in claims 1 and 16, which expressly requires that the probe
`filtering unit be operable to transmit these requests (“probes”) only to
`selected clusters (“processing nodes”) based on the directory memory
`(“probe filtering information”).
`Accordingly, we are not persuaded that the directory board of the
`home cluster constitutes a “probe filtering unit . . . operable . . . to transmit
`the probes only to selected ones of the processing nodes with reference to
`probe filtering information representative of states associated with selected
`ones of the cache memories”—as recited in independent claims 1 and 16.
`Ex. 1001, 31:1–7, 32:7–16 (emphasis added). Thus, Petitioner has not
`shown a reasonable likelihood that it would prevail in establishing that
`Stanford DASH anticipates independent claims 1 and 16. In addition,
`because claims 2, 3, 8, 11, and 12 depend from claim 1 and claims 19, 20,
`and 22 depend from claim 16, Petitioner has not shown a reasonable
`likelihood of proving anticipation with respect to these claims.
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`
`C. ASSERTED OBVIOUSNESS GROUNDS
`1. Obviousness Over Stanford DASH and Keller
`Petitioner argues claims 4–6 of the ’121 patent would have been
`
`obvious over Stanford DASH and Keller. Pet. 36–49.
`a. Keller
`Keller discloses multiprocessing computer system 10, which “includes
`
`several processing nodes” 12A–D. Ex. 1006, 4:33–36; see id. at Fig. 1. A
`“set of dual-unidirectional links” “interconnects” processing nodes 12A–D.
`Id. at 4:57–58; see id. at 2:18–21. “Each unidirectional link forms as a
`point-to-point interconnect that is designed for packetized information
`transfer.” Id. at 2:28–30.
`
`Keller refers to advantages of using a system that connects processors
`with point-to-point links as opposed to a shared bus. In particular, Keller
`states that data transfer over a dual unidirectional link is “substantially
`faster” than data transfer using a memory bus, which results in “reduced data
`transfer latencies.” Id. at 3:45–51. Further, Keller explains that “shared bus
`systems suffer from several drawbacks,” including slow data transfer,
`operation “at a relatively low frequency,” and a “lack of scalability to a
`larger number of devices.” Id. at 1:32–55.
`b. Discussion
`Petitioner argues that it would have been obvious to combine Stanford
`
`DASH with Keller to reach the computer system recited in claims 4–6,
`which depend from claim 1. See Pet. 36–49, Ex. 1001, 31:17–31.
`Specifically, Petitioner contends that, given the advantages of using point-to-
`point links rather than a shared bus, as discussed in Keller, one of ordinary
`skill in the art would have had reason to substitute Keller’s computer
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`system 10—which uses point-to-point links to connect its processors—for
`Stanford DASH’s 4D/240 system—which uses a shared bus to connect its
`processors. See Pet. 37–39. In the proposed combination, Keller’s computer
`systems 10, like the 4D/240 systems used in Stanford DASH, would be
`“supplement[ed] . . . with the directory controller boards described in
`Stanford DASH to create a similar multi-cluster architecture able to maintain
`cache coherence both within clusters and across clusters.” Id. at 37.
`
`We are not persuaded that Petitioner has proffered sufficient evidence
`that the combination of Stanford DASH and Keller would have rendered
`claims 4–6 obvious. First, Petitioner has not explained adequately how,
`under its proposed combination, Keller’s computer system 10 would be
`supplemented with the directory board disclosed in Stanford DASH. See id.
`at 37–49. The 4D/240 system used in Stanford DASH is a “bus-based
`multiprocessor.” Ex. 1005, 50. The bus is integral to the operation of
`Stanford DASH’s directory board. For example, as shown in Figure 3, the
`pseudo-CPU of the directory board issues requests on the cluster’s bus and
`requests enter the directory controller of the directory board from the bus.
`See id. at 150, 152–53, Fig. 3; see supra Part II.B. In contrast, Keller’s
`computer system 10 uses point-to-point links, rather than a shared bus, to
`connect its processors. Ex. 1006, 2:18–30, 4:57–58. Yet neither Petitioner
`nor Dr. Horst explain how the directory board of Stanford DASH would be
`adapted to operate with point-to-point links, rather than a bus. Nor do they
`address whether one of ordinary skill in the art would have had a reasonable
`expectation of success in replacing Stanford DASH’s bus-based 4D/240
`system with Keller’s computer system 10, and modifying this system to
`include Stanford DASH’s directory board. See Amgen Inc. v. F. Hoffman-La
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`Roche Ltd., 580 F.3d 1340, 1362 (Fed. Cir. 2009) (“An obviousness
`determination requires that a skilled artisan would have perceived a
`reasonable expectation of success in making the invention in light of the
`prior art.”).
`Second, Petitioner relies exclusively on Stanford DASH—
`specifically, its directory board of the home cluster—for the limitation “a
`probe filtering unit . . . operable . . . to transmit the probes only to selected
`ones of the processing nodes with reference to probe filtering information
`representative of states associated with selected ones of the cache
`memories,” as recited in independent claim 1. See Pet. 43–44; Prelim.
`Resp. 32–34. Yet as explained above in the asserted anticipation ground, we
`are not persuaded that Stanford DASH discloses this limitation. Petitioner
`does not address any modifications to Stanford DASH’s directory board of
`the home cluster that would teach or suggest the limitation. Nor does
`Petitioner point to any teachings in Keller regarding probe filtering.3
`Therefore, Petitioner’s obviousness arguments for claims 4–6 do not show
`sufficiently that the proposed combination of Stanford DASH with Keller
`teaches or suggests this limitation.
`
`
`3 Further, we note that Patent Owner points to disclosures in Keller that
`suggest Keller’s system does not feature probe filtering. See Prelim. Resp.
`33–34 (quoting Ex. 1006, [57], 2:48–65); Ex. 1006, [57] (“[T]he target
`processing node transmits a probe command to all the remaining processing
`nodes in the computer system regardless of whether one or more of the
`remaining nodes have a copy of the data cached in their respective caches.”);
`id. at 2:48–56. Petitioner’s arguments suggest the same. See, e.g., Pet. 44
`(“Using the techniques described by Keller, the directory board of the
`remote cluster would multicast the read request inside its
`multiprocessor . . . .”); Ex. 1014 ¶¶ C-37, C-40–C-41.
`
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`IPR2015-00172
`Patent 7,296,121 B2
`
`
`Accordingly, Petitioner has not shown a reasonable likelihood that it
`would prevail in establishing that claims 4–6 would have been obvious over
`Stanford DASH and Keller.
`2. Remaining Asserted Obviousness Grounds
`In addition to the asserted grounds of anticipation by Stanford DASH
`
`and obviousness over Stanford DASH and Keller, the Petition asserts three
`other obviousness grounds that rely on Stanford DASH. Specifically, the
`Petition challenges claim 7—which depends from independent claim 1—as
`obvious over Stanford DASH and HyperTransport, claim 9—which depends
`from independent claim 1—as obvious over Stanford DASH and Duato, and
`claims 17–24—which depend from independent claim 16—as obvious over
`Stanford DASH and Smith. Pet. 49–59.
`Each of these asserted obviousness grounds relies on the asserted
`anticipation ground for the independent claims, and discusses the additional
`reference (HyperTransport, Duato, or Smith) only to address the additional
`limitations of the relevant dependent claims. See id. Therefore, the asserted
`grounds rely exclusively on Stanford DASH as teaching or suggesting the
`limitations of independent claims 1 and 16. See id. For the reasons
`explained above in our analysis of the asserted ground of anticipation by
`Stanford DASH, Petitioner has not made a sufficient showing that
`Stanford DASH teaches or suggests a “probe filtering unit . . . operable . . .
`to transmit the probes only to selected ones of the processing nodes with
`reference to probe filtering information representative of states associated
`with selected ones of the cache memories”—as recited in independent
`claims 1 and 16. Ex. 1001, 31:1–7, 32:7–16.
`
`
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`

`IPR2015-00172
`Patent 7,296,121 B2
`
`Accordingly, we determine that the Petition does not establish a
`
`reasonable likelihood that Petitioner would prevail in showing that claim 7
`would have been obvious over Stanford DASH and HyperTransport, claim 9
`would have been obvious over Stanford DASH and Duato, and claims 17–24
`would have been obvious over Stanford DASH and Smith.
`III. ORDER
`For the reasons given, it is:
`ORDERED that pursuant to 35 U.S.C. § 314(a), the Petition is denied.
`
`
`
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`
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`

`IPR2015-00172
`Patent 7,296,121 B2
`
`PETITIONER:
`W. Karl Renner
`Roberto J. Devoto
`FISH & RICHARDSON P.C.
`P.O. Box 1022
`Minneapolis, MN 55440-1022
`(202) 783-5070
`ax@fr.com
`IPR39521-0007IP3@fr.com
`
`PATENT OWNER:
`Jonathan D. Baker
`FARNEY DANIELS PC
`411 Borel Avenue, Suite 350
`San Mateo, CA 94402
`(424) 268-5210
`jbaker@farneydaniels.com
`
`Bryan Atkinson
`FARNEY DANIELS PC
`800 S. Austin, Suite 200
`Georgetown, TX 78626
`(512) 582-2836
`batkinson@farneydaniels.com
`
`
`
`
`20
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