UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC., SAMSUNG
`ELECTRONICS CO. LTD, SAMSUNG ELECTRONICS AMERICA, INC., AND
`AMAZON.COM, INC.,
`Petitioners,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`____________
`
`Case IPR2015-00163
`Patent 7,296,121
`____________
`
`
`
`
`
`PETITIONER’S REQUEST FOR REHEARING
`PURSUANT TO 37 C.F.R. § 42.71
`
`
`
`
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC., SAMSUNG
`ELECTRONICS CO. LTD, SAMSUNG ELECTRONICS AMERICA, INC., AND
`AMAZON.COM, INC.,
`Petitioners,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`____________
`
`Case IPR2015-00163
`Patent 7,296,121
`____________
`
`
`
`
`
`PETITIONER’S REQUEST FOR REHEARING
`PURSUANT TO 37 C.F.R. § 42.71
`
`
`
`
`
`IPR2015-00163
`Patent 7,296,121
`
`I.
`
`Introduction
`Apple Inc., HTC Corporation, HTC America, Inc., Samsung Electronics Co.
`
`Ltd, Samsung Electronics America, Inc., and Amazon.com, Inc. (“Petitioners”)
`
`hereby respectfully request rehearing of the May 8, 2015 Decision (“Decision”),
`
`granting-in-part and denying-in-part institution of trial. In particular, Petitioners
`
`request rehearing of the Board’s decision not to institute review with regard to
`
`claim 12. In rendering its Decision, the Board misapprehended the Petition’s
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`application of Koster to the language of claim 12.
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`First, the Board misapprehended the Petitions’ argument with respect to
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`claim 12, which focused solely on the exemplary single response memory
`
`transaction disclosed in FIG. 9 of Koster, where a requesting microprocessor 182
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`received one and only one response from the other microprocessors and, therefore,
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`in this example, necessarily completed its memory transaction after receiving one
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`and only one response. See Petition, pp. 34-37. While this example alone satisfies
`
`claim 12, as described in the Petition, the Board focused on the fact that Koster’s
`
`system additionally supports memory transactions that may involve multiple
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`responses, where the “requesting processor 182 could potentially receive one, two,
`
`or three responses with copies of the requested data” (emphasis added). See
`
`Decision, p. 23. The ability of Koster’s system to support memory transactions
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`that involve multiple responses does not undermine its disclosure of a processor
`
`
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`1
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`
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`IPR2015-00163
`Patent 7,296,121
`
`programmed to function as described in its Fig. 9, which clearly supports memory
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`transactions that involve a single response and, as noted in the Petition, such single
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`response transactions alone satisfy the features of claim 12.
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`Second, when explaining its denial of the Petition’s proposed ground for
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`unpatentability of claim 12 based on Koster, the Board criticized the Petition for
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`failing to demonstrate how Koster disclosed a node programmed to perform a
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`“memory transaction ... before all the responses are in.” See Decision, p. 23
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`(“Petitioner does not point us to any disclosure in Koster that the memory
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`transaction occurs before all the responses are in. See Pet. 23–37. Thus, we are not
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`persuaded that Petitioner nodes is programmed to complete a memory transaction
`
`after receiving a first number of responses to a first probe” “and the first number is
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`one,” as required by claim 12.”). It is evident from this portion of the Decision that
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`the Board has misapprehended the plain meaning attributed by the Petition to claim
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`12, as the Decision introduces the allegedly unmet non-limitations (“before all the
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`responses are in”) into claim 12. Specifically, contrary to the Petition, the
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`Decision reads claim 12 as if that claim requires a node programmed to trigger
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`transactions “before all the responses are in.” In fact, claim 11 merely requires a
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`node programmed to trigger transactions “after receiving a first number of
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`responses,” and claim 12 merely requires the first number to be “one.” Neither the
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`Patent Owner Preliminary Response nor the Petition misapprehends the plain
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`2
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`IPR2015-00163
`Patent 7,296,121
`
`meaning of claim 12 by introducing this new limitation. Rather, in applying
`
`Koster to claim 12, the Petition explains that claim 12 is given its plain meaning
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`and that FIG. 9 of Koster meets claim 12 by disclosing a microprocessor (182) that
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`is programmed to complete a memory transaction after receiving just “one”
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`response to a first probe. See Petition, pp. 4-5 and 36. While the Decision
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`embraces this description of Koster, it nevertheless refused to apply Koster to
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`claim 12 based on Koster’s alleged failure to meet the “before all the responses are
`
`in” feature that was inappropriately introduced by the Decision into claim 12.
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`Accordingly, misapprehension and oversight led the Board to deny
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`institution of the proposed ground for unpatentability of claim 12 based on Koster.
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`II. Applicable Rules
`37 C.F.R. § 42.71 (d) states:
`
`(d) Rehearing. A party dissatisfied with a decision may file a request
`for rehearing, without prior authorization from the Board. The burden
`of showing a decision should be modified lies with the party
`challenging the decision. The request must specifically identify all
`matters the party believes the Board misapprehended or overlooked,
`and the place where each matter was previously addressed in a
`motion, an opposition, or a reply. A request for rehearing does not toll
`times for taking action. Any request must be filed:
`(1) Within 14 days of the entry of a non-final decision or a decision
`to institute a trial as to at least one ground of unpatentability asserted
`in the petition; or
`
`
`
`3
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`IPR2015-00163
`Patent 7,296,121
`
`
`(2) Within 30 days of the entry of a final decision or a decision not to
`institute a trial.
`
`In accordance with 37 C.F.R. § 42.71 (d)(1), this request is being filed
`
`within 14 days of the entry of a decision to institute a trial as to at least one ground
`
`of unpatentability asserted in the petition.
`
`III. Requested Relief
`Petitioners respectfully request reconsideration of the Board’s decision not
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`to institute a review of claim 12 of U.S. Patent No. 7,296,121 as being anticipated
`
`by Koster. Petitioners submit that Koster anticipates claim 12 and respectfully
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`request that the Board institute review of claim 12 as part of IPR2015-00163.
`
`IV. Claim
`Claim 12 is reproduced below—along with the language of claim 11 from
`
`which it depends—with the significant language highlighted:
`
`
`
`11. The computer system of claim 1 wherein each of the processing
`nodes is programmed to complete a memory transaction after
`receiving a first number of responses to a first probe, the first number
`being fewer than the number of processing nodes.
`
`
`
`12. The computer system of claim 11 wherein the probe filtering unit
`has temporary storage associated therewith for holding read response
`data from one of the cache memories, and the first number is one.
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`
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`4
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`IPR2015-00163
`Patent 7,296,121
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`(emphasis added).
`
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`V. Argument
`Referencing the example depicted in Koster’s Fig. 9, the Petition addresses
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`each feature of claim 12. For instance, the Petition states: “in the example of FIG.
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`9, a requesting microprocessor 182 necessarily completes its memory transaction
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`based on a single response from a microprocessor 188 that is determined to be
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`storing a copy of requested data” (emphasis added). See Petition, p. 36. In
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`referencing the example shown in FIG. 9 of Koster, the Petition asserts that Koster
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`discloses a requesting microprocessor 182 receiving one and only one response
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`from a plurality of microprocessors 184, 186 and 188 in response to a probe
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`request. That is, in the example shown in FIG. 9, the requesting microprocessor
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`182 receives a single response from microprocessor 188, with no responses being
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`received from microprocessors 184 and 186. Thus, in this disclosed example,
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`which was cited in the Petition, the requesting microprocessor 182 is indeed
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`programmed to complete its memory transaction after receiving one (and only one)
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`response. This is evident from the fact that the Koster processor performs the
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`memory transaction in response to the one and only response, when no other
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`responses are received. After all, in the absence of such programming, the Koster
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`processor would not have similarly responded. As such, as noted in the Petition,
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`this disclosure alone is sufficient to satisfy claim 12.
`5
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`IPR2015-00163
`Patent 7,296,121
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`While the Petition clearly relies on Koster’s Fig. 9 disclosure,
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`misapprehension of this argument (and the corresponding portion of Koster) led to
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`denied institution of the Koster ground against claim 12. In greater detail, while
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`the Petition’s argument focused solely on the exemplary single response memory
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`transaction shown in FIG. 9, the Board instead focused on the fact that Koster’s
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`system supports memory transactions that may involve multiple responses, where
`
`the “requesting processor 182 could potentially receive one, two, or three
`
`responses with copies of the requested data” (emphasis added). See Decision, p.
`
`23. But the ability of Koster’s system to support memory transactions that involve
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`multiple responses is not relevant to the language of claim 12, as Koster’s system
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`clearly supports memory transactions that involve a single response, and such
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`single response transactions alone satisfy the features of claim 12. After all, as
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`indicated above, through its Fig. 9 example, Koster discloses a processor that
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`reacts to a single probe response by performing a memory transaction. This
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`processor configuration is sufficient to meet claim 12, and it is not undone by how
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`that processor reacts when facing scenarios that involve multiple probe responses.
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`Importantly, given the Petition’s focus on single response memory
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`transactions as satisfying claim 12, the Decision’s assertion that the Petition makes
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`no attempt to “point us to any disclosure in Koster that the memory transaction
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`occurs before all responses are in” (emphasis added) is neither surprising nor is it a
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`
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`6
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`IPR2015-00163
`Patent 7,296,121
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`deficiency of the Petition. See Decision, p. 23. Rather, through reference to the
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`example of FIG. 9 of Koster, the Petition points out Koster’s disclosure of a node
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`that completes a memory transaction after receiving just one response to a probe,
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`thus satisfying claim 12. Inasmuch as the Fig. 9 node (i.e., microprocessor 182)
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`completes its memory transaction after receiving only one response, the Petition
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`adds that said node is “necessarily programmed” to do the same. See Petition, p.
`
`36.
`
`The Decision reveals a further but distinct misapprehension of the Petition’s
`
`application of Koster when criticizing the Petition for its failure to demonstrate that
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`Koster’s microprocessors are programmed to complete memory transactions
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`“before all the responses are in.” See Decision, p. 23. Specifically, this criticism is
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`the result of a misapprehension of the Petition’s application of Koster to the
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`language of claim 12. Turning first to the Petition’s application of Koster, no
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`attempt is made to address whether Koster completes memory transactions “before
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`all responses are in,” nor is this a deficiency of the Petition. Rather, through
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`reference to Fig. 9 of Koster, the Petition points out Koster’s disclosure of a node
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`that completes a memory transaction after receiving just one response to a probe,
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`thus satisfying claim 12. Inasmuch as the Fig. 9 node (i.e., microprocessor 182)
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`completes its memory transaction after receiving only one response, the Petition
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`7
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`IPR2015-00163
`Patent 7,296,121
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`adds that said node is “necessarily programmed” to do the same. See Petition, p.
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`36.
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`The Petition does not address whether Koster’s nodes are programmed to
`
`complete memory transactions “before all responses are in,” because the Petition
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`rightly recognized no such limitation in claim 12 when viewed through the prism
`
`of the broadest reasonable interpretation standard. Rather, as implicit from its
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`application of Koster's Fig. 9 implementation to claim 12, the Petition treated that
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`claim consistent with its plain language1 - as merely requiring nodes programmed
`
`to complete a memory transaction after receiving one response to a first probe.
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`Inasmuch as claim 11 recites “after receiving a first number of responses” and
`
`claim 12 merely indicates that the first number is “one,” there exists no basis for
`
`the Decision’s introduction of “before all responses are in,” nor its denial of Koster
`
`for allegedly failing to meet this non-limitation. Rather, the Board’s interpretation
`
`of claim 12 as requiring “before all responses” reveals its misapprehension, since
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`this interpretation introduces a boundary that is left unspecified by the plain claim
`
`language of claims 11/12.
`
`
`1 Section III(C), entitled “Claim Construction under 37 C.F.R. §§ 42.104(b)(3),”
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`submits that “all remaining claims [not specifically construed in the Petition] be
`
`given their plain meaning.” Petition, pp. 4-5.
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`8
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`IPR2015-00163
`Patent 7,296,121
`
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`In attempting to justify its denial of the Koster ground against claim 12, the
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`Decision addresses a partial quote from the Petition, as follows: “We are, therefore,
`
`not persuaded that Petitioner has shown that Koster’s requesting microprocessor is
`
`‘necessarily programmed to complete [its memory] transaction after receiving one
`
`response to the broadcast request for data.’” Decision, p. 23. This point of
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`apparent contention is moot, however, as it is the product of misapprehension
`
`regarding the Petition’s argument as applied to the plain meaning of the claim 12
`
`language of concern. Specifically, in the Petition, the “necessarily programmed”
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`language was offered to describe the actions of microprocessor 182 of Koster in
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`the context of the Fig. 9 exemplary flow, as that particular microprocessor is
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`indeed disclosed as being programmed (i.e., it is necessarily programmed) to
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`complete the particular memory transaction shown in Fig. 9, albeit after receiving
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`one and only one response to the broadcast request for data from the other
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`microprocessors 184, 186 and 188 (, i.e., a single response from microprocessor
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`188 and no responses from microprocessors 184 and 186). Rather, the Petition
`
`offers that Koster discloses a processing node programmed to complete a memory
`
`transaction after receiving one response to a first probe, consistent with the plain
`
`meaning of claim 12.
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`Finally, the Decision offers that “Petitioner does not point us to any
`
`disclosure in Koster that the memory transaction occurs before all the responses
`
`
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`9
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`IPR2015-00163
`Patent 7,296,121
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`are in.” Decision, p. 23. As indicated above, this position assumes that the claim
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`requires the node to be programmed to complete its memory transaction before all
`
`the responses are in, which reflects a misapprehension of the plain meaning
`
`addressed in the Petition. Claim 12 instead simply requires that each of the
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`processing nodes is programmed to complete a memory transaction after receiving
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`one response to a first probe. Where a first probe elicits a response from a single
`
`microprocessor, as in Fig. 9, the microprocessors described by Koster are
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`programmed to complete the corresponding memory transaction after receiving the
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`single response, perfectly consistent with the plain language of the claim. See
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`Petition, p. 36; see also Decision, p. 23 (acknowledging that in the exemplary flow
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`illustrated in Fig. 9, Koster completes a memory transaction after receiving one
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`response). Whether or how Koster programs its microprocessors to handle
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`memory transactions when more than one microprocessor responds to a probe
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`therefore does not undo what Koster sets forth with respect to Fig. 9. Nor does
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`disclosure of additional detail regarding the handling of two or more responses
`
`change the fact that the limitations of claim 12 are fully met by the Fig. 9
`
`disclosure of Koster, as applied in the Petition against the plain meaning of claim
`
`12, whose only temporal requirement is for transactions to be performed after
`
`receipt of the first probe.
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`
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`10
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`IPR2015-00163
`Patent 7,296,121
`
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`Accordingly, the Decision misapprehended the Petition’s application of
`
`Koster to the language of claim 12. Because, for the reasons noted above, the
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`Petition adequately demonstrates how Koster explicitly discloses that “each of the
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`processing nodes is programmed to complete a memory transaction after receiving
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`a first number of responses to a first probe” “and the first number is one,” as
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`required by claim 12, Petitioner respectfully requests the Board reconsider its
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`Decision and institute the Petition’s proposed ground for unpatentability of claim
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`12 based on Koster in the pending inter partes review.
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`VI. Conclusion
`For the foregoing reasons, Petitioners respectfully request rehearing of claim
`
`12 of the ’121 Patent and respectfully request that inter partes review be instituted
`
`Respectfully submitted,
`
`
`/ Roberto J. Devoto /
`
`Roberto Devoto, Reg. No. 55,108
`W. Karl Renner, Reg. No. 41,265
`Attorneys for Petitioner
`
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`on Ground 1 for that claim.
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` .
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`Dated: 5-22-15
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`11
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`IPR2015-00163
`Patent 7,296,121
`
`
`CERTIFICATE OF SERVICE
`
`Pursuant to 37 CFR §§ 42.6(e), the undersigned certifies that on May 22,
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`2015, a complete and entire copy of this Petitioner’s Request for Hearing was
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`provided via email, to the Patent Owner by serving the correspondence address of
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`record as follows:
`
`Jonathan D. Baker
`Farney Daniels PC
`411 Borel Avenue, Suite 350
`San Mateo, CA 94402
`
`Bryan Atkinson
`Farney Daniels PC
`800 S. Austin, Suite 200
`Georgetown, TX 78626
`
`Email: jbaker@farneydaniels.com
`Email: batkinson@farneydaniels.com
`Email: fdlitsupport@farneydaniels.com
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`/Edward G. Faeth/
`
`Edward G. Faeth
`Fish & Richardson P.C.
`3200 RBC Plaza
`60 South Sixth Street
`Minneapolis, MN 55402
`(202) 626-6420
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