Trials@uspto.gov
`Tel: 571-272-7822
`
`Paper 18
`Entered: May 8, 2015
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC.,
`SAMSUNG ELECTRONICS CO. LTD,
`SAMSUNG ELECTRONICS AMERICA, INC., and
`AMAZON.COM, INC.,
`Petitioner,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`
`Case IPR2015-00163
`Patent 7,296,121 B2
`
`
`
`
`
`
`
`
`
`Before JENNIFER S. BISK, NEIL T. POWELL, and
`KERRY BEGLEY, Administrative Patent Judges.
`
`BISK, Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`Tel: 571-272-7822
`
`Paper 18
`Entered: May 8, 2015
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC.,
`SAMSUNG ELECTRONICS CO. LTD,
`SAMSUNG ELECTRONICS AMERICA, INC., and
`AMAZON.COM, INC.,
`Petitioner,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`
`Case IPR2015-00163
`Patent 7,296,121 B2
`
`
`
`
`
`
`
`
`
`Before JENNIFER S. BISK, NEIL T. POWELL, and
`KERRY BEGLEY, Administrative Patent Judges.
`
`BISK, Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`Case IPR2015-00163
`Patent 7,296,121 B2
`
`INTRODUCTION
`
`A. Background
`The parties named above1 (“Petitioner”) filed a Petition requesting an
`inter partes review of claims 1–6, 8–12, and 15–25 (the “challenged
`claims”) of U.S. Patent No. 7,296,121 B2 (Ex. 1001, “the ’121
`patent”). Patent Owner, Memory Integrity, LLC, filed a Preliminary
`Response. Paper 13 (“Prelim. Resp.”).
`We have authority to determine whether to institute an inter partes
`review. 35 U.S.C. § 314(b); 37 C.F.R. § 42.4(a). The standard for
`instituting an inter partes review is set forth in 35 U.S.C. § 314(a), which
`provides that an inter partes review may not be instituted “unless the
`Director determines . . . there is a reasonable likelihood that the petitioner
`would prevail with respect to at least 1 of the claims challenged in the
`petition.”
`After considering the Petition and Preliminary Response, we
`determine that Petitioner has established a reasonable likelihood of
`prevailing in showing the unpatentability of claims 4–6, 11, and 19–24.
`Accordingly, we institute inter partes review of these challenged claims.
`We decline to institute an inter partes review of claims 1–3, 8–10, 12, 15–
`18, and 25.
`
`
`1 The Petition also lists Samsung Telecommunications America, LLC
`(“STA”) as a petitioner. Paper 1 (“Pet.”), 1. After the filing of the Petition,
`however, STA merged with and into Samsung Electronics America, Inc.
`Paper 12. Thus, STA no longer exists as a separate corporate entity. Id.
`
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`B. Related Matters
`The parties indicate that the ’121 patent is the subject of several
`proceedings in the United States District Court for the District of Delaware.
`Pet. 1–2; Paper 11, 1–2. Petitioner also filed three other petitions seeking
`inter partes review of the ’121 patent—IPR2015-00159, IPR2015-00161,
`and IPR2015-00172. In addition, another party filed a petition seeking inter
`partes review of the ’121 patent—IPR2015-00158.
`
`C. The Asserted Grounds of Unpatentability
`Petitioner contends that claims 1–6, 8–12, and 15–25 of the ’121
`patent are unpatentable under 35 U.S.C. §§ 102 and/or 103 based on the
`following grounds (Pet. 3):2
`Ground
`References
`§ 102
`§ 103
`§ 103
`§ 103
`
`Challenged Claims
`1–6, 8, 11, 12, and 16
`9 and 10
`15 and 25
`17–24
`
`Koster3
`Koster and Duato4
`Koster and O’Krafka5
`Koster and Smith6
`
`D. The ’121 Patent
`The ’121 patent relates to accessing data in computer systems that
`include more than one processor. Ex. 1001, 1:23–24. Specifically, the ’121
`patent discusses multiple processor systems with a point-to-point
`architecture—a cluster of individual processors (also referred to as
`processing nodes) that are directly connected to each other through point-to-
`
`2 Petitioner also provides a declaration from Dr. Robert Horst. Ex. 1014.
`3 U.S. Patent No. 7,698,509 B1 (Ex. 1009) (“Koster”).
`4 JOSÉ DUATO ET AL., INTERCONNECTION NETWORKS (1997) (Corrected Ex.
`1007, “Duato”).
`5 U.S. Patent No. 7,315,919 B1 (Ex. 1010) (“O’Krafka”).
`6 MICHAEL JOHN SEBASTIAN SMITH, APPLICATION-SPECIFIC INTEGRATED
`CIRCUITS (1997) (Ex. 1008, “Smith”).
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`point links, each with an associated cache memory. Id. at 4:38–40. To
`increase the number of available processors, multiple clusters may be
`connected. Id. at 4:50–53. Figure 1A is reproduced below.
`
`
`Figure 1A shows an example of a multiple cluster, multiple processor
`system described by the ’121 patent. Id. at 6:10–12. Figure 1A includes
`four processing clusters: 101, 103, 105, and 107, each of which can, in turn,
`include multiple processors. Id. at 6:12–14. The clusters are connected
`through point-to-point links 111a–f. Id. at 6:14–16.
`The ’121 patent explains that cache coherency problems can arise in
`such a system, because it may contain multiple copies of the same data. Id.
`at 1:26–38. For example, if the caches of two different processors have a
`copy of the same data block and both processors “attempt to write new
`values into the data block at the same time,” then the two caches may have
`different data values and the system may be “unable to determine what value
`to write through to system memory.” Id. at 1:37–45. Solutions to cache
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`coherency problems often involve an increase in communication traffic and
`a resulting decrease in efficiency. Id. at 1:23–26, 2:46–48. The ’121 patent
`discloses “techniques . . . for increasing data access efficiency in a multiple
`processor system,” while also addressing cache coherency. Id. at 4:36–38.
`The system disclosed by the ’121 patent includes a probe filtering
`unit. Id. at 2:52–65. A probe is defined as “[a] mechanism for eliciting a
`response from a node to maintain cache coherency in a system.” Id. at 5:45–
`47. As opposed to a traditional approach of broadcasting probes to all
`nodes, the probe filtering unit reduces traffic by intercepting the probes and
`transmitting them only to those nodes that require the information based on
`probe filtering information, i.e., “[a]ny criterion that can be used to reduce
`the number of clusters or nodes probed.” Id. at 2:52–3:5, 14:50–52; see id.
`at 28:29–58, 29:43–46. The probe filtering unit may also accumulate
`responses from those nodes selected to receive the probes and respond to the
`node from which the probe originated. Id. at 3:5–8, 28:59–67, 29:46–51.
`Figure 18 of the ’121 patent is reproduced below.
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`Figure 18 shows a multiple processor system with a probe filtering
`unit. Id. at 3:61–63, 26:58–27:20, Fig. 18. Specifically, Figure 18 depicts
`multiple processor system 1800 with processing nodes 1802a–d
`interconnected by point-to-point communication links 1808a–e. Id. at
`26:58–27:1. System 1800 also includes probe filtering unit 1830 as well as
`I/O switch 1810, one or more Basic I/O systems (“BIOS”) 1804, I/O
`adapters 1816, 1820, and a memory subsystem with memory banks 1806a–d.
`Id. at 3:61–63, 26:58–27:20, Fig. 18.
`
`E. Illustrative Claim
`Claims 1, 16, and 25 of the ’121 patent are independent. Claim 1 is
`illustrative of the claimed subject matter and recites:
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`1. A computer system comprising a plurality of processing
`nodes interconnected by a first point-to-point architecture,
`each processing node having a cache memory associated
`therewith,
`the computer system further comprising a probe filtering unit
`which is operable to receive probes corresponding to memory
`lines from the processing nodes and to transmit the probes only
`to selected ones of the processing nodes with reference to probe
`filtering information representative of states associated with
`selected ones of the cache memories.
`Ex. 1001, 30:65–31:7 (line breaks added).
`
`ANALYSIS
`
`A. Claim Construction
`We interpret claims of an unexpired patent using the broadest
`reasonable construction in light of the specification of the patent in which
`they appear. 37 C.F.R. § 42.100(b); see In re Cuozzo Speed Techs., LLC.,
`778 F.3d 1271, 1281 (Fed. Cir. 2015). We presume a claim term carries its
`“ordinary and customary meaning,” which is “the meaning that the term
`would have to a person of ordinary skill in the art in question” at the time of
`the invention. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir.
`2007) (citation and quotations omitted). This presumption, however, is
`rebutted when the patentee acts as his own lexicographer by giving the term
`a particular meaning in the specification with “reasonable clarity,
`deliberateness, and precision.” In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir.
`1994).
`Petitioner and Patent Owner each proffer proposed constructions of
`several claim terms. For purposes of this decision, we determine that only
`the claim terms discussed below require express construction.
`
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`1. “probe”
`Petitioner points out that the ’121 patent defines the term “probe,”
`
`which is recited in challenged claims 1–3, 6, 8–12, 15–17, 19, 20, 22, 24,
`and 25, and argues that the term should be construed as “a mechanism that
`elicits a response from a node to maintain cache coherency in a system.”
`Pet. 7–8. Patent Owner does not address Petitioner’s assertions.
`We note that Petitioner’s proposed construction slightly differs from
`the definition of “probe” in the ’121 patent, which uses the language “[a]
`mechanism for eliciting a response,” as opposed to “[a] mechanism that
`elicits a response” in Petitioner’s proposed construction. Id. (emphases
`added); see Ex. 1001, 5:45–47. Petitioner has provided no reason for the
`difference in wording. Therefore, for purposes of this decision, we adopt as
`the broadest reasonable construction of “probe” the express definition of the
`term in the ’121 patent: “[a] mechanism for eliciting a response from a node
`to maintain cache coherency in a system.” Ex. 1001, 5:45–47.
`
`2. “probe filtering information”
`Petitioner argues that the ’121 patent expressly defines “probe
`
`filtering information,” as recited in challenged claims 1, 3, 6, 16, and 25.
`Pet. 8–9. Patent Owner does not respond to this argument. We agree that
`the ’121 patent defines the term “probe filter information.” Ex. 1001,
`14:50–52. For purposes of this decision, we adopt this definition as the
`broadest reasonable construction of the claim term “probe filtering
`information”: “[a]ny criterion that can be used to reduce the number of
`clusters or nodes probed.” Id.
`
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`3. “states associated with selected ones of the cache memories”
`Claims 1, 16, and 25 recite “probe filtering information”
`“representative of states associated with selected ones of the cache
`memories.” The parties agree that the ’121 patent does not explicitly define
`“states associated with selected ones of the cache memories.” Pet. 9; Prelim.
`Resp. 11. Each party proposes a construction of the term. Pet. 9–10; Prelim.
`Resp. 11–22. Petitioner’s proposal is that the term is “broad enough to
`encompass ‘any modes or conditions of selected ones of the cache
`memories.’” Pet. 10. Patent Owner’s proposal is that the term means
`“cache coherence protocol states associated with data blocks stored in
`selected ones of the cache memories” where a “cache coherence protocol
`state” means “the current state of a data block in a protocol used to maintain
`the coherency of caches, in which a data block can only be in one current
`state at a time, and in which the current state can transition to a different
`state upon one or more triggering events or conditions.” Prelim. Resp. 11–
`12. At this preliminary stage of this proceeding, for the reasons discussed
`below, we are not persuaded that either party’s proposal accurately
`represents the broadest reasonable construction of the term “states associated
`with selected ones of the cache memories.” For purposes of this decision,
`we do not adopt a construction of the term and instead address aspects of its
`scope.
`Petitioner explains that this term should be construed broadly because
`“the ’121 patent fails to limit the recited ‘states’ to a specific type of state
`nor even to a particular group of states, such as standard coherence protocol
`states.” Pet. 9 (citing Ex. 1001, 14:30–36). Petitioner points to a dictionary
`definition of the word “state” as “‘mode or condition of being.’” Id. (citing
`
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`Ex. 1015, 1145). Petitioner argues “state” is exemplified by presence, which
`is defined in the same dictionary as “‘the fact or condition of being
`present.’” Id. (citing Ex. 1015, 919) (emphasis omitted). According to
`Petitioner, the ’121 patent uses the word “state” in a manner consistent with
`this meaning and encompasses the condition of being present by describing
`that a “directory of shared cache states . . . indicates where particular
`memory lines are cached within the cluster.” Id. (quoting Ex. 1001, 28:29–
`34).
`
`Patent Owner disagrees. Specifically, Patent Owner argues that
`“under Petitioner’s construction, the mode or condition need not have any
`relation to cache coherency or even what is stored in the selected ones of the
`cache memories.” Prelim. Resp. 11. To the extent Petitioner’s construction
`is broad enough to include “states” that are not in any way related to what is
`stored in cache memory, we agree with Patent Owner that this construction
`is unreasonable. The words in the limitation “states associated with selected
`ones of the cache memories,” especially when read in the context of the
`claims, plainly link the “states” to the “cache memories.” The claims, in
`fact, use the term “representative of states associated with selected ones of
`the cache memory” to modify “probe filtering information.” Ex. 1001,
`31:5–7, 32:14–15, 32:52–55 (emphasis added). Based on the ultimate
`function of the probe filtering information—reducing the number of clusters
`or nodes probed when requesting contents of cache memory (see id. at
`14:50–52)—we are persuaded that this language effectively relates the
`recited “states” not just to any aspect of the cache memory, but to the
`contents of that memory.
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`On the other hand, we are not persuaded that the ’121 patent supports
`a construction as narrow as that proposed by Patent Owner. For example,
`Patent Owner asserts that “states” refers solely to cache coherence protocol
`states. Prelim. Resp. 12–15. Patent Owner bases this assertion on two
`examples of potential states given in the ’121 patent: “the four states of
`modified, owned, shared, and invalid” and “the five states of modified,
`exclusive, owned, shared, and invalid.” Id. at 12–13 (quoting Ex. 1001,
`14:30–36). According to Patent Owner, these examples “reinforce[] that the
`relevant states are cache coherence protocol states (although not limited to
`any particular cache coherence protocol’s set of states).” Id. at 13. Patent
`Owner also points to Figures 7 and 8, which show similar states in diagram
`form. Id. The ’121 patent, however, sets these examples within broad
`language stating that “particular implementations may use a different set of
`states” and “[t]he techniques of the present invention can be used with a
`variety of different possible memory line states.” Ex. 1001, 14:30–36. We
`are, thus, not persuaded that these examples limit the broadest reasonable
`construction of the term “states” to cache coherence protocol states, as
`asserted by Patent Owner.
`In addition, because we are not persuaded that the term “states” is
`limited to cache coherence protocol states, we are not persuaded by Patent
`Owner’s further limitations to the term “states associated with selected ones
`of the cache memories” based on aspects of cache coherence protocol states.
`See Prelim. Resp. 15–22.
`Moreover, given the usage of “states” in the specification of the
`’121 patent as well as the dictionary definition of “state” cited by Petitioner,
`we are persuaded, on this record, that “states associated with selected ones
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`of the cache memories” is broad enough to include the condition of
`presence. See Pet. 9; Ex. 1001, 14:30–36, 28:29–34; Ex. 1015, 919, 1145.
`This conclusion is further supported by other extrinsic evidence, particularly
`the definition of “state” in MICROSOFT COMPUTER DICTIONARY: “[t]he
`condition at a particular time of any of numerous elements of computing—a
`device, a communications channel, a network station, a program, a bit, or
`other element—used to report on or to control computer operations.”
`Ex. 3001 (MICROSOFT COMPUTER DICTIONARY (5th ed. 2002)), 497–98.
`At this preliminary stage of this proceeding, we decline to adopt either
`party’s proposed construction of the term “states associated with selected
`ones of the cache memories.” Instead, for purposes of this decision, we are
`persuaded only that, on this record, the term is not limited to cache
`coherence protocol states and is broad enough to include the condition of
`presence—i.e., what is stored in cache memory. See, e.g., Ex. 1001, 28:29–
`34 (“The PFU accepts the probe and looks up the address in its directory of
`shared cache states . . . [that] indicates where particular memory lines are
`cached within the cluster.”).
`
`4. “cache coherence controller”
`Petitioner also correctly contends that the ’121 patent defines “cache
`coherence controller,” as recited in claim 3. Pet. 11–12. Patent Owner does
`not address this assertion. For purposes of our construction, below, of
`“probe filtering unit,” we adopt the express definition of the ’121 patent for
`this term. Specifically, we adopt, as the broadest reasonable construction of
`“cache coherence controller”: “[a]ny mechanism or apparatus that can be
`used to provide communication between multiple processor clusters while
`maintaining cache coherence.” Ex. 1001, 7:2–5.
`
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`5. “probe filtering unit”
`Neither party discusses the term “probe filtering unit” in the claim
`construction section of its brief. See Pet. 4–14; Prelim. Resp. 10–22. This
`term, however, requires construction to resolve an issue in dispute. In
`arguing that Koster is prior art to the challenged claims, Petitioner asserts
`that the term “probe filtering unit” is defined by Figures 17 to 22 of the ’121
`patent and the corresponding description. Pet. 20–21 (citing Ex. 1001,
`25:19–57). Further, Petitioner argues that a “probe filtering unit” is distinct
`from anything included in embodiments other than those related to Figures
`17 through 22. Id. Petitioner particularly points to language in the ’121
`patent stating that the embodiments of Figures 17 through 22 “adapt” the
`techniques used in earlier embodiments. Id. at 20. Because the ’121 patent
`goes on to state that “[s]uch techniques are referred to herein as local probe
`filtering . . . the filtering of probes within a cluster” (Ex. 1001, 25:52–53,
`26:36–39), Petitioner appears to argue that the construction of “probe
`filtering unit” excludes any filtering between clusters and instead only
`includes filtering within clusters.
`Patent Owner implicitly construes “probe filtering unit” more broadly,
`pointing to other portions of the ’121 patent that describe “probe filtering”
`and “probe filter information” as evidence that a “probe filtering unit” may
`be construed to include inter-cluster probe filtering as well as intra-cluster
`filtering. Prelim. Resp. 25–26. For example, Patent Owner points to the
`description of Figure 11 as “a process flow diagram showing one example of
`a technique for handling requests at a home cache coherence controller . . .
`[that uses] probe filter information at 1113 to determine whether the number
`of probes at various clusters in the system can be reduced.” Id. at 26.
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`For purposes of this decision, we determine that the broadest
`reasonable construction of the term “probe filtering unit” includes filtering
`both within and between clusters. Although the ’121 patent has some
`discussion of the meaning of the term, it does not contain a single, express
`definition of “probe filtering unit.” For example, the ’121 patent states that
`the filtering of probes within a cluster may be implemented in systems
`having multiple clusters as well as those having a single cluster. Ex. 1001,
`26:36–39. In systems with multiple clusters, probe filtering may be
`implemented in a cache coherence controller, which facilitates
`communication between clusters. Id. at 26:39–42. Within a single cluster,
`“these functionalities may be implemented in a device which will be referred
`to herein as a probe filtering unit (PFU) which may occupy a similar location
`in the cluster as the cache coherence controller, and may include some
`subset of the other functionalities of the cache coherence controller.” Id. at
`26:42–47. This language suggests that a probe filtering unit is a device used
`within a single cluster in place of a cache coherence controller.
`Later, however, the ’121 patent states that “[a]ccording to
`embodiments having multiple clusters of processors, PFU 1830 may
`comprise a cache coherence controller which facilitates communication with
`remote clusters as described above.” Id. at 27:5–8. This language suggests
`that a probe filtering unit may also be used in systems with multiple clusters
`and may, in fact, include a cache coherence controller, which as construed
`above, provides filtering between multiple processor clusters. Moreover, the
`’121 patent expressly states that “the use of the term ‘probe filtering unit’ or
`‘PFU’ in the following discussion [relating to intra-cluster communication]
`is not intended to be limiting or exclusive.” Id. at 26:52–55.
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`The ’121 patent’s language stating that a probe filtering unit may
`include a cache coherence controller that filters between clusters, combined
`with the express disavowal of limitations on the term, leads us to conclude
`that the broadest reasonable construction of the term “probe filtering unit”
`includes filtering both within and between clusters.
`
`B. The Effective Filing Date of the Challenged Claims
`Patent Owner argues that claims 1–3, 8, 15–18, and 25 are entitled to
`a priority date of November 4, 2002 and therefore Petitioner has not shown
`sufficiently that Koster—with a filing date of July 13, 2004—qualifies as
`prior art against these claims. Prelim. Resp. 23–29. Patent Owner “does not
`currently contend that claims 4–6, 9–12, and 19–24 are entitled [to the
`November 4, 2002, priority date].” Id. at 28 n.4.
`Petitioner proffers Koster as § 102(e) art. Pet. 4. There is no dispute
`that Koster’s filing date of July 13, 2004, is before the filing date of U.S.
`Application No. 10/966,161 (“the ’161 application”)—October 15, 2004—
`which issued as the ’121 patent. Patent Owner, however, asserts that claims
`1–3, 8, 15–18, and 25 are entitled to the filing date of U.S. Application No.
`10/288,347 (“the ’347 application”)—November 4, 2002—of which the
`’161 application was a continuation-in-part. Prelim. Resp. 23–29. Petitioner
`disagrees. Pet. 19–23. Because Koster was filed after the ’347 application,
`it is prior art only if Petitioner is correct and the challenged claims of the
`’121 patent are not entitled to the filing date of the ’347 application.
`As Petitioner points out, the ’347 application is shorter than the ’161
`application. Pet. 19. Specifically, although the ’347 and ’161 applications
`share Figures 1 through 14, the ’161 application adds new Figures 15
`through 22 along with supporting description. Id. The relevant issue,
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`however, is whether the ’347 application contains written description that
`supports all the limitations of the challenged claims. See Tech. Licensing
`Corp. v. Videotek, Inc., 545 F.3d 1316, 1327 (Fed. Cir. 2008). We
`determine that claims 1–3, 8, 15–18, and 25 are entitled to the filing date of
`the ’347 application.
`Petitioner argues that the term “probe filtering unit,” which is recited
`in each of the challenged independent claims, is not supported by the ’347
`application. Pet. 20–21. As discussed above, when construing the term
`“probe filtering unit,” Petitioner asserts that the term relates only to the
`embodiments in Figures 17 through 22 and, therefore, includes only intra-
`cluster probe filtering. Id. (citing Ex. 1001, 25:19–57). Patent Owner
`concedes that the ’347 application does not use the term “probe filtering
`unit,” but argues that the specification, nonetheless, provides proper support
`for the term. Prelim. Resp. 27–28.
`Based on the construction of “probe filtering unit” adopted above, we
`are persuaded that the ’347 application “reasonably conveys to those skilled
`in the art that the inventor had possession” of the claimed “probe filtering
`unit.” Ariad Pharms. v. Eli Lilly & Co., 598 F.3d 1336, 1351 (Fed. Cir.
`2010) (en banc). For example, the ’347 application describes “probe filter
`information that can be used to reduce the number of transactions in a
`multiple cluster system.” Ex. 1022, 23:20–24:16, Fig. 8. Similarly, the ’347
`application describes a technique for handling probe requests using a cache
`coherence controller. Id. at 26:7–27:13, Fig. 11. We are persuaded that,
`although the ’347 patent does not use the term “probe filtering unit,” a
`person skilled in the art would have understood that the inventor had
`possession of a technique for probe filtering and a device, or unit, for
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`implementing such technique. See Eiselstein v. Frank, 52 F.3d 1035, 1038
`(Fed. Cir. 1995) (“In order to determine whether a prior application meets
`the ‘written description’ requirement with respect to later-filed claims, the
`prior application need not describe the claimed subject matter in exactly the
`same terms as used in the claims.”).
`Further, we are persuaded that the ’347 application provides proper
`support for all the other limitations of independent claims 1, 16, and 25 (see
`Prelim. Resp. 24–27 (citing Ex. 1022, 3:3–4, 10:4–11:19, 13:29–31, 15:10–
`13, 21:31–24:16, 26:7–27:14, 34:9–10, Figs. 1A, 1B, 2, 3, 4, 7, 8, 11)) and
`the additional limitations recited by dependent claims 2, 3, 8, 15, 17, and 18
`(see Prelim. Resp. 28–29 (citing Ex. 1022, 10:24–30, 11:12–19, 15:10–13,
`21:31–23:18, 25:13–26:5, Figs. 2, 7, 10)).
`Consequently, we are not persuaded that Petitioner has sufficiently
`shown that Koster is properly prior art to claims 1–3, 8, 15–18, and 25.
`Petitioner’s challenge to claims 1–3, 8, 15–18, and 25, therefore, fails.
`
`C. Patentability Challenges
`1. Overview of Koster
`Koster discloses a “snooping-based cache-coherence filter for a point-
`to-point connected multiprocessing node.” Ex. 1009, title. In Koster, when
`a microprocessor requests data that is not available in its local cache, it sends
`a request for that data to a snoop filter. Id. at abs. The snoop filter stores a
`copy of the tags of data stored in the local cache memories of each of the
`microprocessors. Id. When the snoop filter receives a request for data, it
`can determine which microprocessors have copies of the requested data and
`relay the data request only to those microprocessors. Id.
`Figure 9 of Koster is reproduced below.
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`Figure 9 shows an exemplary flow of messages in multiprocessing node 180
`with four microprocessors 182, 184, 186, and 188 and snoop filter 192. Id.
`at 6:61–67. Microprocessor 182 requests data by issuing “broadcast A,”
`which is routed to snoop filter 192. Id. at 6:67–7:3. Snoop filter 192 has
`shadow tag memory 194 that stores copies of the tags of data stored in the
`local cache memories of microprocessors 182, 184, 186, and 188. Id. at 7:3–
`6; 6:9–17. Upon receipt of broadcast A, snoop filter 192 determines whether
`any of the other three microprocessors have a copy of the requested data. Id.
`In Figure 9, snoop filter 192 determines that microprocessor 188 has a copy
`of the requested data and forwards broadcast A to microprocessor 188. Id. at
`7:6–10. Next, microprocessor 188 sends “response B (having a copy of the
`requested data)” to snoop filter 192, which, in turn, forwards response B
`back to requesting microprocessor 182. Id. at 7:10–14.
`Koster notes that “[b]y forwarding response B through the snoop filter
`192, the snoop filter 192 is able to update its shadow tag memory 194.” Id.
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`at 7:15–16. Koster, however, also discloses embodiments in which “a
`response from a microprocessor may be routed directly back to a requesting
`microprocessor.” Id. at 7:17–19.
`
`2. Claims 4–6, 11, and 12
`Petitioner asserts that claims 4–6, 11, and 12 are anticipated by
`Koster. Pet. 31–37. Petitioner supports its assertion with testimony from
`Dr. Horst. Ex. 1014 ¶¶ D-2–D-4. Specifically, Petitioner argues that each of
`the four microprocessors 152, 154, 156, and 158 is equivalent to the claimed
`processing node and snoop filter 162 is equivalent to the claimed probe
`filtering unit. Pet. 26–28. Petitioner also argues that Koster discloses probe
`filtering information through the disclosure of the tags stored in shadow tag
`memory 164. Pet. 28.
`
`a. “probe filtering information”
`Patent Owner argues that Koster does not disclose “probe filtering
`information” “representative of states associated with selected ones of the
`cache memories,” as recited by claims 4–6, 11, and 12. Prelim. Resp. 28–
`34. According to Patent Owner, the tags stored in shadow tag memory 164
`do not represent “states associated with selected ones of the cache
`memories” because “Koster’s snoop filter selects the processors to receive
`the forwarded probes based on the tags (rather than based on valid bits or
`any other state information).” Id. at 31. Patent Owner, therefore, argues that
`Koster does not disclose that its tags—or any other contents of the shadow
`tag memory—“represent a cache coherence protocol state” and therefore
`Koster does not anticipate the challenged claims. Id.
`We are not persuaded by this argument. As discussed above, we do
`not agree that the claims are limited to “states” that “represent a cache
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`coherence protocol” as asserted by Patent Owner. Moreover, we are
`persuaded that Koster’s tags indicate where specific data is cached (i.e., the
`presence of data in specific locations), information we have determined, for
`purposes of this decision, to be included in the claimed subject matter.
`
`b. “each of the processing nodes is programmed to complete a
`memory transaction after receiving a first number of
`responses”
`Patent Owner also argues that Koster does not disclose that “each of
`the processing nodes is programmed to complete a memory transaction after
`receiving a first number of responses,” as recited in claims 11 and 12.
`Prelim. Resp. 34–37. Petitioner asserts that this limitation is inherently
`disclosed by Koster. Pet. 34–35. According to Petitioner, Koster discloses
`that when a microprocessor requests data, it receives either (1) a single
`response from the snoop filter indicating that no microprocessors are storing
`that data (Ex. 1009, 6:24–32), or (2) a response from all the microprocessors
`storing a copy of the requested data (id. at 7:10–14). Id. at 35 (citing Ex.
`1014 ¶ D-17). Petitioner adds that the number of microprocessors
`responding to the request is necessarily less than the total number of
`microprocessors because the requesting microprocessor does not respond to
`its own request. Thus, it follows that “a requesting microprocessor must be
`programmed to complete a memory transaction after receiving a first
`number of responses to a first data request, the first number being fewer than
`the number of processing nodes.” Id. at 34.
`Petitioner also points to Figure 9 of Koster, describing an example in
`which the requesting microprocessor receives a single response and
`“necessarily completes its memory transaction based on this single
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`response,” which is fewer than the four microprocessors within the
`multiprocessor. Id. at 35–36 (citing Ex. 1014 ¶ D-18).
`Patent Owner does not dispute that Koster discloses situations in
`which a requesting processing node receives responses from less than all the
`processing nodes.
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