Patent No. 7,296,121
`IPR2015-00161
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC., SAMSUNG
`ELECTRONICS CO. LTD, SAMSUNG ELECTRONICS AMERICA, INC.,
`SAMSUNG TELECOMMUNICATIONS AMERICA, LLC AND
`AMAZON.COM, INC.,
`Petitioners
`
`v.
`
`MEMORY INTEGRITY, LLC
`Patent Owner
`
`U.S. Patent No. 7,296,121
`
`
`
`Inter Partes Review Case No. 2015-00161
`
`
`MEMORY INTEGRITY, LLC’S PATENT OWNER
`PRELIMINARY RESPONSE PURSUANT TO 37 CFR § 42.107(a)
`
`
`
`
`
`
`

`

`Patent No. 7,296,121
`IPR2015-00161
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`TABLE OF CONTENTS
`
`I.
`
`II.
`
`INTRODUCTION ........................................................................................... 1
`
`TECHNOLOGY BACKGROUND ................................................................. 1
`
`III. SUMMARY OF PETITIONERS’ PROPOSED GROUND FOR
`REVIEW .......................................................................................................... 3
`
`IV. THE PENDING PETITIONS FOR INTER PARTES REVIEW OF THE
`’121 PATENT PRESENT REDUNDANT GROUNDS ................................. 3
`
`A. The Five Pending Petitions for Inter Partes Review of the ’121
`Patent Contain Grounds Redundant Across the Pending Petitions ......... 3
`
`V. MEMORY INTEGRITY, LLC’S CLAIM CONSTRUCTIONS ................. 10
`
`A.
`
`B.
`
`“probe filtering unit” (claims 1, 16, 25) ................................................ 11
`
`“states associated with selected ones of the cache memories”
`(claims 1, 16, 25) ................................................................................... 13
`
`1. The claimed “states” refers to cache coherence protocol states ... 14
`
`2. A cache coherence protocol state is the current state of a data
`block in a protocol used to maintain the coherency of caches,
`in which a data block can only be in one current state at a
`time, and in which the current state can transition to a different
`state upon one or more triggering events or conditions ................ 17
`
`3.
`
`“states associated with selected ones of cache memories”
`refers to the cache coherence protocol state(s) of data block(s)
`which are stored in the selected cache memories ......................... 22
`
`VI. THERE IS NO REASONABLE LIKELIHOOD OF PETITIONERS
`PREVAILING AS TO A CHALLENGED CLAIM OF THE ’121
`PATENT ........................................................................................................ 24
`
`A. Petitioners Failed to Demonstrate That Chaiken Anticipates Claims
`1-3, 8, 11, 14-16, 19, 20, 22, and 25 ..................................................... 24
`
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`1.
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`2.
`
`3.
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`4.
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`5.
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`6.
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`Patent No. 7,296,121
`IPR2015-00161
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`Petitioners Fail to Demonstrate That Chaiken Anticipates Any
`Independent Claim Because Chaiken Does Not Disclose
`“Probes” ........................................................................................ 24
`
`Petitioners Fail to Demonstrate That Chaiken Anticipates Any
`Independent Claim Because Chaiken Does Not Disclose a
`Probe Filtering Unit that “Receive[s] Probes” and
`“Transmit[s] the Probes” ............................................................... 26
`
`Petitioners Fail to Demonstrate That Chaiken Anticipates Any
`Independent Claim Because Chaiken Does Not Disclose
`“probe filtering information” “representative of states
`associated with selected ones of the cache memories” ................. 29
`
`a. Mere “presence or absence,” by itself, does not
`constitute a cache coherence protocol state ........................ 30
`
`Petitioners Fail to Demonstrate That Chaiken Anticipates
`Dependent Claim 2 Because Chaiken Does Not Disclose a
`“Probe Filtering Unit… Interconnected with the Plurality of
`Processing Nodes Via the First Point-to-Point Architecture” ...... 33
`
`Petitioners Fail to Demonstrate That Chaiken Anticipates
`Dependent Claim 11 Because Chaiken Does Not Disclose
`That “Each Of The Processing Nodes Is Programmed To
`Complete A Memory Transaction After Receiving A First
`Number Of Responses” ................................................................. 35
`
`Petitioners Fail to Demonstrate That Chaiken Anticipates
`Dependent Claim 14 Because Chaiken Does Not Disclose a
`“Probe Filtering Unit… operable to modify the probes such
`that the selected processing nodes transmit responses to the
`probes to the probe filtering unit” ................................................. 38
`
`B. Petitioners Failed To Demonstrate That Claim 9 Is Obvious Over
`Chaiken In View of Duato ..................................................................... 39
`
`1. The Petition Fails To Demonstrate That The Combination Of
`Chaiken And Duato Teaches The “Routing Table” As Recited
`in Dependent Claim 9.................................................................... 39
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`Petitioners Failed To Show That A Person Of Ordinary Skill
`In The Art Would Have Been Motivated To Combine The
`Teachings Of Chaiken And Duato ................................................ 40
`
`2.
`
`C. Petitioners Failed To Demonstrate That Claims 17-24 Are Obvious
`Over Chaiken In View of Smith ............................................................ 43
`
`VII. CONCLUSION ................................................................................................ 43
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`Patent No. 7,296,121
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`EXHIBIT LIST
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`Exhibit No.
`Memory Integrity-2001
`
`Memory Integrity-2002
`
`Memory Integrity-2003
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`Memory Integrity-2004
`
`Memory Integrity-2005
`
`Description
`Plaintiff Memory Integrity, LLC’s Initial Identification
`of Asserted Claims And Accused Products, served on
`Petitioners in Memory Integrity LLC v. Amazon.com
`Inc., et al., Nos. 1:13-cv-01795, -01796, -01802,
`-01808 (D. Del. served Oct. 13, 2014)
`Excerpts from D. E. Culler, J. P. Singh, and A. Gupta
`PARALLEL COMPUTER ARCHITECTURE, pp. 279-280
`(1999)
`Sorin et al. , “Specifying and Verifying a Broadcast and
`a Multicast Snooping Cache Coherence Protocol,”
`IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED
`SYSTEMS, Vol. 13, No. 6, pp. 1-23(June 2002)
`Excerpts from Merriam-Webster’s Collegiate
`Dictionary (10th ed. 1999)
`
`Excerpts from David A. Patterson, et al., COMPUTER
`ORGANIZATION AND DESIGN (3d ed. 2005)
`
`
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`TABLE OF AUTHORITIES
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`Patent No. 7,296,121
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` Page(s)
`
`Cases
`Canon Inc. v. Intellectual Ventures I LLC,
`Case No. IPR2014-00535 (PTAB Sep. 24, 2014) ................................................ 5
`
`Canon Inc. v. Intellectual Ventures I LLC,
`Case No. IPR2014-00536 (PTAB Nov. 5, 2014) ................................................. 5
`
`In re Cuozzo Speed Technologies, LLC,
`No. 2014-1301 (Fed. Cir. Feb. 4, 2015) ............................................................. 10
`
`Dominion Dealer Solutions, LLC v. AutoAlert, Inc.,
`Case No. IPR2013-00222 (PTAB Aug. 12, 2013) ............................................. 42
`
`Illumina, Inc. v. Trustees of Columbia Univ.,
`Case No. IPR2012-00006 (PTAB May 10, 2013) ........................................ 3, 4, 8
`
`Gracenote, Inc. v. Iceberg Industries LLC,
`Case No. IPR2013-00551 (PTAB Feb. 28, 2014) .............................................. 11
`
`Ex parte Levy,
`17 USPQ2d 1461 (Bd. Pat. App. & Inter. 1990) ................................................ 37
`
`Microsoft Corporation v. Surfcast, Inc.,
`Case No. IPR2013-00292 (PTAB Nov. 19, 2013) ............................................... 5
`
`Oracle Corporation v. Clouding IP, LLC,
`Case No. IPR2013-0088 (PTAB June 13, 2013) .............................................. 4, 8
`
`Philips v. AWH Corp.,
`415 F.3d 1303(Fed. Cir. 2005) ........................................................................... 10
`
`Therasense, Inc. v. Becton, Dickinson & Co.,
`593 F.3d 1325 (Fed. Cir. 2010) .................................................................... 36, 41
`
`Statutes
`
`35 U.S.C. § 312(a)(3)(A) & (a)(5) ........................................................................... 39
`v
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`Rules
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`Patent No. 7,296,121
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`Fed. R. Evid. 1002 ................................................................................................... 40
`
`Other Authorities
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`32 C.F.R. § 42.107(a) ............................................................................................... 10
`
`37 C.F.R. § 42.1(b) .................................................................................................... 6
`
`37 C.F.R. § 42.22(a)(2) ............................................................................................ 11
`
`37 C.F.R. § 42.62 ..................................................................................................... 40
`
`37 C.F.R. § 42.65 ............................................................................................... 29, 39
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`37 C.F.R. § 42.104(b)(3) .......................................................................................... 11
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`I. INTRODUCTION
`The Board should deny the present request for inter partes review of U.S.
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`Patent No. 7,296,121
`IPR2015-00161
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`Patent No. 7,296,121 (“the ’121 patent”) for several reasons. First, the Petition’s
`
`grounds are redundant of those of Petitioners’ other petitions. Second, the
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`Petition’s invalidity grounds rely upon several incorrect claim constructions and
`
`inadequate inherency theories. As explained below, the Petitioners fail to show
`
`that the properly construed claims are anticipated. Third, the Petition relies on
`
`obviousness combinations that fail to teach all limitations of the claims and that
`
`lack a proper motivation to combine the references. For at least these reasons, as
`
`well as others expressed more fully below, the Petitioners have failed to
`
`demonstrate that there is a reasonable likelihood that they will prevail with respect
`
`to at least one of the claims challenged in the Petition. Accordingly, the Board
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`should deny the Petition.
`
`II. TECHNOLOGY BACKGROUND
`The technology of the ’121 patent generally relates to maintaining the
`
`coherency, or consistency, between copies of information stored in caches of a
`
`multiple processor computer system. Ex. 1001 at 1:22-34. Processors often use
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`small cache memories that the processor is able to read and write to much faster
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`than main memory. Id. at 1:26-44. Because each processor has a cache memory,
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`multiple copies of the same data can reside in multiple cache memories. Id. at
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`1:35-45. A problem arises when a processor attempts to change the data in the
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`cache memory of the first processor while at the same time another processor also
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`attempts to change the value of the same data located in another cache memory
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`because different values for the same data may result. Id. Cache coherency
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`generally relates to techniques that maintain the consistency of the data stored in
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`the processors’ cache memories. Id.
`
`In order to maintain consistency across the same data stored in more than
`
`one cache memory, messages can be sent between the cache memories when
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`information in the cache changes. However, such messages can result in
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`significant traffic. The ’121 patent is directed at maintaining cache coherency
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`while reducing the number of messages that need to be sent. Id. at 2:46-52. A
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`probe filtering unit is connected to the various processing nodes and is configured
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`to receive probes from the nodes. Id. at 2:52-56. The probe filtering unit uses
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`information relating to the state of the cache memories in order to determine which
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`nodes should receive these messages. Id. at 2:52-3:5. The ‘121 Patent thereby
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`discloses a system that maintains coherency between the various cache memories
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`while also reducing the number of messages that need to be transmitted. Id. 
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`2
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`III. SUMMARY OF PETITIONERS’ PROPOSED
`GROUND FOR REVIEW
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`The Petition proposes the rejection of the challenged claims on the following
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`grounds:
`
`1.
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`Claims 1-6, 8, 11, 14-16, 19, 20, 22, and 25: Anticipated by David
`
`Chaiken, et al., “Directory-Based Cache Coherence in Large-Scale
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`Multiprocessors,” Computer vol. 24, issue 9 (June 1990) (“Chaiken”);
`
`2.
`
`Claim 9: Obvious over Chaiken in view of Jose Duato et al.,
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`INTERCONNECTION NETWORKS – AN ENGINEERING APPROACH (1997)
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`(“Duato”);
`
`3.
`
`Claims 17-24: Obvious over Chaiken in view of Michael John
`
`Sebastian Smith, APPLICATION-SPECIFIC INTEGRATED CIRCUITS (1997)
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`(“Smith”).
`
`IV. THE PENDING PETITIONS FOR INTER PARTES REVIEW
`OF THE ’121 PATENT PRESENT REDUNDANT GROUNDS
`A. The Five Pending Petitions for Inter Partes Review of the ’121 Patent
`Contain Grounds Redundant Across the Pending Petitions
`
`The Board has made clear that in order to ensure “the just, speedy, and
`
`inexpensive resolution of every proceeding,” it will not institute inter partes review
`
`proceedings on cumulative or redundant grounds. Illumina, Inc. v. Trustees of
`
`Columbia Univ., IPR2012-00006, Paper 41, at 11-12 (PTAB May 10, 2013). Thus,
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`the Board has instructed parties that it will not “authorize inter partes review on
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`certain unpatentability challenges . . . [where] the challenges appeared to rely on
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`the same prior art facts as other challenges for which inter partes review had been
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`authorized.” Id. “In other words, considering multiple rejections for the same
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`unpatentability issue would unnecessarily consume the time and resources of all
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`parties involved.” Id. Thus, to avoid dismissal of a proposed ground of
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`unpatentability, a petitioner must “provide a meaningful distinction between the
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`different, redundant rejections.” Id. Where multiple references have been cited
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`for the same facts, it is not enough for a petitioner to argue that the cited references
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`are not identical, or to “speculate[] that in certain publications an element may be
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`more clearly set forth in one publication rather than another.” Id. Rather, a
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`petitioner must adequately explain the difference between the references and “how
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`this difference would impact the unpatentability challenge.” Id. This includes
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`“articulat[ing] a meaningful distinction in terms of relative strengths and
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`weaknesses with respect to application of the prior art disclosures to one or more
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`claim limitations,” as well as “why [one reference] is more preferred for satisfying
`
`some elements, while [another reference] is more preferred for satisfying some
`
`other elements.” Oracle Corporation v. Clouding IP, LLC, IPR2013-0088, Paper
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`13, at 5 (PTAB June 13, 2013).
`
`Moreover, this Board’s rules against redundant and cumulative grounds
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`cannot be avoided by filing multiple petitions against the same patent, as
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`Petitioners have done. Where a petitioner files “multiple challenges to” the claims
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`of the same patent “across separate petitions,” and “does not address the
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`duplicative nature of its arguments across Petitions,” the petitions shall be
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`“considered together” by the Board. Canon Inc. v. Intellectual Ventures I LLC,
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`IPR2014-00535, Paper 9, at 19 (PTAB Sep. 24, 2014). “Petitioner’s separate fee
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`payments, [] did not assure them that three separate trials would be instituted.”
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`Canon Inc. v. Intellectual Ventures I LLC, IPR2014-00536, Paper 11, at 4 (PTAB
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`Nov. 5, 2014). Thus, when presented with multiple petitions with redundant
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`challenges to the same claims of the same patent, the Board may elect to only
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`consider one petition. See id. Alternatively, the Board may elect to eliminate
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`redundancies across the petitions and consolidate the remainder of the petitions “to
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`administer the proceedings more efficiently.” Microsoft Corporation v. Surfcast,
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`Inc., IPR2013-00292, Paper 15, at 2 (PTAB Nov. 19, 2013).
`
`Notwithstanding this Board’s clear directive against submitting cumulative
`
`and redundant grounds, the present petition is one of four petitions for inter partes
`
`review simultaneously filed by the same Petitioners, all challenging the ’121
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`Patent: IPR2015-00159, IPR2015-00161, IPR2015-00163, and IPR2015-00172.
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`Pet. at 2. Two of these petitions, the ’159 and ’172 Petitions, utilize the maximum
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`sixty pages permitted for a petition for review, while the other two petitions nearly
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`Patent No. 7,296,121
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`reach that maximum with fifty-six pages each. Together, Petitioners’ four petitions
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`present sixteen grounds for review, involving ten distinct asserted prior art
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`references in two-hundred and thirty-two pages of briefing, as well as over one-
`
`thousand, seven-hundred pages of exhibits, including a one-hundred and twenty-
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`three page expert declaration, Ex. 1014. Additionally, also pending before the
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`Board, is IPR2015-00158, another challenge to the ’121 Patent, filed by parties that
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`are co-defendants to the Petitioners in pending litigations in District Court. The
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`’158 Petition shares one primary prior art reference with the ’163 Petition, but the
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`’158 Petition presents seven grounds for review, as well an additional four distinct
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`alleged prior art references and an additional fifty-nine pages of briefing and claim
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`charts and an additional sixteen pages of expert declaration. Plainly, the pending
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`petitions jeopardize this Board’s goal to “secure the just, speedy, and inexpensive
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`resolution of every proceeding.” 37 C.F.R. § 42.1(b).
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`Additionally, the pending petitions challenging the ’121 Patent present
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`grossly redundant and cumulative grounds for review, as demonstrated by this
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`chart showing the number of grounds asserted against each claim of the ’121
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`Patent for each of the pending petitions.
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`Patent No. 7,296,121
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`Claim #
`\ Pet. # 1
`’158 Pet. 2 2 2 0 0 0 0 2 0 0 2 2 0 2 4 2 2 2 2 2 2 2 2 2 4
`’159 Pet. 1 1 1 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
`’161 Pet. 1 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 1 1 2 2 1 2 1 1 1
`’163 Pet. 1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1
`’172 Pet. 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 1 1 1 2 2 1 2 1 1 0
`Total 6 6 6 2 2 2 1 6 3 1 6 5 1 4 7 6 6 6 8 8 6 8 6 6 7
`
`25
`24
`23
`22
`21
`20
`19
`18
`17
`16
`15
`14
`13
`12
`11
`10
`9
`8
`7
`6
`5
`4
`3
`2
`
`
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`In total, the pending petitions challenging the ’121 Patent ask this Board to
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`make one-hundred and twenty-five determinations of whether a particular ground
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`necessitates cancellation of a particular claim, an average of five grounds per
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`claim. The grounds for review are redundant and cumulative both within
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`individual petitions, and across the petitions.
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`Petitioners argue that the four petitions filed by them are not redundant
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`because they “presented only those grounds necessary to sufficiently demonstrate
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`that each claim of the ’121 is not patentable, having demonstrated how various
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`teachings address the claims divergently.” IPR2015-00159 Pet. at 59. This is
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`plainly false. Indeed, none of the pending petitions even attempts to describe the
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`substance of any of the other pending petitions to compare the different grounds
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`and prior art asserted between them. Moreover, for the claims with redundant
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`grounds within a single petition, e.g., claims 19, 20, and 22 in the ’161 and ’172
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`Petitions, Petitioners present no explanation for that redundancy. Thus, Petitioners
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`fall far short of their burden of “provid[ing] a meaningful distinction between the
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`different, redundant rejections.” Illumina, IPR2012-00006, Paper 41, at 11-12.
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`Petitioners also argue that “[t]he petition including rejections based on
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`Chaiken provides the most direct disclosure of any of the petitions of the features
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`recited in claim 14” However, this is inadequate. Petitioners do not “articulate a
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`meaningful distinction in terms of relative strengths and weaknesses with respect
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`to application of the prior art disclosures to one or more claim limitations,” nor do
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`they explain “why [one reference] is more preferred for satisfying some elements,
`
`while [another reference] is more preferred for satisfying some other elements.”
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`Oracle, IPR2013-0088, paper 13, at 5 (June 13, 2013).
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`Petitioners also argue that “Stanford DASH . . . is the only petition that
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`includes a rejection of claims 4-6 based on prior art that cannot be antedated
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`through priority or swearing behind,” that “Pong is the only petition that includes a
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`rejection of claim 13,” and that “Stanford DASH is the only petition that includes a
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`rejection of claim 7.” IPR2015-00159 Pet. at 59. However, this reflects that
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`Petitioners have attempted to introduce additional disputed claims in an attempt to
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`create the false perspective of meaningful non-redundancy between the petitions.
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`Indeed, each of the pending petitions arises out of patent infringement litigations
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`brought by Patent Owner in District Court. In those cases, prior to the filing of any
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`of the present petitions for inter partes review, Patent Owner served an “Initial
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`Identification of Asserted Claims and Accused Products” on each of the
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`defendants, including each of the Petitioners, which identified claims 1-3, 8, 11-12,
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`and 14-25 of the ’121 Patent as being asserted. Ex. 2001. It is telling that none of
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`the claims that Petitioners identify as being unique to a particular petition were
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`listed in the Initial Identification of Asserted Claims served in the litigations.
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`Thus, Petitioners demonstrably are using additional claims as a tactic to attempt to
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`convince this Board to shoe-horn multiple redundant grounds on the other claims
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`into the IPR proceedings. The Board should not support such tactics.
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`Indeed, even if any of Petitioners’ arguments as to non-redundancy were a
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`legitimate excuse for Petitioners’ grossly redundant and excessive filings, they
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`would only counsel, at most, permitting institution as to those specific identified
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`claims on those specific allegedly non-redundant grounds. They are no basis for
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`instituting all petitions on all grounds, as Petitioners request.
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`Finally, as set forth in Patent Owner’s preliminary response to each petition,
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`Patent Owner believes that none of the grounds of unpatentability presented by
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`Petitioners should be instituted on any claim. However, to the extent that the
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`Board determines that some of the grounds presented by Petitioners should be
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`instituted, and is seeking to identify a reasonable basis for choosing among the
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`various petitions, Patent Owner submits that that the goal of “the just, speedy, and
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`inexpensive resolution of every proceeding” will best be served by instituting on
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`the grounds submitted in the ’163 Petition, as that petition shares a primary prior
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`art reference and similar grounds with those presented in the ’158 Petition, filed by
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`Petitioners’ co-defendants.
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`V. MEMORY INTEGRITY, LLC’S CLAIM CONSTRUCTIONS
`Because this preliminary response “is limited to setting forth the reasons
`
`why no inter partes review should be instituted,” 32 C.F.R. § 42.107(a), Memory
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`Integrity does not at this time propose a construction for each term. However, the
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`following terms are either manifestly incorrectly construed by Petitioners, or are
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`wholly ignored by Petitioners. Memory Integrity reserves the right to assert any
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`construction of any term in any Patent Owner’s response, or in any subsequent
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`filing in this proceeding, or in any other proceeding.1
`
`
`1
`Patent Owner acknowledges that the PTAB has determined that the broadest
`
`reasonable interpretation standard is the appropriate standard for construing claims
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`of an unexpired patent in an IPR proceeding, and that a panel of the Federal Circuit
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`has recently affirmed that holding. See In re Cuozzo Speed Technologies, LLC,
`
`No. 2014-1301 (Fed. Cir. Feb. 4, 2015). Nonetheless, Patent Owner contends that
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`the claims should be construed in accordance the same standard used by the district
`
`courts as articulated by the Federal Circuit in Philips v. AWH Corp., 415 F.3d
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`A.
`
`“probe filtering unit” (claims 1, 16, 25)
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`Despite the fact that “probe filtering unit” is recited in the body of every
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`independent claim of the ’121 Patent, despite the fact that Petitioners admit that the
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`“probe filtering unit” is the “focus” of the claims (Pet. at 18), and despite the fact
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`that Petitioners rely on the “probe filtering unit” to argue that the ’121 Patent is not
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`entitled to the priority of its earlier application (Pet. at 4 n.1), Petitioners make no
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`effort to construe the term. Rather, the Petition merely contains fleeting, cursory
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`mentions of the “probe filtering unit” limitation which fail to substantively address
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`the construction and application of the meaning of the term in the claims. See Pet.
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`at 4 n.1, 18, 23, 25-26. This is, in and of itself, sufficient to deny the petition in its
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`entirety. See 37 C.F.R. § 42.104(b)(3) (“the petition must set forth . . . [h]ow the
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`challenged claim is to be construed.”); Gracenote, Inc. v. Iceberg Industries LLC,
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`IPR2013-00551, Paper 6, at 38 (PTAB Feb. 28, 2014) (denying petition for failure
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`to comply with 37 C.F.R. § 42.104(b)(3)); see also 37 C.F.R. § 42.22(a)(2).
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`If Petitioners’ failure to substantively address this limitation is not
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`1303(Fed. Cir. 2005), and Patent Owner explicitly preserves this issue in the event
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`that the Federal Circuit takes this issue en banc or there is some other change in the
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`governing law. Patent Owner maintains that its proposed constructions are correct
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`under either standard.
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`dispositive, Memory Integrity submits that the proper construction of a probe
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`filtering unit requires, at least, “an apparatus operable to filter probes within a
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`single cluster of processors.” For example, the ’121 Patent describes the probe
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`filtering unit, stating:
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`The filtering of probes within a cluster, i.e., local probe filtering,
`may be implemented in systems . . . having a single cluster of
`processors. . . . . In [that case], these functionalities may be
`implemented in a device which will be referred to herein as a
`probe filtering unit (PFU). It should be understood that the use of
`the term “probe filtering unit” or “PFU” in the following discussion is
`not intended to be limiting or exclusive. Rather, any device or object
`operable to perform the described functionalities . . . is within the
`scope of the invention.
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`Ex. 1001 at 26:36-57; see also Ex. 1001 at 26:58-27:4 (“FIG. 18 is a diagrammatic
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`representation of a multiple processor system 1800 in which embodiments of the
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`invention relating to the filtering of probes within a single cluster of processors
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`may be practiced. System 1800 [includes] probe filtering unit 1830.”); Ex 1001 at
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`29:31-53 (“FIG. 21 is a diagrammatic representation of a transaction flow in which
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`local probe filtering is facilitated . . . The memory controller . . . generates a probe
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`to the probe filtering unit PFU. . . . The PFU, in turn, probes nodes N0 and N2
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`after it applies its directory lookup and probe filtering algorithm”).
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`Thus, the specification of the ’121 Patent supports construing “probe
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`filtering unit” as requiring “an apparatus operable to filter probes within a single
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`cluster of processors.” This is significant because, as discussed below, Petitioners
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`fail to demonstrate that what they contend constitute “probes” in Chaiken are
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`filtered by what they contend to be the “probe filtering unit.”
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`B.
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`“states associated with selected ones of the cache memories” (claims 1,
`16, 25)
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`The Petition argues that, because this phrase is not expressly defined by the
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`’121 Patent, a general purpose dictionary should be used to construe this term,
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`resulting in the proposed construction “any modes or conditions of selected ones of
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`the cache memories.” However, Petitioners’ non-technical construction is plainly
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`unreasonable because it is divorced from the relevant technical context—cache
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`coherency. Indeed, it appears that, under Petitioners’ construction, the mode or
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`condition need not have any relation to cache coherency or even what is stored in
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`the selected ones of the cache memories. Contrary to Petitioners’ construction, in
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`the technical context of the ’121 Patent—cache coherency—”states associated with
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`selected ones of cache memories” should be construed to be “cache coherence
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`protocol states associated with data blocks stored in selected ones of the cache
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`memories” where a “cache coherence protocol state” means “the current state of a
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`data block in a protocol used to maintain the coherency of caches, in which a data
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`block can only be in one current state at a time, and in which the current state can
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`transition to a different state upon one or more triggering events or conditions.”
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`This construction is different from Petitioners’ construction in two important ways:
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`(1) the “states associated with selected ones of cache memories” refers to the
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`state(s) of data block(s) stored in the cache memories; and (2) the pertinent type of
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`“state” is a “cache coherence protocol state,” which is limited to “one current state
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`at a time,” but “in which the current state can transition to a different state upon
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`one or more triggering events or conditions.” Each of these differences will be
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`addressed below.
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`The claimed “states” refers to cache coherence protocol states
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`1.
`Petitioners argue that “states” in the ’121 Patent is not limited “even to a
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`particular group of states, such as standard coherence protocol states.” Pet. at 9.
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`They cite the portion of the specification which states that “The techniques of the
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`present invention can be used with a variety of different possible memory line
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`states.” Pet. at 9 (citing Ex. 1001 14:30-36). However, Petitioners notably ignore
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`the context in which that phrase appears:
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`Although the coherence directory 701 includes the four states of
`modified, owned, shared, and invalid, it should be noted that
`particular implementations may use a different set of states. In one
`example, a system may have the five states of modified, exclusive,
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`owned, shared, and invalid. The techniques of the present invention
`can be used with a variety of different possible memory line states.
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`Ex. 1001 at 14:30-36 (emphasis added). Thus, rather than suggesting that the state
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`in the ’121 Patent refers to “any mode or condition,” this section reinforces that the
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`relevant states are cache coherence protocol states (although not limited to any
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`particular cache coherence protocol’s set of states). Indeed, the ’121 Patent’s
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`discussion of the “probe filtering unit”—which Petitioners admit is the “focus” of
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`the independent claims of the ’121 Patent (Pet. at 18)—repeatedly reinforces that
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`the relevant “state” is a cache coherence protocol state. For example, the ’121
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`Patent explains that “[t]he PFU accepts the probe and looks up the address in its
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`directory of shared cache states . . . the directory of shared states may be
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`implemented as described above with reference to FIGS. 7 and 8.” Ex. 1001 at
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`28:25-34. In turn, these figures show classic cache coherence protocol states:
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`“Invalid,” “Shared,” “Owned,” “Modified.” Ex. 1001, Figs. 7, 8. Additionally, the
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`description of Figures 7 and 8 further demonstrate that the relevant “states” are
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`cache coherence protocol states. Ex. 1001 at 13:44-15:19. Notably, Petitioners
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`cannot point to any “states associated with” a cache memory in the ’121 Patent
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`other than cache coherence protocol states.
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`Petitioners instead rely on a single piece of extrinsic evidence, an article by
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`Chaiken, as allegedly supporting the notion that “state” is not limited to cache
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`coherence protocol states. Pet. 10 (citing Ex. 1004 at 50). But the cited portion of
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`Chaiken uses the ter