UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC., SAMSUNG
`ELECTRONICS CO. LTD, SAMSUNG ELECTRONICS AMERICA, INC., AND
`AMAZON.COM, INC.,
`Petitioners,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`____________
`
`Case IPR2015-00159
`Patent 7,296,121
`____________
`
`
`
`
`
`PETITIONERS’ REPLY TO PATENT OWNER RESPONSE
`PURSUANT TO 37 C.F.R. § 42.23
`
`
`
`
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC., SAMSUNG
`ELECTRONICS CO. LTD, SAMSUNG ELECTRONICS AMERICA, INC., AND
`AMAZON.COM, INC.,
`Petitioners,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`____________
`
`Case IPR2015-00159
`Patent 7,296,121
`____________
`
`
`
`
`
`PETITIONERS’ REPLY TO PATENT OWNER RESPONSE
`PURSUANT TO 37 C.F.R. § 42.23
`
`
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`
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`Patent No. 7,296,121
`Petitioner’s Reply to Patent Owner Response
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`Attorney Docket No. 39521-0007IP1
`IPR2015-00159
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`TABLE OF CONTENTS
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`I.
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`INTRODUCTION .............................................................................................. 1
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`II. CLAIM CONSTRUCTIONS ............................................................................. 1
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`A. “States” ........................................................................................................ 1
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`B. “Programmed” ............................................................................................. 5
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`III. THE INSTITUTED GROUNDS ANTICIPATE OR RENDER OBVIOUS
`CLAIMS 1–3, 8, 11, AND 15–25 .............................................................................. 7
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`A. Pong is Enabling Prior Art ........................................................................... 7
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`B. Pong Discloses the Claimed “States” ........................................................ 15
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`C. Pong Discloses the Claimed “Probes” ....................................................... 19
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`D. Pong Discloses that Each of its Processing Nodes is Programmed in the
`Manner Recited in Claim 11 ............................................................................ 21
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`E. Pong Discloses a Memory Controller that Accumulates Probe Responses
`as Recited in Claims 15 and 25 ........................................................................ 21
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`F. Pong Discloses the Valid Copy Recited in Claim 25 ................................ 24
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`IV. CONCLUSION ................................................................................................ 25
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`EXHIBITS
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`APPL-1025
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`Reply Declaration of Dr. Robert Horst
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`APPL-1026
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`APPL-1027
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`Deposition Transcript of Dr. Vojin G. Oklobdzija Vol. 1, November
`23, 2015
`Deposition Transcript of Dr. Vojin G. Oklobdzija Vol. 2, November
`24, 2015
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`APPL-1028
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`David E. Culler et al., Parallel Computer Architecture: A Hard-
`ware/software Approach (1st Ed.) (1998)
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`APPL-1029
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`APPL-1030
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`“InfiniBand Architecture Specification Volume 1 Release 1.0.a”
`(June 19, 2001)
`James Laudon and Daniel Lenoski, Proceedings of the 24th Annual
`International Symposium on Computer Architecture, "The SGI
`Origin: A ccNUMA Highly Scalable Server" (1997)
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`ii
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`I.
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`Introduction
`Petitioners submit this Reply to Memory Integrity’s (“MI”) Response (Paper
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`25) (“POR”). MI relies upon improper claim construction proposals that have al-
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`ready been considered and rejected in the Board’s Institution Decision (Paper 12).
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`MI’s proposals ignore the actual claim language and improperly seek to narrow the
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`broadest reasonable construction of the terms without support. Moreover, MI’s va-
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`lidity arguments are highly attenuated and reflect a flawed understanding of the
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`Pong reference. As explained in greater detail herein, MI’s arguments should be
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`dismissed.
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`II. Claim Constructions
`In an effort to avoid Pong’s anticipating disclosure, MI “engages in a post
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`hoc attempt to redefine the claimed invention by impermissibly incorporating lan-
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`guage appearing in the specification into the claims.” In re Paulson, 30 F.3d 1475,
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`1480 (Fed. Cir. 1994). MI’s proposals should be rejected as there is no clear defi-
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`nition, in the ’121 Patent or elsewhere, that warrants narrowing the terms.
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`A. “States”
`MI’s proposed construction improperly seeks to add the very limitation that
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`MI is trying to add with its Motion to Amend. Motion to Amend, p. 1 (seeking to
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`add “wherein said states comprise cache coherency states of a cache coherence
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`protocol” to substitute claims). This attempt by MI belies its argument that
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`“states” is already limited to “cache coherence protocol states.” MI should not be
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`allowed to use claim construction to add claim limitations without amendment.
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`Further, the Board has already considered intrinsic and extrinsic evidence
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`and found that the term “states … is not limited to cache coherence protocol states
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`and is broad enough to include the condition of presence—i.e., what is stored in
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`cache memory.” Institution Decision, pp. 9-10. MI effectively repeats its earlier
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`arguments, essentially citing to the same disclosure within the ’121 specification,
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`and has presented no new evidence to diminish the Board’s preliminary findings.
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`Additionally, MI’s proposal contains the word “state” that it seeks to define, ex-
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`posing MI’s attempt to narrow the broadest reasonable interpretation of this term.
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`“[T]he PTO should only limit the claim based on the specification or prose-
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`cution history when those sources expressly disclaim the broader definition.” In re
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`Bigio, 381 F.3d 1320, 1325 (Fed. Cir. 2004). Here, none of the passages cited by
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`MI amount to an express disclaimer. To the contrary, as noted in the Institution
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`Decision, all of the examples in the specification to which MI (again) points are
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`couched in broad language stating that “particular implementations may use a dif-
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`ferent set of states” and “[t]he techniques of the present invention can be used with
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`a variety of different possible memory line states.” Institution Decision, p. 9.
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`Moreover, the claims at issue recite “states associated with selected ones of
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`the cache memories.” This recital is broader than the individual “memory line”
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`states described in each of the ’121 Patent passages quoted by MI. POR, pp. 5-6
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`(“the cache state for a specified line”; “memory line state information”; and “the
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`memory line states are modified, owned, shared, and invalid”) (emphasis added).
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`MI does not and cannot explain why the meaning of states for individual “line”
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`content (these passages), which may be present in a variety of states, should be the
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`same as the state of the whole cache memories (as claimed). Indeed, MI’s expert
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`admitted that MI’s proposal (which he did not help in developing) “would not ap-
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`ply” when referring to entire “cache memories.” See Ex. 1026, 113:15-114:13;
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`112:13-16; 16:15-17:13.
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`Additionally, the dependent claims reveal that the patentee used express lan-
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`guage when seeking to limit a term to the context of cache coherency, and it clear-
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`ly omitted such language with respect to the term “states.” In particular, claim 3,
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`which depends indirectly from independent claim 1, recites that the probe filtering
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`unit corresponds to an additional node that “comprises a cache coherence control-
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`ler.” Claim 3 demonstrates that, where MI intended for a claim term to be limited
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`to the context of cache coherency, MI explicitly used the term “cache coherence”
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`in the claim language. The omission of “cache coherence” from claim 1 is telling,
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`and, under the broadest reasonable interpretation standard should be read in con-
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`trast with claim 3 to preserve the breadth of claim 1.
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`MI also relies upon extrinsic evidence as supportive of its position, citing to
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`two references by Daniel Sorin, one of which was published nearly nine years after
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`the priority date sought by MI. POR, pp. 4-5. However, “the fact that [MI] can
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`point to definitions or usages that conform to their interpretation does not make the
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`PTO’s definition unreasonable when the PTO can point to other sources that sup-
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`port its interpretation.” In re Morris, 127 F.3d 1048, 1056 (Fed. Cir. 1997). Here,
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`the Board cited to the Microsoft Computer Dictionary for support of its construc-
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`tion. Institution Decision, p. 10. MI’s criticism of this source is hardly credible as
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`MI endorses the use of the same Microsoft Computer Dictionary, as well as a gen-
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`eral purpose dictionary, for its “programmed” proposal. POR, p. 13.
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`Finally, the Petition contends that, even within the specific field of cache
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`coherence, the scope of the term “states” is “broad enough to include the condition
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`of presence,” as found by the Board. See, e.g., Petition, p. 10 (identifying the
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`Chaiken reference’s use of “status” to reference presence condition). The ’121 pa-
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`tent accords by also using the term “state” to refer to presence. See ’121 patent at
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`13:60-61 (“In the invalid state, a memory line is not currently available in cache
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`associated with any remote cluster.”). Indeed, the Sorin and Culler references that
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`MI cites also identify a “Not Present State.” Ex. 2010 at 89; Ex. 2002 at 4; see Ex.
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`1026 at 38:3-39:11 (Sorin and Culler are reliable references).
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`Accordingly, it is reasonable, for purposes of this proceeding in which the
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`broadest reasonable construction standard applies, to consider the term “states” as
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`being broad enough to encompass the condition of presence.
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`B. “Programmed”
`MI advanced arguments regarding the term “programmed” in its preliminary
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`response, without explicitly construing the term. MI now improperly seeks to ef-
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`fectively amend the claim to overcome the Board’s preliminary endorsement of the
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`Pong reference by advancing a narrowing interpretation of this term. MI asserts
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`that “the term ‘programmed’ should be construed to refer to a device that has been
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`‘configured by a sequence of instructions’” (POR, p. 11) and argues that “‘pro-
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`grammed’ is not broad enough to encompass hardwired logic” (POR, p. 15).
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`However, these proposals are not supported by the evidence. See Ex. 1025, ¶¶ 2-6.
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`The ’121 Patent does not use the words “instruction” or “execute.” The ’121
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`Patent makes no distinction between hardwired logic and the relevant portion of
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`the processors that dictate the completion of a memory transaction. MI has not cit-
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`ed to any language in the ’121 Patent which provides a clear limitation to the na-
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`ture of the programming. See POR, pp. 12-13. Indeed, the ’121 Patent is clear that
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`these cited sections are “merely exemplary for the purpose of describing a specific
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`embodiment of the present invention.” Ex. 1001, 28:2-5. Further, even the dic-
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`tionaries that MI cites include reasonable definitions for programming that defy
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`MI’s proposal, such as “to work out a sequence of operations to be performed by (a
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`mechanism).” Ex. 2014, p. 931.
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`Indeed, hardwired logic is designed to perform a sequence of operations.
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`For example, a field programmable gate array (FPGA) is effectively an array of
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`logic gates that can be interwired in different configurations according to a manu-
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`facturer’s programming. Ex. 1025, ¶ 3. Contrary to MI’s contention that the term
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`“programmed” is limited to devices that execute a series of instructions, a field
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`programmable gate array does not execute any instructions. Id. Rather, a designer
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`uses an interface to program the physical interconnections between the logic gates,
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`and the logic gates within the FPGA each perform a logical operation correspond-
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`ing to the gate’s type and its input signals. Id. Indeed, MI’s expert admitted that
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`“everybody use[s]” the term “programmable” with respect to an FPGA. See Ex.
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`1026, 123:12-124:11; see also Ex. 1025, ¶ 4.
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`MI’s evidence states that “in hardwired logic systems the physical intercon-
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`nections of the elements govern the routes by which data flows between the pro-
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`cessing elements and thus the sequence of processing operations performed on the
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`data.” Ex. 2015 at 15/3. Yet, this is entirely consistent with the operation of the
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`aforementioned field programmable gate array. Ex. 1025, ¶ 5. By its very name a
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`field programmable gate array is “programmed” by a designer. Indeed, MI’s own
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`specification uses the term “programmable” when referring to devices that do not
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`execute instructions, teaching that “the cache coherence controller 230 is a special-
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`ly configured programmable chip such as a programmable logic device or a field
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`programmable gate array.” Ex. 1001, 7:49-52 (emphasis added).
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`Accordingly, MI’s attempt to narrow the term “programmed” to exclude
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`hardwired systems is inconsistent with the use of the term “programmable” in the
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`’121 Patent and with the extrinsic evidence cited by MI. Indeed, to read the lim-
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`ited passages of the ‘121 Patent cited by MI any differently would be a clear viola-
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`tion of In re Bigio, as the section of the ‘121 Patent in which these passages appear
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`are clear that the examples given are not meant to be limiting. See Ex. 1001, 28:2-
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`5. Instead, consistent with its usage in the context of FPGAs and the dictionary
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`cited by MI, the term “programmed” should be construed at least broadly enough
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`to encompass “designed to perform a sequence of operations,” regardless of
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`whether this design is in hardware or software. See Ex. 1025, ¶ 6.
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`III. The Instituted Grounds Anticipate or Render Obvious Claims 1–3, 8, 11,
`and 15–25
`In its Response, MI largely reiterates arguments raised in its Preliminary Re-
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`sponse. The Board properly found such arguments deficient in its Institution Deci-
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`sion and should do so again, as no further evidence of import is now proffered by
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`MI to establish a valid legal basis for altering the Board’s initial findings.
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`A. Pong is Enabling Prior Art
`MI argues that “neither the Pong reference, nor the Pong reference in com-
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`bination with the Smith reference enables one of ordinary skill in the art to practice
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`the inventions of the independent claims of the ’121 Patent.” POR, p. 18. Howev-
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`er, MI has not overcome the presumption that prior art publications and patents
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`(like Pong) are enabling. In re Antor Media Corp., 689 F.3d 1282, 1287-88 (Fed.
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`Cir. 2012). To the contrary, the evidence of record proves that Pong would have
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`enabled a POSITA to make or use the claimed inventions from the Pong disclosure
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`together with information known in the art without undue experimentation.
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`The test for determining enabling disclosure under 35 U.S.C. § 112 is
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`whether a POSITA could make or use the claimed invention from the disclosed
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`subject matter together with information known in the art without undue experi-
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`mentation. United States v. Telectronics, Inc., 857 F.2d 778, 785 (Fed. Cir. 1988).
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`A disclosure can be enabling even though some experimentation is necessary. Hy-
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`britech Inc. v. Monoclonal Antibodies, Inc., 802 F.2d 1367, 1384 (Fed. Cir. 1986).
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`The issue is whether the amount of required experimentation is undue, not whether
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`any experimentation is necessary. In re Vaeck, 947 F.2d 488, 495 (Fed. Cir. 1991).
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`The relevant factors include: (1) the quantity of experimentation necessary, (2) the
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`amount of direction or guidance presented, (3) the presence or absence of working
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`examples, (4) the nature of the invention, (5) the state of the prior art, (6) the rela-
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`tive skill of those in the art, (7) the predictability or unpredictability of the art, and
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`(8) the breadth of the claims. See In re Wands, 858 F.2d 731, 737 (Fed. Cir. 1988).
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`The testimony of Dr. Oklobdzija does not explain “with sufficient specifici-
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`ty, what and how much experimentation would have been required by one with or-
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`dinary skill, nor why that amount of experimentation should be regarded as ‘un-
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`due.’” Liberty Mutual Insurance Co. v. Progressive Casualty Insurance Co.,
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`CBM2013-00009, Paper 68, p. 40 (P.T.A.B. Feb. 11, 2014). Dr. Oklobdzija barely
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`touches upon the level of experimentation, surmising (importantly, without citation
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`to any supporting evidence) that “it would take in excess of two years to design,
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`verify, and implement a computer system with a point-to-point architecture and
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`supporting cache coherency.” Ex. 2016, ¶ 83. Dr. Oklobdzija fails to identify any
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`legal standard applied in forming his enablement opinion.
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`Even if Dr. Oklobdzija’s naked statements were given full credit, they still
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`fail to explain why this two year design period is undue under the circumstances,
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`nor sufficiently address the various factors set forth in Wands. For example,
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`though Dr. Oklobdzija raises issues with respect to the identity/type of messages
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`used in the Pong system and how those messages are generated and handled by the
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`system, Dr. Oklobdzija does not relate these apparently missing details of Pong to
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`the breadth of the claims of the ‘121 patent (which do not recite these limitations),
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`nor does he address whether such implementation details were well known to a
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`POSITA (which, as will be demonstrated in the next section, they were). Indeed,
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`MI’s expert admitted that his enablement opinions related to features that are not
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`required by the challenged claims. Ex. 1026, 140:2-17; 140:24-141:8 (opining that
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`Pong is not enabled for a system with “more than 16” processors that creates a
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`point to point architecture by “emulating a shared bus-type protocol”). This ane-
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`mic showing compares unfavorably to the extremely high bar established for undue
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`experimentation. Even complex experimentation may not be undue, if the art typi-
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`cally engages in such experimentation. In re Wands, 858 F.2d at 737. According-
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`ly, MI has not met its burden to prove that Pong is not enabling.
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`Contrary to Dr. Oklobdzija’s unsupported conclusions (which relies upon
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`unsupported claim constructions (Ex. 1026, 131:25-132:18), the record demon-
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`strates that Pong would have enabled one of ordinary skill in the art to make or use
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`the claimed invention without undue experimentation, particularly when consider-
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`ing the Pong disclosure together with information in the prior art. Indeed, the level
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`of implementation detail provided by Pong, of which MI argues there is too little,
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`is entirely consistent with the level of implementation detail provided in similar
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`applied prior art disclosures of cache coherent systems, such as Koster (which, no-
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`tably, MI did not argue is not enabling). Ex. 1025, ¶ 7.
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`Further, Pong discloses various alternative embodiments of its invention,
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`separating its disclosure into clearly identifiable sections. Ex. 1025, ¶ 8. MI’s at-
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`tempt to contrast disclosures from these distinct embodiments and declare them
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`“incompatible” is simply not evidence that the single embodiment upon which the
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`Petition relies (i.e., the embodiment shown in FIG. 4) does not itself enable the
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`claims. Rather, a POSITA would have found it straightforward to distinguish
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`Pong’s embodiments and understand how the disclosure related to each could be
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`used to implement each embodiment. Id.
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`Turning to the disclosure of Pong, a first set of embodiments, illustrated in
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`FIGS. 2-3, are described in ¶¶ 0029-0043. In these embodiments, the queues in the
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`memory controller are “designed to broadcast the request to all other processors
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`and the memory.” Ex. 1003, ¶ 0032. Thus, these particular embodiments “emu-
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`lat[e] a shared bus type of protocol,” a protocol that similarly ensures that all re-
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`quests are sent to all processors. Ex. 1003, ¶ 0029; see Ex. 1025, ¶ 9. Further,
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`Pong provides details regarding the physical architecture of its system, including
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`the use of point-to-point links to connect each processor to a central memory con-
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`troller 206, that the memory controller 206 includes queues that buffer and forward
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`requests, and that the data path internal to the memory controller 206 “may be im-
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`plemented with data switches, point-to-point links, a shared bus, etc.” See Ex.
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`1003, ¶¶ 0029-0043.
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`Contrary to Dr. Oklobdzija’s expressed confusion (Decl., ¶ 76) about how
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`such an architecture could be implemented, the comprehensive Culler prior art
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`textbook (Ex. 2011) cited elsewhere by Dr. Oklobdzija describes Pong’s general
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`architecture as “common” and identifies it as one of “four categories” into which
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`all memory hierarchies generally fall, depending on the relative positioning of pro-
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`cessors, cache(s), and main memory with respect to the interconnect. Ex. 1028, pp.
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`270-271; see also Ex. 2016, ¶¶ 90, 93. Pong’s architecture, known as “dancehall,”
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`is shown in FIG. 5.2(c) of the Culler textbook, and applies to systems in which
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`each processor has its own private cache and is separated from main memory by a
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`point-to-point interconnect. See Ex. 1028, pp. 271; see also Ex. 1025, ¶¶ 10-11.
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`Indeed, contrary to Dr. Oklobdzija’s assertions (Decl., ¶ 75), use of cache coher-
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`ence schemes in a scalable point-to-point architecture was well-known before
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`2002, as evidenced by Culler’s devotion of an entire chapter to detailing various
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`cache coherent “directory schemes [that] rely on point-to-point network transac-
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`tions.” Ex. 1028, p. 555 (introducing the subject matter of Chapter 8).
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`Pong (starting at ¶ 0044) provides further enabling disclosure regarding
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`“[o]ptimizations” to the FIGS. 2 and 3 embodiments, which are specifically illus-
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`trated with regard to FIGS. 4-6. Ex. 1025, ¶ 12. In these embodiments, a central
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`directory located in the memory controller (FIG. 4), a separate memory component
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`(FIG. 5), or folded into the data blocks in main memory (FIG. 6), is used to filter
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`requests to reduce traffic. See Ex. 1003, ¶¶ 0056-0060; see also Ex. 1025, ¶ 12.
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`Pong discloses various ways in which such a directory may be used to filter
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`requests, and a POSITA would have been able to easily distinguish between them.
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`Ex. 1025, 13¶. For example, Pong discloses an embodiment in which a requesting
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`processor uses information contained in a directory to specifically address requests
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`to a processor storing a valid copy. Ex. 1003, ¶ 0047. According to the Culler
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`textbook, it was a common technique for a requesting processor to consult a direc-
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`tory in this manner. See Ex. 1028, p. 585. Pong also discloses an alternative ap-
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`proach, in which the directory itself “filters the request and addresses it to the ap-
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`propriate processors.” Ex. 1003, ¶ 0056. Again, the Culler textbook verifies this
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`as a well understood alternative to the embodiment of paragraph 47 that reduces
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`transactions on the interconnect, referring to it as “intervention forwarding.” See
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`Ex. 1028, p. 585. In other words, the Culler prior art textbook demonstrates that a
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`POSITA would have understood Pong’s description in ¶¶ 47 and 56 as well-known
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`alternative embodiments, and would not have viewed them as conflicting, as Dr.
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`Oklobdzija suggests (in Decl., ¶ 78). Ex. 1025, ¶ 14.
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`The other “incompatible embodiments” identified by Dr. Oklobdzija (Decl.,
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`¶ 79) would have similarly been identified as distinctly operable alternative em-
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`bodiments by a POSITA, and not contradictions regarding a single embodiment.
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`Ex. 1025, ¶ 15. Importantly, though, the only embodiment relied upon in the Peti-
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`tion is the embodiment shown in FIG. 4, which is described at least in part in para-
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`graphs 0050-0057, where Pong specifies that, “[u]nless otherwise noted, the de-
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`scription of the components is the same as provided” with regard to FIGS. 2 and 3.
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`Pong, ¶ 0056. In other words, Pong is clear that any description of the embodi-
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`ment shown in FIG. 4 takes precedence over any contradictory description of the
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`previous embodiments. Ex. 1025, ¶ 15.
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`With regard to FIG. 4, Pong discloses that the directory is implemented with
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`a presence bit vector. Ex. 1003, ¶ 0051. The Culler textbook confirms that the use
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`of such a presence bit vector was common at the time of the ’121 Patent and even
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`provides specific description regarding how directories commonly used a presence
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`bit vector to implement a cache coherence scheme. See Ex. 1028, pp. 560-64.
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`Thus, contrary to Dr. Oklobdzija’s conclusions, the Culler textbook demonstrates
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`that a POSITA would have readily known how to implement the Pong FIG. 4 em-
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`bodiment, in which a centralized directory utilizes intervention forwarding and a
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`presence bit vector to implement a cache coherence protocol. Ex. 1025, ¶ 16.
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`While the over 120 pages devoted to directory-based cache coherence in the
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`Culler textbook demonstrate that there were a number of low-level implementation
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`choices a POSITA could have made in making the embodiment shown in FIG. 4,
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`these pages provide evidence that these details were well within the ability and
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`knowledge of a POSTIA. See Ex. 1025, ¶ 17; see generally Ex. 1028, Chap. 8.
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`Indeed, the Culler textbook details various case studies of working directory-based
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`systems and simulations that were commonly used to test them. See Ex. 1028, pp.
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`576-77, 596-644.
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`For at least these reasons, the record demonstrates that Pong would have en-
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`abled a POSITA to make or use the claimed invention without undue experimenta-
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`tion, particularly when considering the Pong disclosure together with information
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`known in the prior art, such as the teachings of the Culler textbook cited by MI.
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`B. Pong Discloses the Claimed “States”
`MI’s argument rests entirely upon its claim construction of the term “state,”
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`which is improperly narrow for the reasons described above. The Board should
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`uphold its preliminary determinations of the scope of the term “state,” and dismiss
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`MI’s arguments with regard to this feature as moot. And, even if the Board were
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`to reverse its preliminary determinations, the Board should dismiss this argument
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`because Pong meets the claims even under MI’s narrow definition of “states.”
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`The claims recite “probe filtering information representative of states associ-
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`ated with selected ones of the cache memories.” As noted in the Petition, in either
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`an update or a write invalidation type of cache coherence protocol, presence bits in
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`a centralized directory, like the directory filter 400 of the memory controller, indi-
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`cate the presence of valid copies of memory. See Ex. 1014 at ¶¶ A-10 to A-13.
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`Validity is undoubtedly a state of memory, so the validity information stored in
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`Pong’s directory filter 400 is probe filtering information representative of states as-
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`sociated with selected ones of the cache memories. See Ex. 1025, ¶¶ 19, 26. To
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`rebut this evidence, MI cites to the teachings of Pong and other extrinsic evidence.
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`MI’s arguments are flawed in at least two respects, as noted below.
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`First, MI argues that Pong ¶ 0013 demonstrates that Pong’s presence bit vec-
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`tor does not maintain validity information. See POR, pp. 25-26. However, the
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`portions of Pong cited by MI are not tied to the Fig. 4 Pong embodiment upon
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`which Petitioner relies. Ex. 1025, ¶ 20. Instead, Pong discloses that Fig. 4 is an
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`“alternative implementation[].” Ex. 1003, ¶ 0056. Additionally, MI’s quote of
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`Pong ¶ 0013 is misleading as it includes ellipses omitting that the section is refer-
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`ring to “broadcast[ing]” (i.e., sending requests to all processors) as an alternative
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`to sending to targeted processors.
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`Moreover, even if the cited portion of Pong was applicable to the Fig. 4 al-
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`ternative implementation (which it is not), it was well known at the time of Pong’s
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`disclosure that processors of the type disclosed by Pong may be designed to redun-
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`dantly check validity. Ex. 1025, ¶ 21. As such Pong’s disclosure of processors’
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`separate validity check does not mean that the directory filter 400 fails to also track
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`validity. Id. For example, at the time of the ‘121 patent, processors were known
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`by POSITAs to have the ability to flush memory lines from their caches without
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`alerting the central directory. Id.
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`Second, MI alleges that “how other references implement their cache coher-
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`ence protocols is not instructive in how Pong implements its own protocol.” POR,
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`p. 26. However, extrinsic evidence is useful in assessing the teachings of a refer-
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`ence by evidencing technological facts known to those in the field of the invention.
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`See, e.g., Continental Can Co. USA, Inc. v. Monsanto Co., 948 F. 2d 1264, 1269
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`(Fed. Cir. 1991). Here, far from the overly broad “assumptions” that MI accuses
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`Dr. Horst of making by citing to the extrinsic evidence, Dr. Horst properly uses the
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`extrinsic evidence to show how a POSITA would understand Pong to work. Based
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`on his own experience and the teachings of the prior art generally, Dr. Horst found
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`that it would make no sense for Pong’s presence bit vector to indicate the presence
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`of memory lines it knows to be invalid. See Ex. 1014, ¶¶ A-10 to A-13.
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`Put simply, the fact that the memory controller uses the presence bit vector
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`to forward requests to only a subset of the processor caches is indicative of a belief
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`(based on the best information available at the memory controller) that this subset
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`of processor caches is the only set of caches with valid copies of the requested
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`memory lines. Ex. 1025, ¶ 22. After all, a POSITA would understand that it
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`makes no sense for the memory controller to forward requests to processor caches
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`that it believes have an invalid copy, as such processor caches are already known
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`to be unable to respond to the requests and, thus, forwarding requests to these
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`caches does nothing more than needlessly increase traffic in Pong’s control path.
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`Id. Such a needless increase in traffic contradicts the very reason why the presence
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`bit vector is used in Pong’s system – i.e., to optimize performance by “limiting
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`traffic in the control path.” Id. (citing Ex. 1003, ¶ 0045).
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`Rather than rebut this understanding, Dr. Horst’s views are proven by the
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`extrinsic evidence cited by MI. For example, MI cites the Dragon protocol as evi-
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`dence that “write-update protocols do not have a valid/invalid state.” POR, p. 27.
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`Yet, this characterization of the Dragon protocol misleads. In the Dragon protocol,
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`all states are “valid.” In fact, because “the protocol always keeps the blocks in the
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`cache up-to-date, so it is always okay to use the data present in the cache if the tag
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`ma
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