UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`PETITIONERS’ REPLY TO PATENT OWNER’S
`RESPONSE TO PETITION
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`SONY CORPORATION, SONY ELECTRONICS INC.,
`SONY MOBILE COMMUNICATIONS AB, and
`SONY MOBILE COMMUNICATIONS (USA) INC.
`Petitioners,
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`v.
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`MEMORY INTEGRITY, LLC,
`Patent Owner.
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`Case IPR2015-00158
`Patent 7,296,121 B2
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`PETITIONERS’ REPLY TO PATENT OWNER’S
`RESPONSE TO PETITION
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`SONY CORPORATION, SONY ELECTRONICS INC.,
`SONY MOBILE COMMUNICATIONS AB, and
`SONY MOBILE COMMUNICATIONS (USA) INC.
`Petitioners,
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`v.
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`MEMORY INTEGRITY, LLC,
`Patent Owner.
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`Case IPR2015-00158
`Patent 7,296,121 B2
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`IPR2015-00158
`Patent 7,296,121
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`TABLE OF CONTENTS
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`INTRODUCTION ........................................................................................... 1
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`CLAIM CONSTRUCTION OF “STATES” ................................................... 1
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`Page
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`I.
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`II.
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`III. THE INSTITUTED CLAIMS ARE UNPATENTABLE ............................... 5
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`IV. CONCLUSION ................................................................................................ 8
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`A.
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`Claim 24 is Obvious Over Koster Alone .............................................. 5
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`1.
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`2.
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`Koster Discloses “Probe Filtering Information Representative
`of States Associated With Selected Ones of the Cache
`Memories” Under the Correct Construction ............................... 5
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`Koster Discloses “Probe Filtering Information Representative
`of States Associated With Selected Ones of the Cache
`Memories” Under Patent Owner’s Incorrect Construction ........ 6
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`B.
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`Claims 19–23 Are Obvious Over Koster In View of Kuskin ............... 7
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`i
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`IPR2015-00158
`Patent 7,296,121
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`TABLE OF AUTHORITIES
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`Page(s)
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`CASES
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`Flo Healthcare Solutions, LLC v. Kappos,
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`697 F.3d 1367 (Fed. Cir. 2012) ....................................................................... 3
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`Silicon Graphics, Inc. v. ATI Techs. Inc.,
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`607 F.3d 784 (Fed. Cir. 2010) ......................................................................... 2
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`ii
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`IPR2015-00158
`Patent 7,296,121
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`LIST OF EXHIBITS
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`Exhibit Name
`Ex. No.
`Sony-1001 U.S. Patent No. 7,296,121 (“the ’121 Patent”)
`Sony-1002 File History for U.S. Pat. App. No. 10/966,161
`Sony-1003 U.S. Patent No. 7,003,633 (“the ’633 Patent”)
`Sony-1004 Comparison of ’121 Patent and ’633 Patent Specifications
`Sony-1005 U.S. Patent No. 7,698,509 to Koster (“Koster”)
`Jeffrey Kuskin, et al., The Stanford FLASH Multiprocessor,
`Sony-1006
`PROCEEDINGS ON THE 21ST ANNUAL INTERNATIONAL SYMPOSIUM ON
`COMPUTER ARCHITECTURE, IEEE (1994) (“Kuskin”)
`Sony-1007 S. Park et al., Verification of Cache Coherence Protocols by
`Aggregation of Distributed Transactions, Theory of Computing
`Systems 31 (1998) (“Park”)
`Sony-1008 U.S. Patent No. 6,088,769 to Luick (“Luick”)
`Sony-1009 U.S. Pat. Pub. 2002/0073261 (“Kosaraju”)
`Sony-1010 AUTHORITATIVE DICTIONARY OF IEEE STANDARDS TERMS (2000)
`Sony-1011
`Jeffrey L. Hilbert, APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC)
`TECHNOLOGY (Academic Press 1991)
`Sony-1012 Ronald Sass, Andrew G. Schmidt, EMBEDDED SYSTEMS DESIGN WITH
`PLATFORM FPGAS: PRINCIPLES AND PRACTICES (Morgan Kaufmann
`2010)
`Sony-1013 Expert Declaration of Daniel J. Sorin
`Sony-1014 Curriculum Vitae of Daniel J. Sorin
`Sony-1015 Supplemental Expert Declaration of Daniel J. Sorin
`Sony-1016 Deposition Transcript of Vojin Oklobdzija (November 23–24, 2015)
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`iii
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`IPR2015-00158
`Patent 7,296,121
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`I.
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`INTRODUCTION
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`Sony Corporation, Sony Electronics Inc., Sony Mobile Communications
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`AB, and Sony Mobile Communications (USA) Inc. (collectively, “Petitioners”)
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`hereby submit their reply to Patent Owner’s Response to Petition (Paper No. 17,
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`“Response”). In its Decision on Institution of Inter Partes Review (Paper No. 7,
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`“Institution Decision”), the Patent Trial and Appeal Board (“Board”) instituted
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`review of claims 19–24 of U.S. Patent No. 7,296,121 (“the ’121 patent”). In
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`particular, the Board instituted review of claim 24 as obvious over U.S. Patent No.
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`7,698,509 to Koster et al. (“Koster”), and claims 19–23 as obvious over Koster in
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`view of Jeffrey Kuskin, et al., The Stanford FLASH Microprocessor, PROCEEDINGS
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`OF THE 21ST ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE,
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`IEEE (1994) (“Kuskin”). The Patent Owner’s Response has essentially one
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`argument—that the Board’s Institution Decision relied on an incorrect claim
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`construction of the term “states.” As described below however, the Board’s
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`construction of “states” was correct, and accordingly claims 19–24 are
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`unpatentable. Moreover, claims 19–24 are unpatentable even under Patent
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`Owner’s incorrect construction of “states” because Koster discloses such states.
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`1
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`Patent 7,296,121
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`II. CLAIM CONSTRUCTION OF “STATES”
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`The Patent Owner argues that the construction of the term “states” is limited
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`to “cache coherence protocol states.” Response at 1–12. The Patent Owner’s
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`construction is incorrect however, because the ordinary meaning of term “states”
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`includes the condition of presence. Both the intrinsic and extrinsic evidence
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`support the Board’s construction in its Institution Decision that the ordinary
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`meaning of the term “states” includes the condition of presence.
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`Most importantly, the specification describes the term “states” as
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`encompassing memory line states other than the cache coherency protocol states to
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`which Patent Owner seeks to confine the term’s meaning, stating that:
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`Although the coherence directory 701 includes the four states of
`modified, owned, shared, and invalid, it should be noted that
`particular implementations may use a different set of states. In
`one example, a system may have the five states of modified,
`exclusive, owned, shared, and invalid. The techniques of the present
`invention can be used with a variety of different possible memory
`line states.
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`Ex. 1001 at 14:30–36; see also 28:29–43. There is nothing in the specification that
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`limits “states” to those states of specific cache coherency protocols such as MOESI
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`(Modified, Owned, Exclusive, Shared, Invalid). In arguing for such a limitation,
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`the Patent Owner violates the fundamental rule that terms should not be limited to
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`particular examples disclosed in the specification. Silicon Graphics, Inc. v. ATI
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`Patent 7,296,121
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`Techs. Inc., 607 F.3d 784, 792 (Fed. Cir. 2010) (“A construing court’s reliance on
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`the specification must not go so far as to import limitations into the claims from
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`examples or embodiments appearing only in the patent’s written description unless
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`the specification makes clear that the patentee intends for the claims and the
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`embodiments in the specification to be strictly coextensive.”) (internal quotation
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`omitted); Flo Healthcare Solutions, LLC v. Kappos, 697 F.3d 1367, 1375 (Fed.
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`Cir. 2012) (“[I]t is not proper to import from the patent’s written description
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`limitations that are not found in the claims themselves.”). The fact that the ’121
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`patent discloses states of specific cache coherency protocols (such as MOESI) does
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`not mean that “states” must be limited to those states found in specific cache
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`coherency protocols.
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`Furthermore, it should be noted that the Patent Owner’s Motion to Amend
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`seeks to add the very limitation that it contends is already present in the claims.
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`Specifically, the Patent Owner’s Motion to Amend seeks to add the limitation of
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`“wherein said states comprise cache coherency states of a cache coherence
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`protocol” to claims 19–24. Paper No. 18 at 2. This attempt by the Patent Owner
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`belies its argument that “states” is already limited to “cache coherence protocol
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`states.” The Patent Owner cannot use claim construction as a vehicle to add claim
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`Patent 7,296,121
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`limitations years after the fact—that should only be attempted in an IPR
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`proceeding through a motion to amend.
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`Moreover, the Patent Owner relies on A Primer on Memory Consistency and
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`Cache Coherence (2011) (Memory Integrity Exhibit 2010) authored by Dr. Daniel
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`Sorin in support of its construction. Response at 4. However, as stated by Dr.
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`Sorin himself, the Patent Owner’s characterization of this book is overly
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`restrictive. Ex. 1015 at ¶ 19 (“Sorin Supp. Decl.”). While this book provides
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`examples of various types of “states,” it does not use the term “state” to mean only
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`a cache coherence protocol state. Sorin Supp. Decl. at ¶ 19. Dr. Sorin himself
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`agrees that person of ordinary skill in the art would understand the term “states
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`associated with selected ones of the cache memories” to not be limited to cache
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`coherence protocol states, and be broad enough to include the condition of
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`presence—i.e., what is stored in cache memory. Sorin Supp. Decl. at ¶¶ 17–18.1
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`In fact, presence information alone (i.e., what is stored in cache memory), is
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`1
`Additionally, as noted by the Board, the definition of “state” in MICROSOFT
`COMPUTER DICTIONARY is “[t]he condition of a particular time of any of numerous
`elements of computing—a device, a communications channel, a network station, a
`program, a bit, or other element—used to report on or to control computer
`operations.” Ex. 3001 (MICROSOFT COMPUTER DICTIONARY (5th ed. 2002)), 497–
`98.
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`Patent 7,296,121
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`enough information for maintaining coherence in a simple cache coherence
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`protocol. Sorin Supp. Decl. at ¶ 17.
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`Therefore, the proper construction of “states” is broad enough to include the
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`condition of presence.
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`III. THE INSTITUTED CLAIMS ARE UNPATENTABLE
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`A. Claim 24 is Obvious Over Koster Alone.
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`1.
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`Koster Discloses “Probe Filtering Information
`Representative of States Associated With Selected Ones of
`the Cache Memories” Under the Correct Construction.
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`Claim 16 of the ’121 patent recites “probe filtering information
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`representative of states associated with selected ones of the cache memories.” Ex.
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`1001 at claim 16. Each of claims 19–24 depend directly or indirectly from claim
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`16, and therefore include this same limitation. Ex. 1001 at claims 19–24. The
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`Patent Owner argues that “states associated with selected ones of the cache
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`memories” refers to “cache coherency states,” and that under this construction,
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`“Koster’s tags do not satisfy the limitation because they are not representative of
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`cache coherency states.” Response at 13. The Patent Owner’s argument should be
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`rejected because, as described above, the proper construction of “states” is includes
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`the condition of presence. Koster discloses shadow tag memory 194 which stores
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`copies of tags of data stored in local cache memories of microprocessors 182, 184,
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`186, and 188. Ex. 1005 at 6:8–17; 7:3–6. These tags indicate where specific data
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`is cached (i.e., the presence of data in specific locations). Ex. 1005 at 6:8–17; 7:3–
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`6. Indeed, the Patent Owner’s expert Dr. Oklobdzija concedes that under the
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`Board’s construction of “states,” Koster discloses “states:”
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`Q. But under the Board’s construction of “states,” which is
`different from yours, does Koster disclose states?
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`***
`A.
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`That is yes. Koster has tags and tags indicate presence, and if
`Board defines “presence” as a state, then under Board
`definition, they—they represent state.
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`Ex. 1016 at 186:17–24 (“Oklobdzija Depo.”). Therefore, Koster discloses the
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`claim limitation of “probe filtering information representative of states associated
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`with selected ones of the cache memories.” Sorin Supp. Decl. at ¶ 21.
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`2.
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`Koster Discloses “Probe Filtering Information
`Representative of States Associated With Selected Ones of
`the Cache Memories” Under Patent Owner’s Incorrect
`Construction.
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`The Patent Owner argues that “state” should be construed as “cache
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`coherence protocol state.” Response at 5. However, even under this incorrect
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`construction, Koster discloses “states” because it discloses that the snoop filter 162
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`contains shadow tag memory 164 which can use the well-known MOESI cache
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`coherency protocol:
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`6
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`IPR2015-00158
`Patent 7,296,121
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`In one or more embodiments of the present invention, a shadow tag
`memory may be optimistically maintained as a set-associative cache.
`Further, in one or more embodiments of the present invention, the set-
`associative cache may use a MOESI (Modified Owner Exclusive
`Shared Invalid) cache-coherency protocol.
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`Ex. 1005 at 6:34–37. The Patent Owner repeatedly criticizes Koster as merely
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`disclosing a “shadow tag memory.” Response at 13–16. Yet, the Patent Owner
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`simply ignores the fact that Koster discloses that its “shadow tag memory” may be
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`maintained as a “set-associative cache” which may use a MOESI cache coherency
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`protocol. Ex. 1005 at 6:34–37. Dr. Sorin agrees that under the Patent Owner’s
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`incorrect construction that “states” means “cache coherence protocol states,”
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`Koster nevertheless discloses “states” through its disclosure of the MOESI cache
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`coherency protocol. Sorin Supp. Decl. at ¶ 22. Dr. Oklobdzija even concedes that
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`the MOESI cache coherency protocol states are used to maintain cache coherency
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`in Koster. Oklobdzija Depo. at 147:3–148:12. Therefore, Koster discloses the
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`claim limitation of “probe filtering information representative of states associated
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`with selected ones of the cache memories.” Sorin Supp. Decl. at ¶ 22.
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`B. Claims 19–23 Are Obvious Over Koster In View of Kuskin
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`Patent Owner’s only argument with respect to claims 19–23 is that because
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`Koster fails to disclose the “probe filtering information representative of states”
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`limitation of claim 16, that Koster cannot disclose the limitation in claims 19–23 as
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`IPR2015-00158
`Patent 7,296,121
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`well. As described above however, Koster does disclose the “probe filtering
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`information representative of states” limitation of claim 16. The Patent Owner’s
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`argument should therefore be rejected.
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`IV. CONCLUSION
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`For the foregoing reasons, Petitioners respectfully request that the Board
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`find claims 19–24 unpatentable.
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`Respectfully submitted,
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`/Zaed M. Billah/
`Walter E. Hanley, Jr.
`Reg. No. 28,720
`Zaed M. Billah
`Reg. No. 71,418
`Kenyon & Kenyon LLP
`One Broadway
`New York, New York 10004
`Phone: 212-425-7200
`Fax: 212-425-5288
`Email: whanley@kenyon.com
`Email: zbillah@kenyon.com
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`
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`Dated: December 1, 2015
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`IPR2015-00158
`Patent 7,296,121
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`CERTIFICATE OF SERVICE
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`The undersigned hereby certifies that a copy of the foregoing
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`PETITIONERS’ REPLY TO PATENT OWNER’S RESPONSE TO PETITION
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`was served via email on December 1, 2015 on the attorneys for the Patent Owner:
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` Jonathan D. Baker, Reg. No. 45,708
`Michael Saunders, Admitted Pro Hac Vice
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`Gurtej Singh, Reg. No. 71020
` Farney Daniels PC
` 411 Borel Avenue, Suite 350
` San Mateo, California 94402
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`Phone: 424-268-5200
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`
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`Email: jbaker@farneydaniels.com
`Email: msaunders@farneydaniels.com
`Email: tsingh@farneydaniels.com
`Email: MemoryIntegrityIPR@farneydaniels.com
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`/Zaed M. Billah/
`Zaed M. Billah
`Reg. No. 71,418
`Kenyon & Kenyon LLP
`One Broadway
`New York, New York 10004
`Phone: 212-425-7200
`Fax: 212-425-5288
`Email: zbillah@kenyon.com
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`9
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`Dated: December 1, 2015
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