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`3
`
`

`
`Application-Spe ific
`Integrated Cir uits
`
`Michael John Sebastian Smith
`
`A.
`TT
`ADDISON-WESLEY
`Boston • San Francisco • New York • Toronto • Montreal
`London • Munich • Paris • Madrid
`Capetown • Sidney • Tokyo • Singapore • Mexico City
`
`4
`
`

`
`This bookis.in the Addison-Wesley VLSI Systems Series
`Lynn Conway and Charles Seitz, Consuliing Editors
`
`Sponsoring Editor
`Associate Editor
`Senior Production Supervisor
`Copyeditor!Proofreader
`Cover Design Supervisor
`Marketing Manager
`Manufacturing Manager
`
`Peter Gordon
`Helen Goldstein
`Juliet Silveri
`Cynthia Benn
`Simone Payment
`Tracy Russ
`Roy Logan
`
`Material in Chapters 10-12, Chapter 14, Appendix A, and Appendix B in this book is reprinted from IEEE Std 1149.1-1990,
`"IEEE Standard Test Access Port and Boundary-Scan Architecture," Copyright © 1990; IEEE Std 1076/lNT-1991 "IEEE Stan(cid:173)
`dards Interpretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual," Copyright © 1991; IEEE Std
`1076-1993 "IEEE Standard VHDL Language Reference Manual," Copyright © 1993; IEEE Std 1164-1993 "IEEE Standard Mul(cid:173)
`tivalue Logic System for VHDL Model Interoperability (Std_Iogic.L.1164)," Copyright © 1993; IEEE Std 1149.1 b-1994 "Supple(cid:173)
`ment to IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture," Copyright © 1994; IEEE Std
`1076.4-1995 "IEEE Standard for VITAL Application-Specific Integerated Circuit (ASIC) Modeling Specification," Copyright
`© 1995; IEEE 1364-1995 "IEEE Standard Description Language Based on the Verilog® Hardware Description Language," Copy(cid:173)
`right © 1995; and IEEE Std 1076.3-1997 "IEEE Standard for VHDL Synthesis Packages," Copyright © 1997; by the Institute of
`Electrical and Electronics Engineers, Inc. The IEEE disclaims any responsibility or liability resulting from the placement and use
`in the described manner. Information is reprinted with the permission of the IEEE. Figures produced by the Compass Design
`Automation software in Chapters 9-17 are reprinted with permission of Compass Design Automation. Figures describing Xilinx
`FPGAs in Chapters 4-8 are courtesy of Xilinx, Inc. ©Xilinx, Inc. 1996, 1997. All rights reserved. Figures describing Altera
`CPLDs in Chapters 4-8 are courtesy of Altera Corporation. Altera is a trademark and service mark of Altera Corporation in the
`United States and other countries. Altera products are the intellectual property of Altera Corporation and are protected by copy(cid:173)
`right laws and one or more U.S. and foreign patents and patent applications. Figures describing Actel FPGAs in Chapters 4-8 are
`courtesy of Actel Corporation.
`
`Library of Congress Cataloging-in-Publication Data
`
`Smith, Michael J. S. (Michael John Sebastian)
`Application-specific integrated circuits / Michael J.S. Smith.
`p.
`cm.
`Includes bibliographical references and index.
`ISBN 0-201-50022-1
`1. Application-specific integrated circuits. 1. Title.
`TK7874.6.S63 1997
`621.39'5--dc20
`
`93-32538
`CIP
`
`N,lany of the designations used by manufacturers and sellers to distinguish their products are claimed as trademarks. Where those
`designations appear in this book, and we were aware of a trademark claim, the designations have been printed in initial capital
`letters or in all capitals.
`
`The author and publisher have taken care in the preparation of this book, but make no expressed or implied warranty of any kind
`and assume no responsibility for errors or omissions. No liability is assumed for incidental or consequential damages in connec(cid:173)
`tion with or arising out of the use of the information or programs contained herein.
`
`Visit A Won the Web: www.awl.comlcseng/
`
`Copyright © 1997 by Addison-Wesley
`
`All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form, or by
`any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior consent of the publisher. Printed in the
`United States of America. Published simultaneously in Canada.
`
`ISBN 0-201-50022-1
`Text printed on recycled paper
`8 9 10 11 12 13 J4-CRW -0403020100
`8th printing, May 2000
`
`5
`
`

`
`·PREFACE
`
`In 1988 I began to teach full-custom VLSI design. In 1990 I started teaching ASIC
`design instead, because my students found it easier to get jobs in this field. I wrote a
`proposal to The National Science Foundation (NSF) to use electronic distribution of
`teaching material. Dick Lyon helped me with preparing the first few CD-ROMs at
`Apple, but Chuck Seitz, Lynn Conway, and others explained to me that I was facing
`a problem that Carver Mead and Lynn had experienced in trying to get the concept
`of multichip wafers adopted. It was not until the publication of the Mead-Conway
`text that people accepted this new idea. It was suggested that I must generate interest
`using a conventional format before people would use my material in a new one
`(CD-ROM or the Internet). In 1992 I stopped writing papers and began writing this
`book-a result of my experiments in computer-based education. I have nearly fin(cid:173)
`ished this book twice. The first time was a copy of my notes. The second time was
`just before the second edition of Weste and Eshragian was published-a hard act to
`follow. In order to finish in 1997 I had to stop updating and including new ideas and
`material and now this book consists of three parts: Chapters 1-8 are an introduction
`to ASICs, 9-14 cover ASIC logical design, and 15-17 cover the physical design of
`ASICs.
`The book is intended for a wide audience. It may be used in an undergraduate or
`graduate course. It is also intended for those in industry who are involved with
`ASICs. Another function of this book is an "ASIC Encyclopedia," and therefore I
`have kept the background material needed to a minimum. The book makes extensive
`use of industrial tools and examples. The examples in Chapters 2 and 3 use tools and
`libraries from MicroSim (PSpice), Meta Software (HSPICE), Compass Design
`Automation (standard-cell and gate-array libraries), and Tanner Research (L-Edit).
`The programmable ASIC design examples in Chapter 4-8 use tools from Compass,
`Synopsys, Actel, Altera, and Xilinx. The examples in Chapter 9 (covering low-level
`design entry) used tools from Exemplar, MINC, AMD, DC Berkeley, Compass,
`Capilano, Mentor Graphics Corporation, and Cadence Design Systems. The VHDL
`examples in Chapter 10 (VHDL) were checked using QuickVHDL from Mentor,
`V-System Plus from Model Technology, and Scout from Cpmpass. The Verilog
`examples in Chapter 11 were checked using Verilog-XL from Cadence, V-System
`Plus, and VeriWell from Wellspring Solutions. The logic synthesis examples in
`
`iii
`
`6
`
`

`
`iv
`
`PREFACE
`
`Chapter 12 were checked with the ASIC Synthesizer product family from Compass
`and tools from Mentor, Synopsys, and UC Berkeley. The simulation examples in
`Chapter 13 were checked with QuickVHDL, V-System/Plus, PSpice, Verilog-XL,
`Design Works from Capilano Computing, CompassSim, QSim, MixSim, and
`HSPICE. The test examples in Chapter 14 were checked using test software from
`Compass, Cadence, Mentor, Synopsys and Capilano's DesignWorks. The physical
`design examples in Chapters 15-17 were generated and tested using Preview, Gate
`Ensemble, and Cell Ensemble (Cadence) as well as ChipPlanner, ChipCompiler,
`and PathFinder (Compass). All these tools are installed at the University of Hawaii.
`I wrote the text using FrameMaker. This allows me to project the text and fig(cid:173)
`ures using an LCD screen and an overhead projector. I used a succession of Apple
`Macintosh computers: a PowerBook 145, a 520, and lastly a 3400 with 144MB of
`RAM, which made it possible for me to create updates to the index in just under
`one minute. Equations are "live" in FrameMaker. Thus,
`book thickness = #pages x 0.0015 in./page::::: (1000) (1.5 x 10-3) = 1.5 in.
`
`can be updated in a lecture and the new result displayed. The circuit layouts are
`color EPS files with enhanced B&W PICT previews created using L-Edit from
`Tanner Research. All of the Verilog and VHDL code examples, compiler and simula(cid:173)
`tion input/output, and the layout CIF that were used in the final version are included
`as conditional (hidden) text in the FrameMaker document, which is approximately
`200MB and just over 6,000 pages (my original source material spans fourteen
`560MB optical disks). Software can operate on the hidden text, allowing, for exam(cid:173)
`ple, a choice of simulators to run the HDL code live in class. I converted draft ver(cid:173)
`sions of the VHDL and Verilog LRMs and related standards to FrameMaker and
`built hypertext links to my text, but copyright problems will have to be solved
`before this type of material may be published. I drew all the figures using
`FreeHand. They are "layered" allowing complex drawings to be built-up slowly or
`animated by turning layers on or off. This is difficult to utilize in book form, but can
`be done live in the classroom.
`A course based on FPGAs can use Chapter 1 and Chapters 4-8. A course using
`commercial semicustom ASIC design tools may use Chapters 1-2 or Chapters 1-3
`and then skip to Chapter 9 if you use schematic entry, Chapter 10 (if you use
`VHDL), or Chapter 11 (if you use Verilog) together with Chapter 12. All classes can
`use Chapters 13 and 14. FPGA-based classes may skim Chapters 15-17, but
`classes in semicustom design should cover these chapters. The chapter dependen(cid:173)
`cies-Y (X) means Chapter Y depends on X-are approximately: 1, 2(1), 3(2),
`4(2), 5(4), 6(5), 7(6), 8(7), 9(2), 10(2), 11(2), 12(10 or 11), 13(2), 14(13), 15(2),
`16(15), 17(16).
`I used the following references to help me with the orthography of complex
`terms, style, and punctuation while writing: Merriam-Webster's Collegiate Dictio(cid:173)
`nary, 10th edition, 1996, Springfield, MA: Merriam-Webster, ISBN 0-87779-709-9,
`PE1628.M36; The Chicago Manual of Style, 14th edition, Chicago: University of
`
`7
`
`

`
`PREFACE
`
`v
`
`Chicago Press, 1993, ISBN 0-226-10389-7, Z253.U69; and Merriam-Webster's
`Standard American Style Manual, 1985, Springfield, MA: Merriam-Webster, ISBN
`0-87779-133-3, PN147.W36. A particularly helpful book on technical writing is
`BUGS in Writing by Lyn Dupre, 1995, Reading, MA: Addison-Wesley, ISBN 0-201-
`60019-6, PE1408.D85 (Lyn's book grew from her unpublished work, Style SomeX,
`which I used).
`The bibliography at the end of each chapter provides alternative sources if you
`cannot find what you are looking for. I have included the International Standard
`Book Number1 (ISBN) and Library of Congress (LOC) Call Number for books, and
`the International Standard Serial Number2 (ISSN) for journals (see the LOC infor(cid:173)
`mation system, LOCIS, at http: / /www.loc.gov). I did not include references to
`material that I could not find myself (except where I have noted in the case of new
`or as yet unpublished books). The electronic references given in this text have (a
`last) access date of 4/19/97 and omit enclosing <> if the reference does not include
`spaces.
`I receive a tremendous level of support and cooperation from industry in my
`work. I thank the following for help with this project: Cynthia Benn and Lyn Dupre
`for editing; Helen Goldstein, Peter Gordon, Susan London-Payne, Tracy Russ, and
`Juliet Silveri, all at Addison-Wesley; Matt Bowditch and Kim Arney at Argosy;
`Richard Lyon, Don North, William Rivard, Glen Stone, the managers of the Newton
`group, and many others at Apple Computer who provided financial support; Apple
`for providing support in the form of software and computers; Bill Becker, Fern
`Forcier, Donna Isidro, Mike Kliment, Paul McLellan, Tom Schaefer, Al Stein, Rich
`Talburt, Bill Walker, and others at Compass Design Automation and VLSI
`Technology for providing the opportunity for me to work on this book over many
`years and allowing me to test material inside these companies and on lecture tours
`they sponsored; Chuck Seitz at Caltech; Joseph Cavallaro, Bernie Chern, Jerry
`Dillion, Mike Foster, and Paul Hulina at the NSF; the NSF for financial support with
`a Presidential Young Investigator Award; Jim Rowson and Doug Fairbairn;
`Constantine Anagnostopolous, Pin Tschang and members of the ASIC design
`groups at Kodak for financial support; the disk-drive design group at Digital Equip(cid:173)
`ment Corp. (Massachusetts), Hewlett-Packard, and Sun Microsystems for financial
`support; Ms. MOSIS and all of the staff at MOSIS who each have helped me at one
`point or another by providing silicon, technical support, and documentation; Bob
`Brodersen, Roger Howe, Randy Katz, and Ed Lee of UC Berkeley for help while I
`was visiting UCB; James Plummer of Stanford, for providing me with access to the
`Terman Engineering Library as a visiting scholar, as well as Abbas EI Gamal and
`Paul Losleben, also at Stanford, for help on several occasions; Don Bouldin at
`University of Tennessee; Krzysztof Kozminski at MCNC for providing Uncle lay-
`
`I A code that uniquely identifies a book, the tenth and last digit is a check digit.
`2 This number uniquely identifies a serial (a magazine, a journal, and so on). It is a seven(cid:173)
`digit number with an eighth check digit (which may be the roman numeral X, the value ten).
`
`8
`
`

`
`vi
`
`PREFACE
`
`out software; Gershom Kedem at Duke University for the public domain tools his
`group has written; Sue Drouin, Jose De Castro, and others at Mentor Graphics
`Corporation in Oregon for providing documentation and tools; Vahan Kasardjhan,
`Gail Grego, Michele Warthen, Steve Gardner, and others at the University Program
`at Cadence Design Systems in San Jose who helped with tools, documentation, and
`support; Karen Dorrington and the Cadence group in Massachusetts; Andy Haines,
`Tom Koppin, Sherri Mieth, Velma Miller, Robert Nalesnik, Mike Sarpa, Telle Whit(cid:173)
`ney, and others at Actel for software, hardware, parts, and documentation; Peter
`Alfke, Leslie Baxter, Brad Fawcett, Chris Kingsley, Karlton Lau, Rick Mitchell,
`Scott Nance, and Richard Ravel at Xilinx for support, parts, software, and documen(cid:173)
`tation; Greg Hedmann at NorCompfor data on FPGAs; Anna Acevedo, Suzanne
`Bailey, Antje MacNaughton, Richard Terrell, and Altera for providing software,
`hardware programmers, parts, and documentation; the documentation group and
`executive management at LSI Logic for tools, libraries, and documentation; Toshiba,
`NEC, AT&T/NCR, Lucent, and Hitachi (for documentation); NEC for their visiting
`scholar program at UH; Fred Furtek, Oscar Naval, and Claire Pinkham at
`Concurrent Logic, Randy Fish at Crosspoint, and Gary Banta at Plus Logic-all for
`documentation; Paul Titchener and others at Comdisco (now part of Cadence Design
`Systems) for providing design tools; John Tanner and his staff at Tanner Research
`for providing their tools and documentation; Mahendra Jain and Nanci Magoun,
`who let me debug early prototypes at the IDEA conference organized by ASIC
`Technology and News; Exemplar for providing documentation on its tools; MINC
`for providing a copy of its FPGA software and documentation; Claudia Traver and
`Synopsys for tools and documentation; Mentor Graphics Corporation for providing
`its complete range of software; Alain Hanover and others at ViewLogic for provid(cid:173)
`ing tools; Mary Shepherd and Jerry Walker at IEEE for help with permissions; Meta
`Software for providing HSPICE; Chris Dewhurst and colleagues at Capilano
`Computing for its design tools; Greg Seltzer (Model Technology) and Charley
`Rowley for providing V-System Plus with online documentation prototypes;
`Farallon and Telebit for the software and hardware I used for early experiments
`with telelectures. Many research students at the University of Hawaii helped me
`throughout this project including: Chin Huang, Clem Portmann, Christeen Gray,
`Karlton Lau, Jon Otaguro, Moe Lwin, Troy Stockstad, Ron Jorgenson, Derwin
`Mattos, William Rivard, Wendy Ching, Anil Aggarwal, Sudhakar Jilla, Linda Xu,
`Angshuman Saha, Harish Pareek, Claude van Ham, Wen Huang, Kumar Vadhri,
`Yan Zhong, Yatin Acharya, and Barana Ranaweera. Each of the classes that used
`early versions of this text at the University of Hawaii at Manoa have also contrib(cid:173)
`uted by finding errors. The remaining errors are mine.
`Links to figures, software, code, problem solutions, and other resources for this
`book may be found at:
`http://www.awl.com/cp/authors/smithm/asics/asics.html.
`
`Michael John Sebastian Smith
`Palo Alto and Honolulu, 1997
`
`9
`
`

`
`CONT NTS
`
`1 INTRODUCTION TO ASICs 1
`
`1.1
`
`1.2
`1.3
`1.4
`
`1.5
`1.6
`1.7
`1.8
`1.9
`
`1.1.8
`
`Types of ASICs 4
`1.1.1
`Full-Custom ASICs 5
`1.1.2
`Standard-Cell-Based ASICs 6
`1.1.3
`Gate-Array-Based ASICs 11
`1.1.4
`Channeled Gate Array 12
`1.1.5
`Channelless Gate Array 12
`1.1.6
`Structured Gate Array 13
`1.1.7
`Programmable Logic
`Devices 14
`Field-Programmable Gate
`Arrays 16
`Design Flow 16
`Case Study 18
`Economics of ASICs 20
`1.4.1
`Comparison Between ASIC
`Technologies 20
`Product Cost 20
`1.4.2
`ASIC Fixed Costs 21
`1.4.3
`ASIC Variable Costs 25
`1.4.4
`ASIC Cell Libraries 27
`Summary 30
`Problems 31
`Bibliography 36
`References 38
`
`2.1
`
`2 CMOS LOGIC 39
`CMOS Transistors 41
`P-Channel Transistors 45
`2.1.1
`2.1.2
`Velocity Saturation 45
`SPICE Models 47
`2.1.3
`Logic Levels 47
`2.1.4
`The CMOS Process 49
`2.2.1
`Sheet Resistance 55
`CMOS Design Rules 58
`Combinational Logic Cells 60
`
`2.2
`
`2.3
`2.4
`
`Pushing Bubbles 63
`2.4.1
`Drive Strength 65
`2.4.2
`2.4.3
`Transmission Gates 66
`Exclusive-OR Cell 69
`2.4.4
`Sequential Logic Cells 70
`2.5.1
`Latch 70
`2.5.2
`Flip-Flop 71
`2.5.3
`Clocked Inverter 73
`Datapath Logic Cells 75
`2.6.1
`Datapath Elements 77
`2.6.2
`Adders 79
`2.6.3
`A Simple Example 85
`2.6.4
`Multipliers 87
`2.6.5
`Other Arithmetic Systems 94
`2.6.6
`Other Datapath Operators 95
`I/O Cells 99
`Cell Compilers 102
`Summary 102
`Problems 103
`Bibliography 113
`References 114
`
`2.5
`
`2.6
`
`2.7
`2.8
`2.9
`2.10
`2.11
`2.12
`
`3 ASIC LIBRARY DESIGN 117
`
`3.1
`3.2
`
`3.3
`
`Transistors as Resistors 117
`Transistor Paras-itic Capacitance 122
`3.2.1
`Junction Capacitance 124
`3.2.2
`Overlap Capacitance 124
`3.2.3
`Gate Capacitance 124
`3.2.4
`Input Slew Rate 126
`Logical Effort 129
`3.3.1
`Predicting Delay 134
`3.3.2
`Logical Area and Logical
`Efficiency 134
`Logical Paths 135
`Multistage Cells 137
`Optimum Delay 138
`Optimum Number of Stages 140
`
`3.3.3
`3.3.4
`3.3.5
`3.3.6
`
`vii
`
`10
`
`

`
`viii
`
`CONTENTS
`
`3.4
`3.5
`3.6
`3.7
`3.8
`3.9
`3.10
`3.11
`3.12
`
`Library-Cell Design 141
`Library Architecture 142
`Gate-Array Design 144
`Standard-Cell Design 150
`Datapath-Cell Design 152
`Summary 155
`Problems 155
`Bibliography 167
`References 168
`
`4 PROGRAMMABLE ASICs 169
`
`4.1
`
`4.2
`4.3
`4.4
`
`4.5
`4.6
`4.7
`
`4.8
`4.9
`4.10
`4.11
`
`The Antifuse 170
`4.1.1
`Metal-Metal Antifuse 172
`Static RAM 174
`EPROM and EEPROM Technology 174
`Practical Issues 176
`4.4.1
`FPGAs in Use 177
`Specifications 178
`PREP Benchmarks 179
`FPGA Economics 180
`4.7.1
`FPGA Pricing 180
`4.7.2
`Pricing Examples 183
`Summary 184
`Problems 185
`Bibliography 190
`References 190
`
`5 PROGRAMMABLE ASIC
`LOGIC CELLS 191
`
`5.1
`
`5.2
`
`5.1.3
`
`5.1.4
`
`Actel ACT 191
`5.1.1
`ACT 1 Logic Module 191
`5.1.2
`Shannon's Expansion
`Theorem 192
`Multiplexer Logic as Function
`Generators 193
`ACT 2 and ACT 3 Logic
`Modules 196
`Timing Model and Critical
`Path 197
`Speed Grading 201
`5.1.6
`Worst-Case Timing 201
`5.1.7
`Actel Logic Module Analysis 204
`5.1.8
`Xilinx LCA 204
`5.2.1
`XC3000 CLB 204
`5.2.2
`XC4000 Logic Block 206
`
`5.1.5
`
`5.2.3
`XC5200 Logic.Block 207
`Xilinx CLB Analysis 207
`5.2.4
`Altera FLEX 209
`Altera MAX 209
`5.4.1
`Logic Expanders 211
`5.4.2
`Timing Model 215
`5.4.3
`Power Dissipation in Complex
`PLDs 217
`Summary 218
`Problems 224
`Bibliography 229
`References 230
`
`5.3
`5.4
`
`5.5
`5.6
`5.7
`5.8
`
`6 PROGRAMMABLE
`ASIC 1/0 CELLS 231
`
`6.1
`
`6.2
`
`6.3
`
`6.4
`
`6.5
`
`6.6
`
`6.7
`
`6.8
`6.9
`6.10
`6.11
`6.12
`
`DC Output 232
`6.1.1
`Totem-Pole Output 234
`6.1.2
`Clamp Diodes 235
`AC Output 235
`6.2.1
`Supply Bounce 239
`6.2.2
`Transmission Lines 240
`DC Input 243
`6.3.1
`Noise Margins 244
`6.3.2
`Mixed-Voltage Systems 246
`AC Input 248
`6.4.1
`Metastability 249
`Clock Input 253
`6.5.1
`Registered Inputs 253
`Power Input 255
`6.6.1
`Power Dissipation 256
`6.6.2
`Power-On Reset 258
`Xilinx 1/0 Block 258
`6.7.1
`Boundary Scan 260
`Other I/O Cells 261
`Summary 262
`Problems 263
`Bibliography 272
`References 273
`
`7 PROGRAMMABLE
`ASIC INTERCONNECT 275
`
`7.1
`
`Actel ACT 275
`7.1.1
`Routing Resources 276
`7.1.2
`Elmore's Constant 278
`
`11
`
`

`
`7.1.3
`
`7.1.4
`
`RC Delay in Antifuse
`Connections 280
`Antifuse Parasitic
`Capacitance 281
`ACT 2 and ACT 3
`Interconnect 283
`Xilinx LCA 284
`Xilinx EPLD 288
`Altera MAX 5000 and 7000 289
`Altera MAX 9000 290
`Altera FLEX 291
`Summary 292
`Problems 294
`Bibliography 297
`References 297
`
`7.1.5
`
`7.2
`7.3
`7.4
`7.5
`7.6
`7.7
`7.8
`7.9
`7.10
`
`8 PROGRAMMABLE
`ASIC DESIGN SOFTWARE 299
`
`8.1
`
`8.2
`
`8.3
`
`8.4
`8.5
`8.6
`
`8.7
`
`Design Systems 299
`8.1.1
`Xilinx 301
`8.1.2
`Actel 303
`8.1.3
`Altera 303
`Logic Synthesis 304
`8.2.1
`FPGA Synthesis 305
`The Halfgate ASIC 307
`8.3.1
`Xilinx 307
`8.3.2
`Actel 310
`8.3.3
`Altera 310
`8.3.4
`Comparison 315
`Summary 316
`Problems 316
`Bibliography 320
`8.6.1
`FPGA Vendors 321
`8.6.2
`Third-Party Software 323
`References 326
`
`9 LOW-LEVEL
`DESIGN ENTRY 327
`
`9.1
`
`Schematic Entry 328
`9.1.1
`Hierarchical Design 330
`9.1.2
`The Cell Library 330
`9.1.3
`Names 332
`9.1.4
`Schematic Icons and Symbols
`333
`Nets 336
`
`9.1.5
`
`CONTENTS
`
`ix
`
`9.1.6
`
`9.1.7
`9.1.8
`
`Schematic Entry for ASICs and
`PCBs 336
`Connections 338
`Vectored Instances and
`Buses 338
`Edit-in-Place 340
`9.1.9
`Attributes 341
`9.1.10
`Netlist Screener 341
`9.1.11
`Schematic-Entry tools 343
`9.1.12
`Back-Annotation 345
`9.1.13
`Low-Level Design Languages 345
`9.2.1
`ABEL 346
`9.2.2
`CUPL 348
`9.2.3
`PALASM 350
`PLA Tools 353
`EDIF 355
`EDIF Syntax 355
`9.4.1
`An EDIF Netlist Example 357
`9.4.2
`9.4.3
`An EDIF Schematic Icon 359
`9.4.4
`An EDIF Example 365
`CFI Design Representation 369
`9.5.1
`CFI Connectivity Model 370
`Summary 373
`Problems 373
`Bibliography 376
`References 377
`
`9.2
`
`9.3
`9.4
`
`9.5
`
`9.6
`9.7
`9.8
`9.9
`
`10 VHDL 379
`
`10.1
`10.2
`
`10.3
`10.4
`10.5
`10.6
`
`A Counter 380
`A 4-bit Multiplier 381
`10.2.1
`An 8-bit Adder 381
`10.2.2
`A Register Accumulator 381
`10.2.3
`Zero Detector 383
`10.2.4
`A Shift Register 384
`10.2.5
`A State Machine 384
`10.2.6
`A Multiplier 385
`10.2.7
`Packages and Testbench 388
`Syntax and Semantics of VHDL 390
`Identifiers and Literals 392
`Entities and Architectures 393
`Packages and Libraries 398
`10.6.1
`Standard Package 399
`10.6.2
`Std_logic_1164 Package 400
`10.6.3
`Textio Package 402
`10.6.4 Other Packages 403
`10.6.5
`Creating Packages 404
`
`12
`
`

`
`x
`
`CONTENTS
`
`10.7
`
`Interface Declarations 405
`Port Declaration 406
`10.7.1
`10.7.2 Generics 410
`Type Declarations 411
`10.8
`10.9 Other Declarations 413
`10.9.1
`Object Declarations 414
`10.9.2
`Subprogram Declarations 415
`10.9.3
`Alias and Attribute
`Declarations 418
`Predefined Attributes 419
`10.9.4
`10.10 Sequential Statements 419
`10.10.1 Wait Statement 421
`10.10.2 Assertion and Report State-
`ments 423
`10.10.3 Assignment Statements 424
`10.10.4 Procedure Call 426
`If Statement 427
`10.10.5
`10.10.6 Case Statement 428
`10.10.7 Other Sequential Control
`Statements 429
`10.11 Operators 430
`10.12 Arithmetic 432
`10.12.1
`IEEE Synthesis Packages 434
`10.13 Concurrent Statements 437
`10.13.1 Block Statement 438
`10.13.2 Process Statement 440
`10.13.3 Concurrent Procedure Call 441
`10.13.4 Concurrent Signal
`Assignment 442
`10.13.5 Concurrent Assertion State-
`ment 443
`10.13.6 Component Instantiation 444
`10.13.7 Generate Statement 444
`10.14 Execution 445
`10.15 Configurations and Specifications 447
`10.16 An Engine Controller 449
`10.17 Summary 456
`10.18 Problems 459
`10.19 Bibliography 477
`10.20 References 478
`
`11 VERILOG HDl 479
`
`11.1
`11.2
`
`A Counter 480
`Basics of the Verilog Language 482
`Verilog Logic Values 483
`11.2.1
`Verilog Data Types 483
`11.2.2
`11.2.3 Other Wire Types 486
`
`11.4
`11.5
`
`11.6
`
`11.6.5
`
`11.7
`11.8
`
`11.9
`
`11.2.4 Numbers 486
`11.2.5
`Negative Numbers 488
`11.2.6
`Strings 489
`11.3 Operators 490
`Arithmetic 492
`11.3.1
`Hierarchy 494
`Procedures and Assignments 495
`Continuous Assignment
`11.5.1
`Statement 496
`Sequential Block 497
`11.5.2
`Procedural Assignments 498
`11.5.3
`Timing Controls and Delay 498
`11.6.1
`Timing Control 498
`11.6.2
`Data Slip 501
`11.6.3 Wait Statement 502
`11.6.4
`Blocking and Nonblocking
`Assignments 503
`Procedural Continuous
`Assignment 504
`Tasks and Functions 506
`Control Statements 506
`11.8.1
`Case and If Statement 506
`11.8.2
`Loop Statement 507
`Disable 508
`11.8.3
`11.8.4
`Fork and Join 509
`Logic-Gate Modeling 509
`11.9.1
`Built-in Logic Models 509
`11.9.2
`User-Defined Primitives 510
`11.10 Modeling Delay 512
`11.10.1 Net and Gate Delay 512
`11.10.2 Pin-to-Pin Delay 513
`11.11 Altering Parameters 515
`11.12 A Viterbi Decoder 515
`11.12.1 Viterbi Encoder 515
`11.12.2 The Received Signal 519
`11.12.3 Testing the System 521
`11.12.4 Verilog Decoder Model 523
`11.13 Other Verilog Features 532
`11.13.1 Display Tasks 533
`11.13.2 File 1/0 Tasks 533
`11.13.3 Timescale, Simulation, and
`Timing-Check Tasks 534
`11.13.4 PLA Tasks 537
`11.13.5 Stochastic Analysis Tasks 538
`11.13.6 Simulation Time Functions 539
`11.13.7 Conversion Functions 539
`11.13.8 Probability Distribution
`Functions 540
`
`13
`
`

`
`11.13.9 Programming Language
`Interface 541
`11.14 Summary 541
`11.15 Problems 543
`11.15.1 The Viterbi Decoder 556
`11.16 Bibliography 557
`11.17 References 557
`
`12 lOGIC SYNTHESIS 559
`
`12.1
`12.2
`
`12.3
`12.4
`
`12.5
`
`12.6
`
`A Logic-Synthesis Example 560
`A Comparator/MUX 561
`12.2.1
`An Actel Version of the
`Comparator/MUX 567
`Inside a Logic Synthesizer 569
`Synthesis of the Viterbi Decoder 572
`ASIC I/O 572
`12.4.1
`Flip-Flops 575
`12.4.2
`The Top-Level Model 575
`12.4.3
`Verilog and Logic Synthesis 580
`Verilog Modeling 580
`12.5.1
`Delays in Verilog 581
`12.5.2
`Blocking and Nonblocking
`12.5.3
`Assignments 582
`12.5.4 Combinational Logic in
`Verilog 582
`12.5.5 Multiplexers In Verilog 584
`The Verilog Case
`12.5.6
`Statement 585
`Decoders In Verilog 586
`12.5.7
`Priority Encoder in Verilog 587
`12.5.8
`Arithmetic in Verilog 587
`12.5.9
`12.5.10 Sequential Logic in Veri log 589
`12.5.11 Component Instantiation in
`Verilog 590
`12.5.12 Datapath Synthesis in
`Verilog 591
`VHDL and Logic Synthesis 593
`Initialization and Reset 593
`12.6.1
`12.6.2
`Combinational Logic Synthesis
`in VHDL 594
`12.6.3 Multiplexers in VHDL 594
`Decoders in VHDL 595
`12.6.4
`Adders in VHDL 597
`12.6.5
`Sequential Logic in VHDL 597
`12.6.6
`Instantiation in VHDL 598
`12.6.7
`Shift Registers and Clocking in
`12.6.8
`VHDL 601
`
`CONTENTS
`
`xi
`
`12.6.9
`
`12.7
`
`12.9
`
`Adders and Arithmetic
`Functions 603
`12.6.10 Adder/Subtracter and Don't
`Cares 604
`Finite-State Machine Synthesis 605
`12.7.1
`FSM Synthesis in Veri log 607
`12.7.2
`FSM Synthesis in VHDL 608
`12.8 Memory Synthesis 611
`12.8.1 Memory Synthesis in
`Verilog 611
`12.8.2 Memory Synthesis in VHDL 612
`The Multiplier 614
`12.9.1 Messages During
`Synthesis 617
`12.10 The Engine Controller 619
`12.11 Performance-Driven Synthesis 620
`12.12 Optimization of the Viterbi Decoder 625
`12.13 Summary 628
`12.14 Problems 629
`12.15 Bibliography 638
`12.16 References 639
`
`13 SIMULATION 641
`
`13.1
`13.2
`
`13.3
`
`13.4
`
`13.5
`
`13.6
`
`Types of Simulation 641
`The Comparator/MUX Example 643
`13.2.1
`Structural Simulation 644
`13.2.2
`Static Timing Analysis 647
`13.2.3 Gate-Level Simulation 648
`13.2.4 Net Capacitance 650
`Logic Systems 652
`Signal Resolution 653
`13.3.1
`13.3.2
`Logic Strength 653
`How Logic Simulation Works 656
`VHDL Simulation Cycle 658
`13.4.1
`13.4.2
`Delay 658
`Cell Models 659
`13.5.1
`Primitive Models 659
`Synopsys Models 660
`13.5.2
`13.5.3
`Verilog Models 661
`VHDL Models 663
`13.5.4
`13.5.5
`VITAL Models 664
`SDF in Simulation 667
`13.5.6
`Delay Models 669
`13.6.1
`Using a Library Data Book 670
`Input-Slope Delay Model 672
`13.6.2
`Limitations of Logic
`13.6.3
`Simulation 674
`
`14
`
`

`
`xii
`
`CONTENTS
`
`13.7
`
`13.8
`
`Static Timing Analysis 675
`Hold Time 678
`13.7.1
`Entry Delay 679
`13.7.2
`Exit Delay 680
`13.7.3
`External Setup Time 681
`13.7.4
`Formal Verification 682
`13.8.1
`An Example 682
`13.8.2 Understanding Formal
`Verification 684
`13.8.3
`Adding an Assertion 685
`13.8.4 Completing a Proof 687
`13.9
`Switch-Level Simulation 688
`13.10 Transistor-Level Simulation 689
`13.10.1 A PSpice Example 689
`13.10.2 SPICE Models 692
`13.11 Summary 696
`13.12 Problems 696
`13.13 Bibliography 708
`13.14 References 708
`
`14 TEST 711
`
`14.1
`14.2
`
`14.3
`
`14.4
`
`The Importance of Test 712
`Boundary-Scan Test 714
`14.2.1
`BST Cells 716
`14.2.2
`BST Registers 718
`14.2.3
`Instruction Decoder 719
`14.2.4
`TAP Controller 722
`14.2.5
`Boundary-Scan Controller 724
`14.2.6
`A Simple Boundary-Scan
`Example 727
`BSDL 732
`14.2.7
`Faults 736
`.14.3.1
`Reliability 736
`Fault Models 737
`14.3.2
`14.3.3
`Physical Faults 738
`14.3.4
`Stuck-at Fault Model 740
`14.3.5
`Logical Faults 741
`14.3.6
`IDDQ Test 742
`14.3.7
`Fault Collapsing 743
`14.3.8
`Fault-Collapsing Example 743
`Fault Simulation 745
`14.4.1
`Serial Fault Simulation 747
`14.4.2
`Parallel Fault Simulation 747
`14.4.3 Concurrent Fault
`Simulation 747
`14.4.4 Nondeterministic Fault
`Simulation 748
`
`14.4.5
`14.4.6
`
`14.4.7
`14.4.8
`
`14.4.9
`
`14.8.3
`14.8.4
`14.8.5
`
`14.5
`
`14.6
`14.7
`
`14.8
`
`Fault-Simulation Results 748
`Fault-Simulator Logic Systems
`749
`Hardware Acceleration 751
`A Fault-Simulation Example
`752
`Fault Simulation in an ASIC
`Design Flow 754
`Automatic Test-Pattern Generation 755
`14.5.1
`The D-Calculus 755
`14.5.2
`A Basic A TPG Algorithm 757
`14.5.3
`The PODEM Algorithm 759
`14.5.4
`Controllability and
`Observability 761
`Scan Test 764
`Built-in Self-test 766
`14.7.1
`LFSR 766
`14.7.2
`Signature Analysis 766
`14.7.3
`A Simple BIST Example 767
`14.7.4
`Aliasing 768
`14.7.5
`LFSR Theory 771
`14.7.6
`LFSR Example 773
`14.7.7 MISR 775
`A Simple Test Example 778
`14.8.1
`Test-Logic Insertion 778
`14.8.2
`How the Test Software
`Works 780
`ATVG and Fault Simulation 787
`Test Vectors 787
`Production Tester Vector
`Formats 789
`Test Flow 791
`14.8.6
`The Viterbi Decoder Example 791
`14.9
`14.10 Summary 794
`14.11 Problems 794
`14.12 Bibliography 800
`14.13 References 801
`
`15 ASIC CONSTRUCTION 805
`
`15.1
`15.2
`
`15.3
`15.4
`15.5
`
`Physical Design 805
`CAD Tools 807
`15.2.1 Methods and Algorithms 808
`System Partitioning 809
`Estimating ASIC Size 811
`Power Dissipation 816
`15.5.1
`Switching Current 816
`15.5.2
`Short-Circuit Current 817
`
`15
`
`

`
`15.5.3
`
`15.6
`
`15.7
`
`Subthreshold and Leakage
`Current 818
`FPGA Partitioning 820
`15.6.1
`ATM Simulator 820
`15.6.2
`Automatic Partitioning with
`FPGAs 823
`Partitioning Methods 824
`15.7.1
`Measuring Connectivity 824
`15.7.2
`A Simple Partitioning
`Example 826
`15.7.3 Constructive Partitioning 827
`15.7.4
`Iterative Partitioning
`Improvement 828
`The Kernighan-Lin
`Algorithm 829
`The Ratio-Cut Algorithm 834
`15.7.6
`The Look-ahead Algorithm 835
`15.7.7
`Simulated Annealing 836
`15.7.8
`15.7.9 Other Partitioning
`Objectives 837
`Summary 838
`15.8
`Problems 838
`15.9
`15.10 Bibliography 850
`15.11 References 851
`
`15.7.5
`
`16 FLOORPLANNING
`AND PLACEMENT 853
`
`16.1
`
`16.2
`
`Floorplanning 853
`16.1.1
`Floorplanning Goals and
`Objectives 854
`16.1.2 Measurement of Delay in
`Floorplanning 856
`Floorplanning Tools 859
`16.1.3
`16.1.4 Channel Definition 861
`I/O and Power Planning 864
`16.1.5
`16.1.6 Clock Planning 869
`Placement 873
`16.2.1
`Placement Terms and
`Definitions 873
`Placement Goals and
`Objectives 876
`16.2.3 Measurement of Placement
`Goals and Objectives 877
`Placement Algorithms 882
`Eigenvalue Placement
`Example 885
`Iterative Placement
`Improvement 887
`
`16.2.4
`16.2.5
`
`16.2.6
`
`16.2.2
`
`CONTENTS
`
`xiii
`
`16.2.7
`
`16.2.8
`
`16;2.9
`
`Placement Using Simulated
`Annealing 890
`Timing-Driven Placement
`Methods 891
`A Simple Placement
`Example 893
`Physical Design Flow 894
`Information Formats 895
`16.4.1
`SDF for Floorplanning and
`Placement 895
`PDEF 896
`16.4.2
`LEF and DEF 897
`16.4.3
`Summary 898
`Problems 898
`Bibliography 906
`References 9