UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`SONY CORPORATION, SONY ELECTRONICS INC.,
`SONY MOBILE COMMUNICATIONS AB, and
`SONY MOBILE COMMUNICATIONS (USA) INC.
`Petitioners,
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`v.
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`MEMORY INTEGRITY, LLC,
`Patent Owner.
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`Case IPR2015-00158
`Patent 7,296,121 B2
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`SUPPLEMENTAL EXPERT DECLARATION OF
`PROFESSOR DANIEL J. SORIN
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`SONY CORPORATION, SONY ELECTRONICS INC.,
`SONY MOBILE COMMUNICATIONS AB, and
`SONY MOBILE COMMUNICATIONS (USA) INC.
`Petitioners,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`
`
`
`
`
`
`
`
`
`
`Case IPR2015-00158
`Patent 7,296,121 B2
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`SUPPLEMENTAL EXPERT DECLARATION OF
`PROFESSOR DANIEL J. SORIN
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`No. IPR2015-158
`Supp. Expert Decl. of Daniel J. Sorin
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`I.
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`INTRODUCTION
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`1.
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`I, Professor Daniel J. Sorin, have been retained by counsel for Sony
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`Corporation, Sony Mobile Communications AB, Sony Mobile
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`Communications (USA) Inc., and Sony Electronics Inc. (collectively,
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`“Petitioners”).
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`2.
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`I submit this declaration in support of Petitioner’s Reply to Patent Owner’s
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`Response to Petition in the Inter Partes Review of U.S. Pat. No. 7,296,121,
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`No. IPR2015-00158.
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`II. QUALIFICATIONS
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`3.
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`I hold a Ph.D. in Electrical and Computer Engineering from the University
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`of Wisconsin—Madison (awarded in 2002). My doctoral dissertation
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`focused on checkpointing/recovery of multiprocessors with cache-coherent
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`shared memory.
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`4.
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`I am a Professor in the Department of Electrical and Computer Engineering
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`at Duke University. Prior to being a Professor, I was an Associate Professor
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`in the Department of Electrical and Computer Engineering at Duke
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`University (2009-2015), an Assistant Professor in the Department of
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`Electrical and Computer Engineering at Duke University (2002-2009), a
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`Research Assistant in the Computer Sciences Department at the University
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`of Wisconsin—Madison (1996-2002), and a Teaching Assistant in the
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`No. IPR2015-158
`Supp. Expert Decl. of Daniel J. Sorin
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`Department of Electrical and Computer Engineering at the University of
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`Wisconsin—Madison (1996-1997).
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`5.
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`I am the author or co-author of two books: “A Primer on Memory
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`Consistency and Cache Coherence” Synthesis Lectures on Computer
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`Architecture, Morgan & Claypool Publishers, 2011; and “Fault Tolerant
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`Computer Architecture” Synthesis Lectures on Computer Architecture,
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`Morgan & Claypool Publishers, 2009.
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`6.
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`I have published over 70 technical articles, including over 20 related to
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`cache coherence technology.
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`7.
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`I have over 16 years of experience in the design and implementation of
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`cache coherency systems and protocols in multi-processor computer
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`systems.
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`8. My curriculum vitae more fully describes my education, professional
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`experience, and relevant publications. See Sony-1014.
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`III. MATERIALS CONSIDERED
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`9.
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`I have reviewed U.S. Pat. No. 7,296,121 (the “’121 Patent”) including its
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`claims.
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`10.
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`I have reviewed U.S. Patent No. 7,698,509 to Koster (“Koster”). I
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`understand Koster is prior art to at least claims 19–24 of the ’121 Patent.
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`3
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`No. IPR2015-158
`Supp. Expert Decl. of Daniel J. Sorin
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`11.
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`I have reviewed all of the Exhibits entered thus far in IPR2015-00158,
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`including Sony-1001–1014; Memory Integrity-2001–2040; and Exhibit-
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`3001.
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`12.
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`I have reviewed the Patent Trial and Appeal Board’s (“Board”) Decision in
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`Institution in IPR2015-00158 (Paper No. 7) (“Institution Decision”).
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`13.
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`I have reviewed the Patent Owner’s Response to Petition in IPR2015-00158
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`(Paper No. 17) (“Response”).
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`IV. PERSON OF ORDINARY SKILL IN THE ART
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`14.
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`In the 2002–2004 timeframe, a person with ordinary skill in the art with
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`respect to the technology disclosed by the ’121 Patent would have a PhD
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`degree in Electrical Engineering, Computer Engineering, or Computer
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`Science or a MS degree and two to three years of industry experience in the
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`area of cache coherency in multi-processor computer systems.
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`15. Based upon my education and experience, I consider myself to be a person
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`of at least ordinary skill in the field of technology disclosed by the ’121
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`Patent. In forming the opinions that I express herein, I have adopted the
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`perspective of a person of ordinary skill in the art, as described in paragraph
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`4
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`14 above.
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`No. IPR2015-158
`Supp. Expert Decl. of Daniel J. Sorin
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`V. CLAIM CONSTRUCTION
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`16.
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`I understand that in rendering an opinion on claim construction, I am to
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`“interpret claims of an unexpired patent using the broadest reasonable
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`construction in light of the specification of the patent in which they appear.”
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`Institution Decision at 7.
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`17.
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`In the Institution Decision, with respect to the term “states associated with
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`selected ones of the cache memories” in claim 16 of the ’121 patent, the
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`Board stated that “the term is not limited to cache coherence protocol states
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`and is broad enough to include the condition of presence—i.e., what is
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`stored in cache memory.” Institution Decision at 10. I agree with this
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`construction. A person of ordinary skill in the art would understand the term
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`“states associated with selected ones of the cache memories” to not be
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`limited to cache coherence protocol states, and be broad enough to include
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`the condition of presence—i.e., what is stored in cache memory. In fact,
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`presence information alone (i.e., what is stored in cache memory), is enough
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`information for maintaining coherence in a simple cache coherence protocol.
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`18.
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`In the Response, with respect to the term “states” in claim 16 of the ’121
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`patent, the Patent Owner contends that “the appropriate construction of
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`states is limited to cache coherence states, and does not include mere
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`presence.” Response at 2. I disagree with this construction. The
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`No. IPR2015-158
`Supp. Expert Decl. of Daniel J. Sorin
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`appropriate construction of “states” is not limited to cache coherence states.
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`The appropriate construction of “states” includes mere presence— i.e., what
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`is stored in cache memory.
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`19.
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`In the Response, the Patent Owner cites to Sorin et al., A Primer on Memory
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`Consistency and Cache Coherence (2011) (Memory Integrity Exhibit 2010).
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`Response at 4. I am a co-author of this book. The Patent Owner discusses
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`several passages in this book and then proceeds to characterize the book by
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`stating that “[t]his interchangeable use of the term ‘states’ and ‘coherence
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`states’ and, use of the term ‘state’ alone to discuss the states of particular
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`cache coherence protocol, demonstrates that the term ‘state’ means a cache
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`coherence protocol state in the field of cache coherency.” Response at 4–5.
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`The Patent Owner’s characterization of this book is overly restrictive. While
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`this book provides examples of various types of “states,” it does not use the
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`term “state” to mean only a cache coherence protocol state. As examples,
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`the book uses the terms “final states of the memory” and “state of a
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`register.” Memory Integrity Exhibit 2010 at 3, 29. As used in these
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`examples, the term “state” does not refer to a cache coherence protocol state.
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`6
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`No. IPR2015-158
`Supp. Expert Decl. of Daniel J. Sorin
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`VI. KOSTER
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`20.
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`In the Institution Decision, the Board stated that “Koster’s tags indicate
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`where specific data is cached (i.e., the presence of data in specific locations),
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`information we have determined, for purposes of this decision, to be
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`included in the claimed subject matter.” Institution Decision at 23. I agree
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`with this statement. Under the correct construction of “states associated
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`with selected ones of the cache memories,” Koster discloses the limitation of
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`“probe filtering information representative of states associated with selected
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`ones of the cache memories” in claim 16. See Koster at 6:8–17; 7:3–6.
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`21.
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`In the Response, the Patent Owner appears to contend that under the Patent
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`Owner’s construction that “states” is limited to “cache coherence states,”
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`that Koster does not disclose “states.” I disagree with the Patent Owner’s
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`contention. Even assuming that “states” limited to “cache coherence states,”
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`Koster discloses “states” because Koster’s “shadow tag memory” may be
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`maintained as a “set-associative cache” which may use a MOESI cache
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`coherency protocol. Koster at 6:34-37. Through this disclosure, Koster
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`meets the claim limitation of “probe filtering information representative of
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`states associated with selected ones of the cache memories” in claim 16
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`under the Patent Owner’s construction of “states.”
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`7
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`No. IPR2015-158
`Supp. Expert Decl. of Daniel J. Sorin
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`I declare under penalty of perjury that the foregoing is true and correct.
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`Dated November
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`, 2015
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`____________________
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`Daniel J. Sorin
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`8
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