W.H. Gardner Jr. Associate Professor of Electrical and Computer Engineering
`
`Daniel J. Sorin
`
`Department of Electrical and Computer Engineering
`Duke University
`Box 90291
`Durham, NC 27708
`
`phone: (919) 660-5439
`fax: (919) 660-5293
`email:sorin@ee.duke.edu
`http://www.ee.duke.edu/~sorin
`
`Research Interests
`Multiprocessor computer architectures, with an emphasis on memory system design
`Fault tolerant computer architectures
`Verification-aware microprocessor design
`Architectures for emerging nanotechnologies
`Evaluation of system performance and dependability
`
`Education
`University of Wisconsin—Madison, Madison, WI
`Doctorate of Philosophy in Electrical and Computer Engineering, August 2002
`Advisor: David A. Wood
`University of Wisconsin—Madison, Madison, WI
`Master of Science in Electrical and Computer Engineering, May 1998
`Duke University, Durham, NC
`Bachelor of Science in Electrical and Computer Engineering, May 1996
`
`Honors and Awards
`Best Paper Award at 2014 International Symposium on High-Performance Computer Architecture
`Computing Community Consortium’s Computing Research Highlight of the Week, February 11-18,
`2011 [http://www.cra.org/ccc/rh-detouring.php]
`2011 Lois and John L. Imhoff Distinguished Teaching Award
`Paper chosen as one of IEEE Micro’s Top Picks from Computer Architecture Conferences, 2010
`Paper chosen as one of IEEE Micro’s Top Picks from Computer Architecture Conferences, 2007
`NSF Faculty Early Career Award, 2005
`Technology Research News’ Top of 2004 list for research performed by nanocomputing research group
`Warren Faculty Scholarship, Pratt School of Engineering, Duke University
`Outstanding Graduate Research Award, University of Wisconsin Department of Computer Sciences
`Intel Foundation Graduate Fellowship
`Phi Beta Kappa, Tau Beta Pi, and Eta Kappa Nu academic honor societies
`Senior Member of the IEEE
`
`1
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`Petition for Inter Partes Review of 
`U.S. Pat. No. 7,296,121
`IPR2015‐00158
`EXHIBIT
`Sony‐
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`Senior Member of the ACM
`
`Experience
`Associate Professor, Duke University, Department of Electrical and Computer Engineering and
`Department of Computer Science
`July 2009-present
`Assistant Professor, Duke University, Department of Electrical and Computer Engineering and
`Department of Computer Science
`September 2002-June 2009
`Research Assistant, University of Wisconsin—Madison, Computer Sciences Department
`August 1996-August 2002
`Teaching Assistant, University of Wisconsin—Madison, Dept. of Electrical and Computer Engr.
`August 1996-May 1997
`
`Books
`1. Daniel J. Sorin, Mark D. Hill, and David A. Wood. “A Primer on Memory Consistency and Cache
`Coherence.” Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2011.
`2. Daniel J. Sorin. “Fault Tolerant Computer Architecture.” Synthesis Lectures on Computer Architec-
`ture, Morgan & Claypool Publishers, 2009.
`
`Journal Publications
`1. Ralph Nathan and Daniel J. Sorin. “Argus-G: Comprehensive, Low-Cost Error Detection for
`GPGPU Cores.” Accepted for publication in Computer Architecture Letters, 2014.
`2. Milo M. K. Martin, Mark D. Hill, and Daniel J. Sorin. “Why On-Chip Cache Coherence Is Here to
`Stay.” Communications of the ACM, volume 55, number 7, July 2012, pages 78-89.
`3. Bogdan F. Romanescu, Alvin R. Lebeck, and Daniel J. Sorin. “Address Translation-Aware Memory
`Consistency.” IEEE Micro: Micro's Top Picks from Computer Architecture Conferences, volume 31,
`number 1, January/February 2011, pages 109-118.
`4. Meng Zhang, Alvin R. Lebeck, and Daniel J. Sorin. “Fractal Consistency: Architecting the Memory
`System to Facilitate Verification.” Computer Architecture Letters, volume 9, number 2, July-December
`2010, pages 61-64.
`5. Albert Meixner and Daniel J. Sorin. “Dynamic Verification of Memory Consistency in Cache-
`Coherent Multithreaded Computer Architectures.” IEEE Transactions on Dependable and Secure Com-
`puting (TDSC), volume 6, number 1, January-March 2009, pages 18-31.
`6. Fred A. Bower, Daniel J. Sorin, and Landon P. Cox. “The Impact of Dynamically Heterogeneous
`Multicore Processors on Thread Scheduling.” IEEE Micro, May/June 2008, pages 17-25.
`7. Albert Meixner, Michael E. Bauer, and Daniel J. Sorin. “Argus: Low-Cost, Comprehensive Detec-
`tion of Errors in Simple Cores.” IEEE Micro: Micro’s Top Picks from Computer Architecture Confer-
`ences, volume 28, number 1, January/February 2008, pages 52-59.
`8. Fred A. Bower, Daniel J. Sorin, and Sule Ozev. “Online Diagnosis of Hard Faults in Microproces-
`sors.” ACM Transactions on Architecture and Code Optimization (TACO), volume 4, number 2, June
`2007, article 8.
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`9. Tong Li, Alvin R. Lebeck, and Daniel J. Sorin. “Spin Detection Hardware for Improved Manage-
`ment of Multithreaded Systems.” IEEE Transactions on Parallel and Distributed Systems (TPDS), vol-
`ume 17, number 6, June 2006, pages 508-521.
`10. Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, and Daniel J. Sorin. “NANA: A Nano-Scale
`Active Network Architecture.” ACM Journal on Emerging Technologies in Computing Systems (JETC),
`volume 2, number 1, January 2006, pages 1-30.
`11. Fred A. Bower, Sule Ozev, and Daniel J. Sorin. “Autonomic Microprocessor Execution via Self-
`Repairing Arrays.” IEEE Transactions on Dependable and Secure Computing (TDSC), volume 2, num-
`ber 4, October-December 2005, pages 297-310.
`12. Chris Dwyer, Alvin R. Lebeck, and Daniel J. Sorin. “Self-Assembled Architecture and the Tempo-
`ral Aspects of Computing.” IEEE Computer, volume 38, number 1, January 2005, pages 56-64.
`13. Chris Dwyer, Vijeta Johri, Jaidev P. Patwardhan, Alvin R. Lebeck, and Daniel J. Sorin. “Design
`Tools for Self-assembling Nanoscale Technology”, Institute of Physics Nanotechnology, volume 15,
`number 9, September 2004, pages 1240-1245. [Paper chosen by Technology Research News as part
`of their Top of 2004 list]
`14. Alaa R. Alameldeen, Milo M. K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Daniel J. Sorin,
`Mark D. Hill, and David A. Wood. “Simulating a $2M Commercial Server on a $2K PC.” IEEE Com-
`puter, volume 36, number 2, February 2003, pages 50-57.
`15. Daniel J. Sorin, Jonathan L. Lemon, Derek L. Eager, and Mary K. Vernon. “Analytic Evaluation of
`Shared-Memory Architectures.” Transactions on Parallel and Distributed Systems (TPDS), volume 14,
`number 2, February 2003, pages 166-180.
`16. Daniel J. Sorin, Manoj Plakal, Anne E. Condon, Mark D. Hill, Milo M. K. Martin, and David A.
`Wood. “Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol.”
`Transactions on Parallel and Distributed Systems (TPDS), volume 13, number 6, June 2002, pages
`556-578.
`
`Refereed Conference Publications
`1. Ralph Nathan, Bryan Anthonio, Shih-Lien Lu, Helia Naeimi, Daniel J. Sorin, and Xiaobai Sun.
`“Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy.” SC '14,
`November 2014.
`2. Ralph Nathan and Daniel J. Sorin. “Nostradamus: Low-Cost Hardware-Only Error Detection for
`Processor Cores.” Design, Automation & Test in Europe (DATE), March 2014.
`3. Meng Zhang, Jesse D. Bingham, John Erickson, and Daniel J. Sorin. “PVCoherence: Designing Flat
`Coherence Protocols for Scalable Verification.” 0th International Symposium on High Performance
`Computer Architecture (HPCA), February 2014. [Best Paper Award]
`4. Opeoluwa Matthews, Meng Zhang, and Daniel J. Sorin. “Scalably Verifiable Dynamic Power Man-
`agement.” 20th International Symposium on High Performance Computer Architecture (HPCA), Febru-
`ary 2014.
`5. Kushal Seetharam, Lance Co Ting Keh, Ralph Nathan, and Daniel J. Sorin. “Applying Reduced Pre-
`cision Arithmetic to Detect Errors in Floating Point Multiplication.” 19th IEEE Pacific Rim Interna-
`tional Symposium on Dependable Computing (PRDC), December 2013.
`6. Blake A. Hechtman and Daniel J. Sorin. “Exploring Memory Consistency for Massively-Threaded
`Throughput-Oriented Processors.” International Symposium on Computer Architecture (ISCA), June
`2013, pages 201-212.
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`7. Blake A. Hechtman and Daniel J. Sorin. “Evaluating Cache Coherent Shared Virtual Memory for
`Heterogeneous Multicore Chips.” Extended abstract and poster in the IEEE International Symposium
`on Performance Analysis of Systems and Software (ISPASS), April 2013, pages 118-119.
`8. Adam N. Jacobvitz, A. Robert Calderbank, and Daniel J. Sorin. “Coset Coding to Improve the Life-
`time of Memory.” International Symposium on High Performance Computer Architecture (HPCA),
`February, 2013, pages 222-233.
`9. Adam N. Jacobvitz, A. Robert Calderbank, and Daniel J. Sorin. “Writing Cosets of a Convolutional
`Code to Increase the Lifetime of Flash Memory.” Invited paper at the 50th Annual Allerton Conference
`on Communication, Control, and Computing, October, 2012, pages 308-318.
`10. Patrick J. Eibl, Albert Meixner, and Daniel J. Sorin. “An FPGA-Based Experimental Evaluation of
`Microprocessor Core Error Detection with Argus-2.” Poster and 2-page paper at ACM SIGMETRICS,
`June 2011, pages 121-122.
`11. Meng Zhang, Alvin R. Lebeck, and Daniel J. Sorin. “Fractal Coherence: Scalably Verifiable Cache
`Coherence.” 43rd International Symposium on Microarchitecture (MICRO), December 2010, pages
`471-482.
`12. Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin. “Specifying and Dynamically Verifying
`Address Translation-Aware Memory Consistency.” 15th International Conference on Architectural
`Support for Programming Languages and Operating Systems (ASPLOS), March 2010. [Selected by
`IEEE Micro as one of 11 “Top Picks” among all computer architecture conference publications in
`2010]
`13. Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin, and Anne Bracy. “UNified Instruc-
`tion/Translation/Data (UNITD) Coherence: One Protocol to Rule Them All.” 16th IEEE International
`Symposium on High-Performance Computer Architecture (HPCA), January 2010.
`14. Patrick J. Eibl, Daniel J. Sorin, and Andrew D. Cook. “Reduced Precision Checking for a Floating
`Point Adder.” 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
`(DFT), October 2009, pages 145-152.
`15. Meng Zhang, Anita Lungu, and Daniel J. Sorin. “Analyzing Formal Verification and Testing
`Efforts of Different Fault Tolerance Mechanisms.” 24th IEEE International Symposium on Defect and
`Fault Tolerance in VLSI Systems (DFT), October 2009, pages 277-285.
`16. Anita Lungu, Pradip Bose, Alper Buyuktosunoglu and Daniel J. Sorin. “Dynamic Power Gating
`with Quality Guarantees.” International Symposium on Low Power Electronics and Design (ISLPED),
`August 2009, pages 377-382.
`17. Anita Lungu, Pradip Bose, Daniel Sorin, Steven German and Geert Janssen. “Multicore Power
`Management: Ensuring Robustness via Early-Stage Formal Verification.” Seventh ACM-IEEE Interna-
`tional Conference on Formal Methods and Models for Codesign (MEMOCODE), July 2009, pages 78-
`87.
`18. Bogdan F. Romanescu and Daniel J. Sorin. “Core Cannibalization Architecture: Improving Life-
`time Chip Performance for Multicore Processors in the Presence of Hard Faults.” Seventeenth Interna-
`tional Conference on Parallel Architectures and Compilation Techniques (PACT), October 2008, pages
`43-51.
`19. Albert Meixner and Daniel J. Sorin. “Detouring: Translating Software to Circumvent Hard Faults
`in Simple Cores.” 38th Annual International Conference on Dependable Systems and Networks (DSN),
`June 2008, pages 80-89.
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`20. Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, and Sule Ozev. “Reducing the Impact of
`Intra-Core Process Variability with Criticality-Based Resource Allocation and Prefetching.” ACM
`International Conference on Computing Frontiers, May 2008, pages 129-138.
`21. Albert Meixner, Michael E. Bauer, and Daniel J. Sorin. “Argus: Low-Cost, Comprehensive Detec-
`tion of Errors in Simple Cores.” 40th Annual IEEE/ACM International Symposium on Microarchitec-
`ture (MICRO), December, 2007, pages 210-222. [Selected by IEEE Micro as one of 10 “Top Picks”
`among all computer architecture conference publications in 2007]
`22. Sule Ozev, Daniel J. Sorin, and Mahmut Yilmaz. “Low-Cost Run-time Diagnosis of Hard Delay
`Faults in the Functional Units of a Microprocessor.” IEEE International Conference on Computer
`Design (ICCD), October 2007, pages 317-324.
`23. Mahmut Yilmaz, Albert Meixner, Sule Ozev, and Daniel J. Sorin. “Lazy Error Detection for Micro-
`processor Functional Units.” IEEE International Symposium on Defect and Fault Tolerance in VLSI
`Systems (DFT), September 2007, pages 361-369.
`24. Anita Lungu and Daniel J. Sorin. “Verification-Aware Microprocessor Design.” Sixteenth Interna-
`tional Conference on Parallel Architectures and Compilation Techniques (PACT), September 2007,
`pages 83-93.
`25. Albert Meixner and Daniel J. Sorin. “Error Detection Using Dynamic Dataflow Verification.” Six-
`teenth International Conference on Parallel Architectures and Compilation Techniques (PACT), Sep-
`tember 2007, pages 104-115.
`26. Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, and Sule Ozev. “Reducing the Impact of
`Process Variability with Prefetching and Criticality-Based Resource Allocation.” Poster and extended
`abstract in Sixteenth International Conference on Parallel Architectures and Compilation Techniques
`(PACT), September 2007, page 424.
`27. Albert Meixner and Daniel J. Sorin. “Unified Microprocessor Core Storage.” ACM Conference on
`Computing Frontiers, May 2007, pages 23-34.
`28. Albert Meixner and Daniel J. Sorin. “Error Detection via Online Checking of Cache Coherence
`with Token Coherence Signatures.” 13th International Symposium on High Performance Computer
`Architecture (HPCA), February, 2007, pages 145-156.
`29. Mahmut Yilmaz, Derek R. Hower, Sule Ozev, and Daniel J. Sorin. “Self-Detecting and Self-Diag-
`nosing 32-bit Microprocessor Multiplier.” International Test Conference (ITC), October 2006.
`30. Nathan N. Sadler and Daniel J. Sorin. “Choosing an Error Protection Scheme for a Microproces-
`sor’s L1 Data Cache.” International Conference on Computer Design (ICCD), October 2006, pages
`499-505.
`31. Albert Meixner and Daniel J. Sorin. “Dynamic Verification of Memory Consistency in Cache-
`Coherent Multithreaded Computer Architectures.” International Conference on Dependable Systems
`and Networks (DSN), June 2006, pages 73-82.
`32. Fred A. Bower, Derek R. Hower, Mahmut Yilmaz, Daniel J. Sorin, and Sule Ozev. “Applying
`Architectural Vulnerability Analysis to Hard Faults in the Microprocessor.” Poster and 2-page paper at
`ACM SIGMETRICS, June 2006, pages 375-376.
`33. Fred A. Bower, Daniel J. Sorin, and Sule Ozev. “A Mechanism for Online Diagnosis of Hard Faults
`in Microprocessors.” 38th Annual IEEE/ACM International Symposium on Microarchitecture
`(MICRO), November 2005, pages 197-208.
`34. Albert Meixner and Daniel J. Sorin. “Dynamic Verification of Sequential Consistency.” 32nd
`Annual International Symposium on Computer Architecture (ISCA), June 2005, pages 482-493.
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`35. Tong Li, Carla S. Ellis, Alvin R. Lebeck, and Daniel J. Sorin. “Pulse: A Dynamic Deadlock Detec-
`tion Mechanism Using Speculative Execution.” USENIX Annual Technical Conference, April 2005,
`pages 31-44.
`36. Jonathan R. Carter, Sule Ozev, and Daniel J. Sorin. “Circuit-Level Modeling for Concurrent Test-
`ing of Operational Defects due to Gate Oxide Breakdown.” Design, Automation, and Test in Europe
`(DATE), March 2005, pages 300-305.
`37. Chris Dwyer, Moky Cheung, and Daniel J. Sorin. “Semi-empirical SPICE Models for Carbon Nan-
`otube FET Logic.” Fourth IEEE Conference on Nanotechnology (IEEE-Nano), August 2004, pages
`386-388.
`38. Fred A. Bower, Paul G. Shealy, Sule Ozev, and Daniel J. Sorin. “Tolerating Hard Faults in Micro-
`processor Array Structures.” International Conference on Dependable Systems and Networks (DSN),
`June 2004, pages 51-60.
`39. Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, and Daniel J. Sorin. “Circuit and System
`Architecture for DNA-Guided Self-Assembly of Nanoelectronics.” Invited paper in Foundations of
`Nanoscience: Self-Assembled Architectures and Devices (FNANO), April 2004, pages 344-358.
`40. Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood. “Using Speculation to Sim-
`plify Multiprocessor Design.” International Parallel and Distributed Processing Symposium (IPDPS),
`April 2004, pages 75-84.
`41. Jaidev P. Patwardhan, Alvin R. Lebeck, and Daniel J. Sorin. “Communication Breakdown: Analyz-
`ing CPU Usage in Commercial Web Workloads.” International Symposium on Performance Analysis of
`Systems and Software (ISPASS), March 2004, pages 12-19.
`42. Daniel J. Sorin, Mark D. Hill, and David A. Wood. “Dynamic Verification of End-to-End Multipro-
`cessor Invariants.” International Conference on Dependable Systems and Networks (DSN-3), June
`2003, pages 281-290.
`43. Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, and David A. Wood. “Using
`Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared Memory Multipro-
`cessors.” 30th Annual International Symposium on Computer Architecture (ISCA), June 2003, pages
`206-217.
`44. Tong Li, Alvin R. Lebeck, and Daniel J. Sorin. “Quantifying Instruction Criticality for Shared
`Memory Multiprocessors.” 15th Symposium on Parallelism in Algorithms and Architectures (SPAA),
`June 2003, pages 128-137.
`45. Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood. “SafetyNet: Improving the
`Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery.” 29th Annual Inter-
`national Symposium on Computer Architecture (ISCA), May 2002, pages 123-134.
`46. Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, and David A. Wood. “Bandwidth Adaptive
`Snooping.” 8th International Symposium on High Performance Computer Architecture (HPCA), Febru-
`ary 2002, pages 251-262.
`47. Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, and Mikko H. Lipasti. “Cor-
`rectly Implementing Value Prediction in Microprocessors that Support Multithreading or Multiprocess-
`ing.” 34th International Symposium on Microarchitecture (MICRO), December 2001, pages 328-337.
`48. Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson,
`Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, and David A. Wood. “Timestamp Snoop-
`ing: An Approach for Extending SMPs.” 9th International Conference on Architectural Support for
`Programming Languages and Operating Systems (ASPLOS), November 2000, pages 25-36.
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`49. Derek L. Eager, Daniel J. Sorin, and Mary K. Vernon. “AMVA Techniques for High Service Time
`Variability.” ACM SIGMETRICS, June 2000, pages 217-228.
`50. Mark D. Hill, Anne E. Condon, Manoj Plakal, and Daniel J. Sorin. “A System-Level Specification
`Framework for I/O Architectures.” 11th Annual Symposium on Parallel Algorithms and Architectures
`(SPAA), June 1999, pages 138-147.
`51. E. Ender Bilir, Ross M. Dickson, Ying Hu, Manoj Plakal, Daniel J. Sorin, Mark D. Hill, and David
`A. Wood. “Multicast Snooping: A New Coherence Method Using a Multicast Address Network.” 26th
`Annual International Symposium on Computer Architecture (ISCA), May 1999, pages 294-304.
`52. Anne E. Condon, Mark D. Hill, Manoj Plakal, and Daniel J. Sorin. “Using Lamport Clocks to Rea-
`son About Relaxed Memory Models.” 5th International Symposium on High Performance Computer
`Architecture (HPCA), January 1999, pages 270-278.
`53. Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, and David A. Wood. “Analytic Eval-
`uation of Shared-Memory Systems with ILP Processors.” 25th Annual International Symposium on
`Computer Architecture (ISCA), June 1998, pages 380-391.
`54. Manoj Plakal, Daniel J. Sorin, Anne E. Condon, and Mark D. Hill. “Lamport Clocks: Verifying a
`Directory Cache-Coherence Protocol.” 10th Annual Symposium on Parallel Algorithms and Architec-
`tures (SPAA), June 1998, pages 67-76.
`Publications in Conference Special Sessions
`1. Daniel J. Sorin, Opeoluwa Matthews, and Meng Zhang. "Architecting Dynamic Power Manage-
`ment to be Formally Verifiable." Design Automation Conference (DAC), June 2014.
`2. Dimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry
`Hari, Daniel Sorin, Albert Meixner, Arijit Biswas, and Xavier Vera. “Architectures for Online Error
`Detection and Recovery in Multicore Processors.” Paper presented as part of embedded tutorial in
`Design, Automation & Test in Europe (DATE), March 2011.
`Refereed and Invited Workshop Publications
`1. John Ingalls, Adam Jacobvitz, Patrick Eibl, Michael Ansel and Daniel Sorin. “Experiences in Devel-
`oping and Evaluating a Low-Cost Soft-Error-Tolerant Multicore Processor.” 10th Workshop on Silicon
`Errors in Logic - System Effects (SELSE), April 2014.
`2. Adam N. Jacobvitz, Robert Calderbank, and Daniel J. Sorin. “Coset Coding to Extend the Lifetime
`of Non-Volatile Memory.” Non-Volatile Memories Workshop (NVM-W), March 2014.
`3. Blake A. Hechtman and Daniel J. Sorin. “The Limits of Concurrency in Cache Coherence.” 10th
`Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD), June 2012.
`4. Ralph Nathan and Daniel J. Sorin. “Argus-G: A Low-Cost Error Detection Scheme for GPGPUs.”
`Workshop on Resilient Architectures, December 2010.
`5. Anita Lungu, Pradip Bose, Daniel J. Sorin, Steven German, and Geert Janssen. “Multicore Power
`Management: Ensuring Robustness via Early-Stage Formal Verification.” 3rd Workshop on Depend-
`able Architectures (WDA-3), November 2008.
`6. Albert Meixner and Daniel J. Sorin. “IOTA: Detecting Erroneous I/O Behavior via I/O Transaction
`Auditing.” First Workshop on Compiler and Architectural Techniques for Application Reliability and
`Security (CATARS), June 2008.
`7. Daniel J. Sorin and Sule Ozev. “Fault Tolerant Microprocessors for Space Missions.” NASA Science
`Technology Conference, June 2007. (invited paper)
`8. Bogdan F. Romanescu, Sule Ozev, and Daniel J. Sorin. “Quantifying the Impact of Process Variabil-
`ity on Microprocessor Behavior.” 2nd Workshop on Architectural Reliability (WAR), December 2006.
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`9. Albert Meixner and Daniel J. Sorin. “Comprehensive Detection of Hardware Errors in Commodity
`Multithreaded Architectures.” 2-page paper and poster in Workshop on Edge Computing Using New
`Commodity Architectures (EDGE), May 2006.
`10. Jaidev Patwardhan, Chris Dwyer, Alvin R. Lebeck, and Daniel J. Sorin. “Evaluating the Connec-
`tivity of Self-Assembled Networks of Nano-Scale Processing Elements.” IEEE International Workshop
`on Design and Test of Defect-Tolerant Nanoscale Architectures (NANOARCH’05), May 2005, pages
`2.17-2.24.
`11. Alaa R. Alameldeen, Pacia J. Harper, Milo M. K. Martin, Carl J. Mauer, Daniel J. Sorin, Min Xu,
`Mark D. Hill, and David A. Wood. "Evaluating Non-deterministic Multi-threaded Commercial Work-
`loads." Fifth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-
`02), February 2002, pages 30-38.
`Book Contributions
`Exercise Editor for: David A. Patterson and John L. Hennessy. Computer Organization and Design:
`The Hardware/Software Interface, 3rd edition. Morgan-Kaufmann Publishers, 2004.
`
`Patents
`1. United State Patent 6,883,070. “Bandwidth-Adaptive, Hybrid, Cache-Coherence Protocol.” Inven-
`tors: Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, and David A. Wood. April 19, 2005.
`2. United States Patent 7,415,644. “Self-Repairing of Microprocessor Array Structures.” Inventors:
`Fred A. Bower, Sule Ozev, Paul G. Shealy, and Daniel J. Sorin. August 19, 2008.
`Other Publications
`1. Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, and Daniel J. Sorin. “VariaSim: Simulating
`Circuits and Systems in the Presence of Process Variability.” Computer Architecture News (CAN), vol-
`ume 35, number 5, December 2007, pages 45-48.
`2. Milo M.K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R.
`Alameldeen, Kevin E. Moore, Mark D. Hill, and David A. Wood. “Multifacet’s General Execution-
`driven Multiprocessor Simulator (GEMS) Toolset.” Computer Architecture News (CAN), volume 33,
`number 4, November 2005.
`
`Software Distributions
`1. Multifacet GEMS Simulation infrastructure. http://www.cs.wisc.edu/gems/
`2. Cynk runtime for CPU/GPU task-parallel programming: https://bitbucket.org/blake-
`hechtman/cynk/wiki/Home
`3. Pulse: dynamic deadlock detection. http://www.ee.duke.edu/~sorin/tasmania/
`4. VariaSim statistical static timing analysis. http://www.ee.duke.edu/variasim/
`
`Conference Talks
`1. “PVCoherence: Designing Flat Coherence Protocols for Scalable Verification.” 0th International
`Symposium on High Performance Computer Architecture (HPCA), Orlando, Florida, February 2014.
`Best Paper Award
`2. “Architectures for Online Error Detection and Recovery in Multicore Processors.” Design, Automa-
`tion & Test in Europe (DATE), Grenoble, France, March 2011.
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`3. “Multicore Power Management: Ensuring Robustness via Early-Stage Formal Verification.” Seventh
`ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE),
`Cambridge, Massachusetts, July 2009.
`4. “Fault Tolerant Microprocessors for Space Missions.” NASA Science Technology Conference
`(NSTC-07), Adelphi, Maryland, June 2007.
`5. “Choosing an Error Protection Scheme for a Microprocessor’s L1 Data Cache.” International Con-
`ference on Computer Design (ICCD), San Jose, California, October 2006.
`6. “Using Speculation to Simplify Multiprocessor Design.” International Parallel and Distributed
`Processing Symposium (IPDPS), Santa Fe, New Mexico, April 2004.
`7. “Dynamic Verification of End-to-End Multiprocessor Invariants.” International Conference on
`Dependable Systems and Networks (DSN-3), San Francisco, California, June 2003.
`8. “SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Check-
`point/Recovery.” 29th International Symposium on Computer Architecture (ISCA), Anchorage, Alaska,
`June 2002.
`9. “Correctly Implementing Value Prediction in Microprocessors that Support Multithreading or Multi-
`processing.” 34th International Symposium on Microarchitecture (MICRO-34), Austin, Texas, Decem-
`ber 2001.
`10. “AMVA Techniques for High Service Time Variability.” ACM SIGMETRICS 2000, Santa Clara,
`California, June 2000.
`11. “A System-Level Specification Framework for I/O Architectures.” 11th Annual Symposium on
`Parallel Algorithms and Architectures (SPAA), Saint-Malo, France, June 1999. (Also presented at the
`Wisconsin Architecture Affiliates Meeting, October 1999)
`12. “Using Lamport Clocks to Reason About Relaxed Memory Models.” 5th International Symposium
`on High Performance Computer Architecture (HPCA), Orlando, Florida, January 1999.
`13. “Analytic Evaluation of Shared-Memory Systems with ILP Processors.” 25th Annual International
`Symposium on Computer Architecture (ISCA), Barcelona, Spain, June 1998. (Also presented at the Wis-
`consin Architecture Affiliates Meeting, October 1998)
`
`Invited Talks
`“Cache Coherence: Scalability, New Platforms, and Verification”
`• Qualcomm (Raleigh, NC), May 2013
`“Verification-Aware Architecture and Fractal Coherence”
`• Keynote talk at 3rd HiPEAC Workshop on Design for Reliability (Heraklion, Greece), January
`2011
`• Washington University (St. Louis, MO), February 2011
`“Verification-Aware Architecture”
`• Workshop on Resilient Architectures (Atlanta, GA), December 2010
`“UNified Instruction/Translation/Data (UNITD) Coherence: One Protocol to Rule Them All”
`• AMD (Portland, OR), September 2010
`• Intel Corporation (Hillsboro, OR), September 2010
`“Detecting Faults and Hardware Bugs Using Dynamic Verification”
`
`9
`
`

`

`• Dagstuhl seminar on Fault Tolerant Distributed Algorithms for VLSI Chips (Dagstuhl, Ger-
`many), September 2008
`“Post-Silicon Validation Using Dynamic Verification”
`• GSRC Workshop on Post-Silicon Validation (Anaheim, CA), June 2008
`“Low-cost, Comprehensive Error Detection for Commodity Processors”
`• Stanford University (Palo Alto, CA), May 2008; University of California—Berkeley, May 2008;
`University of Illinois (Champaign-Urbana, IL), April 2008; University of Michigan (Ann Arbor,
`MI), April 2008
`“Why Do We Still Have Bugs?” (panel discussion)
`• IBM T.J. Watson Research Center (Yorktown Heights, NY), April 2008
`“The Design of Dependable and Variability-Tolerant Multithreaded Architectures”
`• IBM T.J. Watson Research Center (Yorktown Heights, NY), September 2006
`“Comprehensive Detection of Errors in Multithreaded Architectures”
`• Intel Corporation (Hudson, MA), April 2007; University of Texas at Austin, March 2007;
`Advanced Micro Devices (Austin, TX), March 2007; Carnegie Mellon University (Pittsburgh,
`PA), February 2007; University of Pennsylvania (Philadelphia, PA), June 2006
`"Comprehensive Error Detection for Multithreaded Memory Systems"
`• NC State University: Computer Engineering Seminar, November 2005
`“Duke FaultFinder Project”
`• IBM University Day (Research Triangle Park, NC), October 2005
`“Sherlock: Dynamic Verification of Multithreaded Memory Systems”
`• Intel Labs (Portland, OR), September 2003; University of British Columbia (Vancouver, Can-
`ada), June 2003
`“SafetyNet: Improving the Availability and Designability of Shared Memory Multiprocessors”
`• University of California—Berkeley, April 2002; University of California—San Diego, April
`2002; Stanford University (Palo Alto, CA), March 2002; University of Pennsylvania (Philadel-
`phia, PA), March 2002; North Carolina State University (Raleigh, NC), February 2002; Duke Uni-
`versity (Durham, NC), February 2002; Case Western Reserve University (Cleveland, OH),
`February 2002; Northwestern University (Evanston, IL), February 2002
`“SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Check-
`point/Recovery”
`• Intel Labs (Portland, OR), January 2002
`
`Tutorials
`“Verification-Aware Dynamic Power Management” as part of Tutorial on Energy-Secure System
`Architectures, at the 38th International Symposium on Computer Architecture (ISCA), June 2011.
`“Fault Tolerant Computer Architecture,” at the Sixth International Summer School on Advanced Com-
`puter Architecture and Compilation for Embedded Systems (ACACES). Week-long course sponsored by
`the European Network of Excellence on High Performance and Embedded Architecture and Compila-
`tion (HiPEAC). Terrassa (Barcelona), Spain, July 2010.
`
`10
`
`

`

`“GEMS: Multifacet’s Accurate and Flexible Full System Simulator”, at the 32nd International Sympo-
`sium on Computer Architecture (ISCA), June 2005. Organized by Mike Marty, Bradford Beckmann,
`Luke Yen, Alaa R. Alameldeen, Min Xu, Kevin E. Moore, Daniel J. Sorin, and Milo M.K. Martin
`
`Teaching (Sp = Spring, Fa = Fall)
`>> ECE 152: Introduction to Computer Architecture: Sp 2005, Sp 2008, Sp 2009, Sp 2011, Sp 2012
`• major updating of course in Sp 2005
`>> ECE 250: Computer Architecture: Fa 2012, Sp 2013, Fa 2014
`• developed and first offered in Fa 2012
`>> ECE 552 / CPS 550 (was ECE 252 / CPS 220): Advanced Computer Architecture I: Fa 2003, Fa
`2005, Fa 2007, Fa 2009, Fa 2013
`• first cross-listed with Computer Science in Fa 2003
`>> ECE 254 / CPS 225: Fault Tolerant and Testable Computing Systems: Fa 2004, Fa 2006, Fa 2008, F
`2011
`
`• major updating of course in Fa 2004
`>> ECE 652 / CPS 650 (was ECE 259 / CPS 221): Advanced Computer Architecture II: Sp 2003, Sp
`2004, Sp 2006, Sp 2010, Sp 2014
`• developed and first offered in ECE in Sp 2003
`• added to Digital Systems sequence in Sp 2006 (first class with undergraduates)
`>> I have also taught dozens of independent study courses.
`
`Journal Editor Service
`Associate Editor for Computer Architecture Letters (2012-current)
`Subject Area Editor for Journal of Parallel and Distributed Computing (2014-current)
`
`Conference and Workshop Program Committee Service
`International Symposium on Computer Architecture (ISCA): 2008, 2009, 2010 (external review com-
`mittee), 2013
`International Conference on Dependable Systems and Networks (DSN): 2008, 2009, 2010, 2012, 2013
`International Symposium on Microarchitecture (MICRO): 2009, 2010, 2012 (external review commit-
`tee), 2014 (external review committee)
`International Symposium on High-Performance Computer Architecture (HPCA): 2009, 2010, 2013,
`2014, 2015
`IEEE Micro’s Top Picks in Computer Architecture: 2012, 2014
`International Conference on Parallel Architectures and Compilation Techniques (PACT): 2009, 2014
`ACM SIGMETRICS: 2005
`International Conference on Architectural Support for Programming Languages and Operating Systems
`(ASPLOS): 2010 (external review committee), 2011 (external review committee), 2012
`Symposium on Parallelism in Algorithms and Architectures (SPAA): 2004, 2007
`International Conference on Computer Design (ICCD): 2006, 2007, 2008
`IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS): 2007
`IEEE International Symposium on Workload Characterization (IISWC