111111
`
`1111111111111111111111111111111111111111111111111111111111111111111111111111
`US 20020073261Al
`
`(19) United States
`(12) Patent Application Publication
`Kosaraju
`
`(10) Pub. No.: US 2002/0073261 A1
`Jun. 13, 2002
`(43) Pub. Date:
`
`(54) APPARATUS AND A METHOD TO PROVIDE
`HIGHER BANDWIDTH OR PROCESSING
`POWER ON A BUS
`
`(21) Appl. No.:
`
`09/737,648
`
`(22) Filed:
`
`Dec. 13, 2000
`
`(76)
`
`Inventor: Chakravarthy Kosaraju, Sunnyvale,
`CA(US)
`
`Correspondence Address:
`Thomas S. Ferrill
`BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN
`LLP
`7th Floor
`12400 Wilshire Boulevard
`Los Angeles, CA 90025-1026 (US)
`
`Publication Classification
`
`(51)
`
`Int. Cl? .......................... G06F 12/00; G06F 13/14;
`G06F 13/38
`(52) U.S. Cl. .............................................................. 710/240
`
`ABSTRACT
`(57)
`A method and apparatus in which an arbiter links to a
`processor having a flexible architecture, and the processor
`connects to a device through a point to point bus.
`
`Processor 1
`
`Processor 2
`
`Processor 3
`
`Processor 4
`
`Northbridge
`chipset
`
`t---
`t---
`
`External
`Memory
`
`Southbridge
`chipset
`
`Petition for Inter Partes Review of 
`U.S. Pat. No. 7,296,121
`IPR2015‐00158
`EXHIBIT
`Sony‐
`
`1
`
`

`

`Patent Application Publication
`
`Jun. 13, 2002 Sheet 1 of 9
`
`US 2002/0073261 A1
`
`Processor 1
`
`Processor2
`
`Processor 3
`
`Processor 4
`
`Northbridge
`chipset
`
`1-------
`1----
`
`External
`Memory
`
`Southbridge
`chipset
`
`Figure 1
`
`2
`
`

`

`Patent Application Publication
`
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`Patent Application Publication
`
`Jun. 13, 2002 Sheet 4 of 9
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`US 2002/0073261 A1
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`

`Patent Application Publication
`
`Jun. 13, 2002 Sheet 5 of 9
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`Patent Application Publication
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`Jun. 13, 2002 Sheet 6 of 9
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`US 2002/0073261 A1
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`
`7
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`

`

`Patent Application Publication
`
`Jun. 13, 2002 Sheet 7 of 9
`
`US 2002/0073261 A1
`
`Protocol Layer
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`Patent Application Publication
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`Jun. 13, 2002 Sheet 9 of 9
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`US 2002/0073261 A1
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`Figure 10
`
`10
`
`

`

`US 2002/0073261 A1
`
`Jun. 13,2002
`
`1
`
`APPARATUS AND A METHOD TO PROVIDE
`HIGHER BANDWIDTH OR PROCESSING POWER
`ON A BUS
`
`FIELD OF THE INVENTION
`
`[0001] This invention generally relates to changing the
`number of ports linked between a device and a processor.
`More particularly this invention relates to an apparatus and
`method capable of changing the number of ports linked
`between a device and a processor without changing the
`architecture in the processor.
`
`BACKGROUND OF THE INVENTION
`Joining several processors in parallel increases
`[0002]
`processing capacity. Typically, any number from two to
`eight processors may be joined in parallel. Generally, mul(cid:173)
`tiple parallel processors are joined together on a shared bus.
`FIG. 1 illustrates a four processor ( 4P) architecture used in
`conjunction with a shared bus. Four processors, Processor 1,
`Processor 2, Processor 3, and Processor 4, connect to a
`shared bus, which in turn connects to the Northbridge
`chipset. The Northbridge chipset further connects to the
`Southbridge chipset and external memory. For example, a
`PentiumTM processor may employ the shared bus architec(cid:173)
`ture illustrated in FIG. 1. However, a point-to point archi(cid:173)
`tecture, typically, provides a higher bandwidth than does a
`shared bus architecture.
`
`In a shared bus architecture, multiple devices all
`[0003]
`share the same bus and must follow an order and protocol to
`use the bus. In contrast, a point-to-point bus architecture
`provides an uninterrupted connection between two separate
`devices. Thus, in general, a point-to-point bus creates a
`higher bandwidth between two separate devices. A higher
`bandwidth can have the beneficial effect of yielding an
`increased performance from a single processor or group of
`processors. For example, if a 48-bit connection exists
`between two devices, then transactions occur between the
`two devices three times faster than if only a 16-bit connec(cid:173)
`tion exists between the two devices. However, a point-to(cid:173)
`point bus architecture may have a disadvantage because the
`architecture provides an uninterrupted connection between
`two separate devices. Thus, if at any given time, light
`transfers of information occur between the two devices, then
`the excess bandwidth capacity is essentially wasted.
`
`[0004] For example, if a customer is using his or her
`computer system to run both a workstation application and
`a server application, then the customer may not be achieving
`peak performance from the hardware in his computer sys(cid:173)
`tem. In a server application a heavy exchange of information
`occurs between processors. Thus, the manufacturer may
`create a high bandwidth connection between each processor
`in the system. Yet, if for example a customer wants to use a
`computer system for an application, which involves a heavy
`exchange of information between each processor and a
`chipset, such as a workstation application, then the manu(cid:173)
`facturer creates a high bandwidth connection between each
`processor and the chip in the system. However, if the
`customer has a computer system which has a high band(cid:173)
`width connection between the processor(s) and the chipset,
`but chooses to currently run a server application on this
`system, then the customer may suffer poor performance
`from the server application and waste the excess bandwidth
`between the chipset and processor(s).
`
`[0005] Further, manufacturers may build different ver(cid:173)
`sions of a processor: to optimally service either a work
`station or a server; or to perform satisfactorily for most work
`station or server applications. Typically, a processor is
`hardwired to the other processors and components, such as
`chipsets, in the system. A manufacturer may create a high
`bandwidth connection between two processors or a proces(cid:173)
`sor and a chipset by dedicating a number of port establishing
`the connection between these two devices. The manufac(cid:173)
`turer creates the chip with an expectation that a hardwire
`connection to exist between the two devices. The manufac(cid:173)
`turer presets the processing component of the processor to
`know that these ports are dedicated between the two devices.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0006] The drawings refer to the invention in which:
`
`[0007] FIG. 1 illustrates a four processor ( 4P) architecture
`used in conjunction with a shared bus;
`
`[0008] FIG. 2 illustrates an embodiment of a processor
`having an arbiter, a protocol layer, a buffer layer, and an
`information transfer layer;
`
`[0009] FIG. 3 illustrates a two processor point-to-point
`architecture having a 16-bit point-to-point connection
`between: 1) an input-output component and the first proces(cid:173)
`sor; as well as 2) the input-output component and the second
`processor;
`
`[0010] FIG. 4 illustrates a two processor point-to-point
`architecture having a 32-bit point-to-point connection
`between: 1) the input-output component and the first pro(cid:173)
`cessor; as well as 2) the input-output component and the
`second processor;
`
`[0011] FIG. 5 illustrates a four processor point-to-point
`architecture having a 16-bit point-to-point connection
`between an input-output component and each of the four
`processors;
`
`[0012] FIG. 6 illustrates an embodiment of an eight pro(cid:173)
`cessor point-to-point architecture comprised of four pairs of
`processors linked to a corresponding bridge and each bridge
`connected to a chipset;
`
`[0013] FIG. 7 illustrates an embodiment of the arbiter
`controlling the inbound signal pathways in an embodiment
`of the information transfer layer;
`
`[0014] FIG. 8 illustrates an embodiment of the arbiter
`controlling the inbound signal pathways in an embodiment
`of the buffer layer;
`
`[0015] FIG. 9 illustrates an embodiment of the arbiter
`controlling the outbound signal pathways in an embodiment
`of the buffer layer; and
`
`[0016] FIG. 10 illustrates an embodiment of the arbiter
`controlling the signal pathways in an outbound information
`transfer layer.
`
`[0017] While the invention is subject to various modifi(cid:173)
`cations and alternative forms, specific embodiments thereof
`have been shown by way of example in the drawings and
`will herein be described in detail. The invention should be
`understood to not be limited to the particular forms dis(cid:173)
`closed, but on the contrary, the intention is to cover all
`
`11
`
`

`

`US 2002/0073261 Al
`
`Jun. 13,2002
`
`2
`
`modifications, equivalents, and alternatives falling within
`the spirit and scope of the invention.
`
`DETAILED DISCUSSION
`
`[0018] A person skilled in the art will appreciate that
`various deviations from the described embodiments of the
`invention are possible and that many modifications and
`improvements may be made within the scope and spirit
`thereof. For example, in several described embodiments
`specific clock speeds, specific number of data bits, specific
`number of layers, a specific number of components, etc. are
`used within this description to illustrate embodiments of the
`invention. However, a person skilled in the art will appre(cid:173)
`ciate that embodiments of this invention specifically include
`various deviations from the specific number given in a
`particular embodiment described herein for illustrative pur(cid:173)
`poses.
`
`[0019] An arbiter may be used with a processor in a
`point-to-point architecture to allow a customer to change the
`number of ports linked between a processor and a device
`external to the processor. A point-to-point bus architecture
`provides an uninterrupted connection between two separate
`devices. Generally, a packet based protocol transfers infor(cid:173)
`mation in a point-to-point bus architecture. The arbiter may
`alter the number of ports linked between the processor and
`the device exterior to the processor by changing one or more
`internal signal pathways in the processor without changing
`a physical component layout in the processor. In an embodi(cid:173)
`ment, the manufacturer or the customer may change the
`number of ports linked between the two devices to increase
`the bandwidth between the devices. In an embodiment, the
`manufacturer or the customer may add additional processors
`linked to a device by changing the number of ports linked
`between a first processor and the device exterior to the first
`processor.
`
`[0020] FIG. 2 illustrates an embodiment of a processor
`200 having an arbiter 202, a protocol layer 204, a buffer
`layer 206, and an information transfer layer 208. In one
`embodiment, the processor 200 has an arbiter 202 and three
`layers, the protocol layer 204, a buffer layer 206 such as one
`or more link layers 210, and an information transfer layer
`208 such as one or more physical layers 212. The arbiter 202
`changes the signal pathways within the physical layer 212
`and link layer 210 without changing the physical component
`layout in the processor 200. The physical layer 212 carries
`out the actual physical transfer of information to and from
`other devices. The link layer 210 performs liaison functions
`between the higher functions of the protocol layer 204 and
`the physical layer 212. The protocol layer 204 processes
`requests, responses, and data transfers.
`
`In an embodiment, the arbiter 202 may be internal
`[0021]
`or external to the processor 200. In an embodiment, a single
`arbiter 202 controls the signal pathways in all the layers of
`the processor 200. In an alternative embodiment, multiple
`arbiters 202 exist to control the signal pathways. The arbiter
`202 may be a combination of hardware and software. The
`arbiter 202 may have several functions such as sending an
`enable/disable signal to one or more signal pathway switch(cid:173)
`ing devices and sending a signal to change various clocking
`speeds. The buffer layer 206 may have one or more inbound
`signal pathways. The buffer layer 206 may have one or more
`outbound signal pathways. The information transfer layer
`
`208 may have one or more inbound signal pathways. The
`information transfer layer 208 may have one or more
`outbound signal pathways.
`[0022] FIG. 3 illustrates a two processor point-to-point
`architecture 300 having a 16-bit point-to-point connection
`between: 1) an input-output component 302 and the first
`processor 304; as well as 2) the input-output component 302
`and the second processor 306. A first processor 304 having
`four 16-bit ports 308, 310, 312, 314 connected to the
`processor may have three 16-bit ports 308, 310, 312 con(cid:173)
`nected to a second processor 306 and one 16-bit port
`connected 314 to the input-output component 302. In an
`embodiment, the input-output component maybe a bridge, a
`memory, a chipset or similar component. Thus, a 48-bit
`bandwidth connection exists between the first processor 304
`and the second processor 306. Further, the first processor
`304 and the second processor 306 have a 16-bit bandwidth
`connection to the input-output component 302. The arbiter
`can change the signal pathways in the first processor 304
`such that the processor now has two 16-bit point-to-point
`(32-bit) connections to the second processor 306 and a
`32-bit connection to the input-output component 302.
`
`[0023] FIG. 4 illustrates a two processor point-to-point
`architecture 400 having a 32-bit point-to-point connection
`between: 1) the input-output component 402 and the first
`processor 404; as well as 2) the input-output component 402
`and the second processor 406. A first processor 404 having
`four 16-bit ports 408, 410, 412, 414 connected to the
`processor may have two 16-bit ports connected to a second
`processor 406 and two 16-bit ports connected to the input(cid:173)
`output component 402 such as a chip set. Thus, a 32-bit
`bandwidth connection exists between the first processor 404
`and the second processor 406. Further, the first processor
`404 and the second processor 406 have a 32-bit bandwidth
`connection to the input-output component 402. In the 32-bit
`mode as compared to 16-bit mode, the bandwidth between
`the input-output component 402 and the first processor 404
`as well as the input-output component 402 and the second
`processor 406 has effectively doubled. Bandwidth is the total
`amount of information that can be transferred within a given
`time period between two devices. In 16-bit mode, eight
`clock cycles must occur to transfer eight 16-bit packets (128
`bits) of information between each processor and the input(cid:173)
`output component. In 32-bit mode, four clock cycles must
`occur to transfer four 32-bit packets (128 bits) of informa(cid:173)
`tion between each processor and the input-output compo(cid:173)
`nent.
`
`[0024] FIG. 5 illustrates an embodiment of a four proces(cid:173)
`sor point-to-point architecture 500 having a 16-bit point-to(cid:173)
`point connection between an input-output component 502
`and each of the four processors 504, 506, 508, 510. The four
`processors are processor 1 504, processor 2 506, processor
`3 508, and processor 4 510. In an embodiment, each of the
`four processors 504, 506, 508, 510 employs an embodiment
`of the arbiter. The processors 504, 506, 508, 510 have a
`flexible architecture that coordinates with the arbiter to
`allow a variety of uses for these processors 504, 506, 508,
`510. For example, the four processor architecture 500 may
`be substituted with the two processor architecture employing
`a 32-bit connection with the input-output component 502.
`Thus, the processing power of this arrangement has effec(cid:173)
`tively doubled because four processors will process the data
`coming from the input-output component 502. Thus, an
`
`12
`
`

`

`US 2002/0073261 Al
`
`Jun. 13,2002
`
`3
`
`embodiment of the arbiter allows the same input-output
`component 502 to work with either a two processor archi(cid:173)
`tecture, a four processor architecture 500 or other similar
`multiple processor architecture.
`
`[0025] A programmable knob setting in a configuration
`register directs the arbiter to establish the customer's current
`desired configuration such as a 16-bit, 32-bit, or 48-bit
`point-to-point connection between the processor and a
`device exterior to the processor. In an embodiment, the
`device exterior to the processor may be another processor, an
`input-output device, a bridge or other similar device. In an
`embodiment, the manufacturer or the customer may pro(cid:173)
`gram the knob setting to establish the bandwidth connec(cid:173)
`tions between the processor and devices exterior to the
`processor. Based on the knob setting of the configuration
`register, the arbiter may enable and disable signal pathways
`within the information transfer layer and buffer layer. In an
`embodiment, the arbiter may change these signal pathways
`to increase or decrease the number of processor ports, and
`thus, the effective bandwidth, between a processor and
`another device. In an embodiment, the arbiter may change
`these signal pathways to increase or decrease the number of
`processor ports, and thus the number of processors, con(cid:173)
`nected to the input-output device.
`
`[0026] Typically, in a server, a large exchange of data
`occurs between a first processor and a second processor.
`Thus, having a 48-bit point-to-point connection between
`these two devices greatly decreases the time required to
`complete each transaction between the devices. Typically, in
`a work station, a large exchange of data occurs between a
`each processor and the input-output component. Thus, hav(cid:173)
`ing a 32-bit or 48-bit point-to-point connection between
`these devices greatly decreases the time required to com(cid:173)
`plete each transaction between the devices.
`
`[0027] FIG. 6 illustrates an embodiment of an eight pro(cid:173)
`cessor (8P) point-to-point architecture 600 comprised of
`four pairs of processors, 602, 604, 606, 608, 610,612, 614
`and 616, linked to a corresponding bridge, 620, 622, 624,
`628, and each bridge, 620, 622, 624, 628, connected to a
`chipset 630. A first processor 602 and a second processor
`604 each have a 16-bit point to point connection with a first
`bridge 620. The first bridge 620 has a connection, such as a
`32-bit connection, with the chipset 630. Similarly, a third
`processor 606 and a fourth processor 608 each have a 16-bit
`point to point connection with a second bridge 622. The
`second bridge 622 has a connection, such as a 32-bit
`connection, with the chipset 630. In a similar fashion, the
`fifth processor 610 through eighth processor 612 eventually
`link with the chipset 630. In an embodiment, the arbiter may
`allow the signal paths internal to each processor 602, 604,
`606, 608, 610,612, 614 and 616, to be changed by a
`programmable setting. This allows a manufacturer to fabri(cid:173)
`cate a single version of a processor with a generic but
`flexible architecture within the processor to service multiple
`processor platforms. Thus, in an embodiment, an arbiter
`linked to a processor having a single flexible architecture
`may be employed to service, a 2P architecture, 4P architec(cid:173)
`ture, 8P architecture or other multiple processor architecture,
`as well as service a server application and a workstation
`application.
`
`[0028]
`In an embodiment, the ability of the arbiter to
`change the allocation of internal signal paths allows a
`
`manufacturer to design and fabricate fewer versions of the
`same chip to service customers needs. In an embodiment,
`the architecture of the processor is the arrangement and
`component makeup of the various elements within the
`processor. In an embodiment, the components and elements
`contained within the protocol layer, the information layer
`and the buffer layer makeup the architecture of the proces(cid:173)
`sor. Those ordinarily skilled in the art will recognize the
`specific components illustrated in the following embodi(cid:173)
`ments may be deviated from and still be within the spirit of
`this invention.
`[0029] FIG. 7 illustrates an embodiment of the arbiter 702
`controlling the inbound signal pathways in an embodiment
`of the information transfer layer 700. The first physical layer
`(SPXO) 704 has a first port 706; nine 16-bit registers, a first
`register 708, a second register 710, a third register 712, a
`fourth register 714, a fifth register 716, a sixth register 718,
`a seventh register 720, an eighth register 722, and a ninth
`register 724; first 64-bit register 726; a signal pathway
`switching device 728 such as a multiplexer; an embodiment
`of the arbiter 702; a first time delay 709, and a first flip flop
`730. The second physical layer (SPX1) 732 has a second
`port 734; nine 16-bit registers, a tenth register 736, an
`eleventh register 738, a twelfth register 740, a thirteenth
`register 742, a fourteenth register 744, a fifteenth register
`746, a sixteenth register 748, a seventeen register 750, and
`an eighteenth register 752; a second 64-bit register 753; and
`a second time delay 737, and a second flip flop 756. A
`multiplexer is a device that merges several low-speed trans(cid:173)
`missions into one high-speed transmission and vice versa.
`The configuration register 754 informs the arbiter 702
`whether a particular component exterior to the processor
`should be a 16-bit, 32-bit or 48-bit-point-to-point connec(cid:173)
`tion.
`If the configuration register 754 is programmed for
`[0030]
`a 16-bit point-to-point connection to the input-output com(cid:173)
`ponent, then the arbiter 702 directs each physical layer to act
`independently of the other physical layers. In an embodi(cid:173)
`ment of a four processor architecture for example, the first
`port 706 connects to a second processor and the second port
`734 links up to an input-output component. The first register
`708 receives an inbound 16-bit packet of information
`through the first port 706. This 16-bit packet of information
`is sent from the first register 708 through a first time delay
`709 to be stored in the second register 710. The first register
`708 receives another inbound 16-bit packet of information
`through the first port 706. The first register 708 sends this
`second 16-bit packet of information to be stored in the third
`register 712. The first physical layer 704 repeats this process
`until the second register 710 through the ninth register 724
`are each storing 16-bit packets of information. The first
`signal pathway switching device 728 senses that these eight
`16-bit (or 128-bits) of information are ready to be trans(cid:173)
`ferred to the first link layer through the first flip flop 730.
`Upon the next clock cycle the 128-bits of information are
`transferred to the first link layer through the first flip flop
`730. In a similar manner but using the components of second
`physical layer 732, the second physical layer 732 transfers
`128-bits to the second link layer. However, the 128-bits of
`information that are transferred to the first link layer are
`unrelated to the 128-bits of information that are transferred
`to the second link layer. Thus, in our example the first
`128-bits of information come through the first port 706 from
`a second processor. Similarly, the second 128-bits of infor-
`
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`US 2002/0073261 Al
`
`Jun. 13,2002
`
`4
`
`mation come through the second port 734 from the input(cid:173)
`output component. The arbiter 702 enables the 128-bit path
`in the first signal pathway switching device 728. The arbiter
`702 disables the dual 64-bit path in the first signal pathway
`switching device 728. The arbiter 702 enables the first flip
`flop 730 and the second flip flop 756.
`
`If the configuration register 754 is programmed for
`[0031]
`a 32-bit point-to-point connection, then the arbiter 702
`gangs two physical layers to act together. The arbiter 702
`disables the 128-bit path in the first signal pathway switch(cid:173)
`ing device 728. The arbiter 702 enables the dual 64-bit path
`in the first signal pathway switching device 728. The arbiter
`702 enables the first flip flop 730 but disables the second flip
`flop 756. The arbiter 702 increases the clocking speed for the
`first register 708 through the eighteenth register 752 by a
`factor of two. The first physical layer 704 receives four
`16-bit packets of information and stores the packets of
`information in the second register 710 through the fifth
`register 716. The second physical layer 732 receives four
`16-bit packets of information and stores the packets of
`information in the eleventh register 738 through the four(cid:173)
`teenth register 744. The first signal pathway switching
`device 728 senses that the first 64-bit register contains four
`16-bit packets of information from the second register 710
`through the fifth register 716. The first signal pathway
`switching device 728 senses that the second 64-bit register
`contains four 16-bit packets of information from the elev(cid:173)
`enth register 738 through the fourteenth register 744. Upon
`the next clock cycle, the 64-bits of information from the first
`64-bit register and the 64-bits of information from the
`second 64-bit register are transferred up to the first signal
`pathway switching device 728 through the dual 64-bit path.
`The first signal pathway switching device 728 transfers the
`eight related 16-bit packets of information to the first link
`layer. Both the device exterior to the processor and the
`processor transfer the eight related 16-bit packets of infor(cid:173)
`mation as if a 32-bit point-to-point connection exists
`between the processor and the device. The second link layer
`receives no signal because the second flip flop 756 is
`disabled. In a similar manner, the arbiter may gang three
`physical layers together to create a 48-bit point-to-point
`connection between the processor and the device.
`
`[0032] FIG. 8 illustrates an embodiment of the arbiter 802
`controlling the inbound signal pathways in an embodiment
`of the buffer layer 800. The inbound signal pathway of the
`first link layer 804 has a first 128-bit register 806, a first
`response queue 808, a first request queue 810, and a first
`signal pathway switching device 812. The inbound signal
`pathway of the second link layer 814 has a second 128-bit
`register 816, a second response queue 811, a second request
`queue 813, and a second signal pathway switching device
`816. The component makeup of the third link layer 818 and
`fourth link layer 820 are similar to the first link layer 804.
`The first link layer 804 through the fourth link layer 820 feed
`into a fifth signal pathway switching device 822, an embodi(cid:173)
`ment of an arbiter 802, a fifth 128-bit register 824, a local
`address transaction tracker buffer (LAT1) 826, a central data
`management buffer (CDM) 828, and a remote address
`transaction tracker buffer (RAT1) 830.
`
`[0033]
`In an embodiment of the inbound buffer layer 800,
`if the configuration register 832 is programmed for a 32-bit
`point-to-point connection, then the arbiter 802 effectively
`gangs two link layers together. The first link layer 804
`
`receives the eight related 16-bit packets (128-bit) of infor(cid:173)
`mation at twice the clock speed from the communication
`switching device in the first physical layer. The first link
`layer 804 stores the 128-bit packet of information in the first
`register 806. The 128-bit packet of information is routed
`appropriately to either the first response queue 808 or the
`first request queue 810. The arbiter 802 sends an enablement
`signal to the first signal pathway switching device 812, third
`signal pathway switching device 834, and fifth signal path(cid:173)
`way switching device 822. The arbiter 802 also sends a
`disable signal to the second signal pathway switching device
`816 and fourth signal pathway switching device 836. The
`arbiter 802 directs the fifth signal pathway switching device
`822 to request data only from the first signal pathway
`switching device 812 and the third signal pathway switching
`device 834. In 32-bit mode, the second signal pathway
`switching device 816 and fourth signal pathway switching
`device 836 receive no signal from the physical layer because
`the arbiter 802 disabled the second flip flop and fourth flip
`flop in the physical layer.
`[0034] The 128-bit packets of information are transferred
`to the fifth signal pathway switching device 822 through the
`first signal pathway switching device 812 and then the third
`signal pathway switching device 834 in a cyclic sequential
`manner. In a repeating cycle, the fifth signal pathway
`switching device 822 requests the contents of the first
`response queue 808, then the first request queue 810, then
`the third response queue 838, then the third request queue
`840, and then repeats this sequence. Every packet of infor(cid:173)
`mation may be either a request for a command and/or data
`or a response to a command or data. In an embodiment, once
`a packet is written into a response queue or request queue,
`then the information is transferred from these queues at core
`clock frequency. The packets of information are sent from
`the fifth signal pathway switching device 822 to one of the
`following three components. The central data management
`buffer (CDM) 828 stores data to be consumed by the
`protocol layer 840. The remote address transaction tracker
`buffer (RATT) 830 stores commands from a remote device
`such as a request from a remote processor. The CDM 828
`stores corresponding data, if any, associated with that com(cid:173)
`mand. Similarly, the local address transaction tracker buffer
`(LATT) 826 stores local commands and responses made by
`the processor core. The corresponding data, if any, associ(cid:173)
`ated with that command is stored in the CDM 828.
`If the configuration register 832 is programmed for
`[0035]
`a 16-bit point-to-point connection, then each inbound link
`layer 804, 814, 818, 820 acts independently. The arbiter 802
`directs the fifth signal pathway switching device 822 to
`request inform