&
`
`CM& Morgan Claypool Publishers
`A Primer on Memory
`Consistency and
`Cache Coherence
`
`Daniel J. Sorin
`Mark D. Hill
`David A. Wood
`
`SYNTHESIS LECTURES ON
`COMPUTER ARCHITECTURE
`Mark D. Hill, Series Editor
`
`SORIN • HILL • WOOD
`
`A PRIMER ON MEMORY CONSISTENCY AND CACHE COHERENCE
`
`MORGAN & CLAYPOOL
`
`Series ISSN: 1935-3235
`
`SYNTHESIS LECTURES ON
`COMPUTER ARCHITECTURE
`Series Editor: Mark D. Hill, University of Wisconsin
`A Primer on Memory Consistency
`and Cache Coherence
`Daniel J. Sorin, Duke University
`Mark D. Hill and David A. Wood, University of Wisconsin, Madison
`
`Many modern computer systems and most multicore chips (chip multiprocessors) support shared
`memory in hardware. In a shared memory system, each of the processor cores may read and write to
`a single shared address space. For a shared memory machine, the memory consistency model defines
`the architecturally visible behavior of its memory system. Consistency definitions provide rules about
`loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting
`a memory consistency model, many machines also provide cache coherence proto-cols that ensure that
`multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with
`a basic understanding of consistency and coherence. This understanding includes both the issues that
`must be solved as well as a variety of solutions. We present both high-level concepts as well as specific,
`concrete examples from real-world systems.
`
`About SYNTHESIs
`This volume is a printed version of a work that appears in the Synthesis
`Digital Library of Engineering and Computer Science. Synthesis Lectures
`provide concise, original presentations of important research and development
`topics, published quickly, in digital and print formats. For more information
`visit www.morganclaypool.com
`&
`Morgan Claypool Publishers
`w w w . m o r g a n c l a y p o o l . c o m
`
`ISBN: 978-1-60845-564-5
`90000
`
`9 781608 455645
`
`

`
`

`
`A Primer on Memory Consistency
`and Cache Coherence
`
`

`
`ii
`
`One liner Chapter TitleSynthesis Lectures on Computer
`
`Architecture
`
`Editor
`Mark D. Hill, University of Wisconsin
`Synthesis Lectures on Computer Architecture publishes 50- to 100-page publications on topics
`pertaining to the science and art of designing, analyzing, selecting and interconnecting hardware
`components to create computers that meet functional, performance and cost goals. The scope will
`largely follow the purview of premier computer architecture conferences, such as ISCA, HPCA,
`MICRO, and ASPLOS.
`
`A Primer on Memory Consistency and Cache Coherence
`Daniel J. Sorin, Mark D. Hill, and David A. Wood
`2011
`
`Dynamic Binary Modification: Tools, Techniques, and Applications
`Kim Hazelwood
`2011
`
`Quantum Computing for Computer Architects, Second Edition
`Tzvetan S. Metodi, Arvin I. Faruque, Frederic T. Chong
`2011
`
`High Performance Datacenter Networks: Architectures, Algorithms, and Opportunities
`Dennis Abts, John Kim
`2011
`
`Processor Microarchitecture: An Implementation Perspective
`Antonio González, Fernando Latorre, and Grigorios Magklis
`2011
`
`Transactional Memory, 2nd edition
`Tim Harris, James Larus, and Ravi Rajwar
`2010
`
`

`
`iii
`
`Computer Architecture Performance Evaluation Models
`Lieven Eeckhout
`2010
`
`Introduction to Reconfigurable Supercomputing
`Marco Lanzagorta, Stephen Bique, and Robert Rosenberg
`2009
`
`On-Chip Networks
`Natalie Enright Jerger and Li-Shiuan Peh
`2009
`
`The Memory System: You Can’t Avoid It, You Can’t Ignore It, You Can’t Fake It
`Bruce Jacob
`2009
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`Fault Tolerant Computer Architecture
`Daniel J. Sorin
`2009
`
`The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines
`Luiz André Barroso and Urs Hölzle
`2009
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`Computer Architecture Techniques for Power-Efficiency
`Stefanos Kaxiras and Margaret Martonosi
`2008
`
`Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency
`Kunle Olukotun, Lance Hammond, and James Laudon
`2007
`
`Transactional Memory
`James R. Larus and Ravi Rajwar
`2006
`
`Quantum Computing for Computer Architects
`Tzvetan S. Metodi and Frederic T. Chong
`2006
`
`

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`Copyright © 2011 by Morgan & Claypool
`
`All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
`any form or by any means—electronic, mechanical, photocopy, recording, or any other except for brief quotations
`in printed reviews, without the prior permission of the publisher.
`
`A Primer on Memory Consistency and Cache Coherence
`Daniel J. Sorin, Mark D. Hill, and David A. Wood
`www.morganclaypool.com
`
`ISBN: 9781608455645 paperback
`
`ISBN: 9781608455652 ebook
`
`DOI: 10.2200/S00346ED1V01Y201104CAC016
`
`A Publication in the Morgan & Claypool Publishers series
`
`SYNTHESIS LECTURES ON COMPUTER ARCHITECTURE #16
`
`Lecture #16
`
`Series Editor: Mark D. Hill, University of Wisconsin
`
`Series ISSN
`ISSN 1935-3235
`ISSN 1935-3243
`
`print
`electronic
`
`

`
`A Primer on Memory Consistency
`and Cache Coherence
`
`Daniel J. Sorin, Mark D. Hill, and David A. Wood
`
`SYNTHESIS LECTURES ON COMPUTER ARCHITECTURE #16
`
`

`
`vi
`
`ABSTRACT
`Many modern computer systems and most multicore chips (chip multiprocessors) support shared
`memory in hardware. In a shared memory system, each of the processor cores may read and write
`to a single shared address space. For a shared memory machine, the memory consistency model
`defines the architecturally visible behavior of its memory system. Consistency definitions provide
`rules about loads and stores (or memory reads and writes) and how they act upon memory. As part
`of supporting a memory consistency model, many machines also provide cache coherence proto-
`cols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer
`is to provide readers with a basic understanding of consistency and coherence. This understanding
`includes both the issues that must be solved as well as a variety of solutions. We present both high-
`level concepts as well as specific, concrete examples from real-world systems.
`
`KEYWORDS
`computer architecture, memory consistency, cache coherence, shared memory, memory systems,
`multicore processor, multiprocessor
`
`

`
`vii
`
`Preface
`
`This primer is intended for readers who have encountered memory consistency and cache coher-
`ence informally, but now want to understand what they entail in more detail. This audience includes
`computing industry professionals as well as junior graduate students.
`We expect our readers to be familiar with the basics of computer architecture. Remembering
`the details of Tomasulo’s algorithm or similar details is unnecessary, but we do expect readers to
`understand issues like architectural state, dynamic instruction scheduling (out-of-order execution),
`and how caches are used to reduce average latencies to access storage structures.
`The primary goal of this primer is to provide readers with a basic understanding of consis-
`tency and coherence. This understanding includes both the issues that must be solved as well as a
`variety of solutions. We present both high-level concepts as well as specific, concrete examples from
`real-world systems. A secondary goal of this primer is to make readers aware of just how complicated
`consistency and coherence are. If readers simply discover what it is that they do not know—without
`actually learning it—that discovery is still a substantial benefit. Furthermore, because these topics
`are so vast and so complicated, it is beyond the scope of this primer to cover them exhaustively. It
`is not a goal of this primer to cover all topics in depth, but rather to cover the basics and apprise the
`readers of what topics they may wish to pursue in more depth.
`We owe many thanks for the help and support we have received during the development of
`this primer. We thank Blake Hechtman for implementing and testing (and debugging!) all of the
`coherence protocols in this primer. As the reader will soon discover, coherence protocols are com-
`plicated, and we would not have trusted any protocol that we had not tested, so Blake’s work was
`tremendously valuable. Blake implemented and tested all of these protocols using the Wisconsin
`GEMS simulation infrastructure [http://www.cs.wisc.edu/gems/].
`For reviewing early drafts of this primer and for helpful discussions regarding various topics
`within the primer, we gratefully thank Trey Cain and Milo Martin. For providing additional feed-
`back on the primer, we thank Newsha Ardalani, Arkaprava Basu, Brad Beckmann, Bob Cypher, Joe
`Devietti, Sandip Govind Dhoot, Alex Edelsburg, Jayneel Gandhi, Dan Gibson, Marisabel Gue-
`vara, Gagan Gupta, Blake Hechtman, Derek Hower, Zachary Marzec, Hiran Mayukh, Ralph Na-
`than, Marc Orr, Vijay Sathish, Abhirami Senthilkumaran, Simha Sethumadhavan, Venkatanathan
`
`

`
`viii A PRIMER ON MEMORY CONSISTENCY AND CACHE COHERENCE
`
`Varadarajan, Derek Williams, and Meng Zhang. While our reviewers provided great feedback, they
`may or may not agree with all of the final contents of this primer.
`This work is supported in part by the National Science Foundation (CNS-0551401, CNS-
`0720565, CCF-0916725, CCF-0444516, and CCF-0811290), Sandia/DOE (#MSN123960/
`DOE890426), Semiconductor Research Corporation (contract 2009-HJ-1881), and the University
`of Wisconsin (Kellett Award to Hill). The views expressed herein are not necessarily those of the
`NSF, Sandia, DOE, or SRC.
`Dan thanks Deborah, Jason, and Julie for their love and for putting up with him taking the
`time to work on another synthesis lecture. Dan thanks his Uncle Sol for helping inspire him to be
`an engineer in the first place. Lastly, Dan dedicates this book to the memory of Rusty Sneiderman,
`a treasured friend of thirty years who will be dearly missed by everyone who was lucky enough to
`have known him.
`Mark wishes to thank Sue, Nicole, and Gregory for their love and support.
`David thanks his coauthors for putting up with his deadline-challenged work style, his par-
`ents Roger and Ann Wood for inspiring him to be a second-generation Computer Sciences profes-
`sor, and Jane, Alex, and Zach for helping him remember what life is all about.
`
`

`
`ix
`
`Contents
`
`Preface ....................................................................................................................... ix
`
`1.
`
`2.
`
`Introduction to Consistency and Coherence .........................................................1
`1.1 Consistency (a.k.a., Memory Consistency, Memory Consistency Model,
`or Memory Model) .............................................................................................. 2
`1.2 Coherence (a.k.a., Cache Coherence) .................................................................. 4
`1.3 A Consistency and Coherence Quiz .................................................................... 6
`1.4 What this Primer Does Not Do .......................................................................... 6
`
`Coherence Basics ................................................................................................9
`2.1 Baseline System Model ....................................................................................... 9
`2.2 The Problem: How Incoherence Could Possibly Occur .................................... 10
`2.3 Defining Coherence .......................................................................................... 11
`2.3.1 Maintaining the Coherence Invariants .................................................. 13
`2.3.2 The Granularity of Coherence .............................................................. 13
`2.3.3 The Scope of Coherence ....................................................................... 15
`2.4 References .......................................................................................................... 15
`
`3. Memory Consistency Motivation and Sequential Consistency ............................ 17
`3.1 Problems with Shared Memory Behavior .......................................................... 17
`3.2 What Is a Memory Consistency Model? ........................................................... 20
`3.3 Consistency vs. Coherence ................................................................................ 21
`3.4 Basic Idea of Sequential Consistency (SC) ........................................................ 22
`3.5 A Little SC Formalism ...................................................................................... 24
`3.6 Naive SC Implementations ............................................................................... 26
`3.7 A Basic SC Implementation with Cache Coherence......................................... 27
`3.8 Optimized SC Implementations with Cache Coherence .................................. 29
`3.9 Atomic Operations with SC .............................................................................. 32
`3.10 Putting it All Together: MIPS R10000 ............................................................. 33
`
`

`
`x A PRIMER ON MEMORY CONSISTENCY AND CACHE COHERENCE
`
`4.
`
`5.
`
`3.11 Further Reading Regarding SC ......................................................................... 34
`3.12 References .......................................................................................................... 35
`
`Total Store Order and the x86 Memory Model .................................................... 37
`4.1 Motivation for TSO/x86 ................................................................................... 37
`4.2 Basic Idea of TSO/x86 ...................................................................................... 38
`4.3 A Little TSO Formalism and an x86 Conjecture .............................................. 42
`Implementing TSO/x86 .................................................................................... 45
`4.4
`4.5 Atomic Instructions and Fences with TSO ....................................................... 46
`4.5.1 Atomic Instructions ............................................................................... 46
`4.5.2 Fences .................................................................................................... 47
`4.6 Further Reading Regarding TSO ...................................................................... 47
`4.7 Comparing SC and TSO ................................................................................... 48
`4.8 References .......................................................................................................... 49
`
`5.3
`
`Relaxed Memory Consistency ............................................................................ 51
`5.1 Motivation ......................................................................................................... 51
`5.1.1 Opportunities to Reorder Memory Operations ..................................... 52
`5.1.2 Opportunities to Exploit Reordering .................................................... 53
`5.2 An Example Relaxed Consistency Model (XC) ................................................ 55
`5.2.1 The Basic Idea of the XC Model........................................................... 55
`5.2.2 Examples Using Fences under XC......................................................... 56
`5.2.3 Formalizing XC ..................................................................................... 57
`5.2.4 Examples Showing XC Operating Correctly......................................... 59
`Implementing XC ............................................................................................. 61
`5.3.1 Atomic Instructions with XC ................................................................ 62
`5.3.2 Fences with XC ..................................................................................... 64
`5.3.3 A Caveat ................................................................................................ 64
`5.4 Sequential Consistency for Data-Race-Free Programs ..................................... 64
`5.5 Some Relaxed Model Concepts ......................................................................... 68
`5.5.1 Release Consistency ............................................................................... 68
`5.5.2 Causality and Write Atomicity .............................................................. 69
`5.6 A Relaxed Memory Model Case Study: IBM Power ........................................ 70
`5.7 Further Reading and Commercial Relaxed Memory Models ............................ 74
`5.7.1 Academic Literature .............................................................................. 74
`5.7.2 Commercial Models .............................................................................. 74
`
`

`
`6.
`
`7.
`
`CONTENTS xi
`
`5.8 Comparing Memory Models ............................................................................. 75
` How Do Relaxed Memory Models Relate to Each Other and
`5.8.1
`TSO and SC? ............................................................................... ......... 75
`5.8.2 How Good Are Relaxed Models? .......................................................... 76
`5.9 High-Level Language Models .......................................................................... 76
`5.10 References .......................................................................................................... 79
`
`Coherence Protocols ......................................................................................... 83
`6.1 The Big Picture ................................................................................................. 83
`6.2 Specifying Coherence Protocols ........................................................................ 85
`6.3 Example of a Simple Coherence Protocol ......................................................... 86
`6.4 Overview of Coherence Protocol Design Space ................................................ 88
`6.4.1 States ..................................................................................................... 88
`6.4.2 Transactions ........................................................................................... 92
`6.4.3 Major Protocol Design Options ............................................................ 95
`6.5 References .......................................................................................................... 97
`
`7.2.3
`
`Snooping Coherence Protocols .......................................................................... 99
`7.1
`Introduction to Snooping .................................................................................. 99
`7.2 Baseline Snooping Protocol ............................................................................. 103
`7.2.1 High-Level Protocol Specification ...................................................... 104
` Simple Snooping System Model: Atomic Requests,
`7.2.2
`Atomic Transactions ..................................................................... ....... 104
` Baseline Snooping System Model: Non-Atomic Requests,
`Atomic Transactions ..................................................................... ....... 109
`7.2.4 Running Example ................................................................................ 113
`7.2.5 Protocol Simplifications....................................................................... 114
`7.3 Adding the Exclusive State.............................................................................. 115
`7.3.1 Motivation ........................................................................................... 115
`7.3.2 Getting to the Exclusive State ............................................................. 115
`7.3.3 High-Level Specification of Protocol .................................................. 116
`7.3.4 Detailed Specification .......................................................................... 118
`7.3.5 Running Example ................................................................................ 119
`7.4 Adding the Owned State ................................................................................. 119
`7.4.1 Motivation ........................................................................................... 119
`7.4.2 High-Level Protocol Specification ...................................................... 121
`
`

`
`xii A PRIMER ON MEMORY CONSISTENCY AND CACHE COHERENCE
`
`7.4.3 Detailed Protocol Specification ........................................................... 121
`7.4.4 Running Example ................................................................................ 122
`7.5 Non-Atomic Bus ............................................................................................. 123
`7.5.1 Motivation ........................................................................................... 124
`7.5.2 In-Order vs. Out-of-Order Responses ................................................ 124
`7.5.3 Non-Atomic System Model ................................................................ 124
`7.5.4 An MSI Protocol with a Split-Transaction Bus .................................. 126
` An Optimized, Non-Stalling MSI Protocol with a
`7.5.5
`Split-Transaction Bus ................................................................... ....... 130
`7.6 Optimizations to the Bus Interconnection Network ....................................... 132
`7.6.1 Separate Non-Bus Network for Data Responses ................................. 132
`7.6.2 Logical Bus for Coherence Requests ................................................... 133
`7.7 Case Studies .................................................................................................... 133
`7.7.1 Sun Starfire E10000 ............................................................................ 133
`7.7.2 IBM Power5 ........................................................................................ 135
`7.8 Discussion and the Future of Snooping ........................................................... 137
`7.9 References ........................................................................................................ 138
`
`8. Directory Coherence Protocols ........................................................................ 139
`8.1
`Introduction to Directory Protocols ................................................................ 139
`8.2 Baseline Directory System ............................................................................... 141
`8.2.1 Directory System Model ..................................................................... 141
`8.2.2 High-level Protocol Specification ........................................................ 142
`8.2.3 Avoiding Deadlock .............................................................................. 144
`8.2.4 Detailed Protocol Specification ........................................................... 146
`8.2.5 Protocol Operation .............................................................................. 147
`8.2.6 Protocol Simplifications....................................................................... 149
`8.3 Adding the Exclusive State.............................................................................. 150
`8.3.1 High-Level Protocol Specification ...................................................... 150
`8.3.2 Detailed Protocol Specification ........................................................... 152
`8.4 Adding the Owned State ................................................................................. 153
`8.4.1 High-Level Protocol Specification ..................................................... 153
`8.4.2 Detailed Protocol Specification ......................................................... 155
`8.5 Representing Directory State .......................................................................... 156
`8.5.1 Coarse Directory ................................................................................ 157
`8.5.2 Limited Pointer Directory .................................................................. 157
`
`

`
`CONTENTS xiii
`
`8.6 Directory Organization ................................................................................... 158
`8.6.1 Directory Cache Backed by DRAM ................................................... 159
`8.6.2 Inclusive Directory Caches .................................................................. 160
`8.6.3 Null Directory Cache (with no backing store)..................................... 163
`8.7 Performance and Scalability Optimizations..................................................... 163
`8.7.1 Distributed Directories ........................................................................ 163
`8.7.2 Non-Stalling Directory Protocols ........................................................ 164
`8.7.3 Interconnection Networks without Point-to-Point Ordering .............. 166
`8.7.4 Silent vs. Non-Silent Evictions of Blocks in State S ........................... 168
`8.8 Case Studies .................................................................................................... 169
`8.8.1 SGI Origin 2000 ................................................................................. 169
`8.8.2 Coherent HyperTransport ................................................................... 171
`8.8.3 HyperTransport Assist......................................................................... 172
`8.8.4 Intel QPI ............................................................................................. 173
`8.9 Discussion and the Future of Directory Protocols ........................................... 175
`8.10 References ........................................................................................................ 175
`
`Advanced Topics in Coherence ........................................................................ 177
`9.1 System Models ................................................................................................ 177
`9.1.1 Instruction Caches ............................................................................... 177
`9.1.2 Translation Lookaside Buffers (TLBs) ................................................ 178
`9.1.3 Virtual Caches ..................................................................................... 179
`9.1.4 Write-Through Caches ....................................................................... 180
`9.1.5 Coherent Direct Memory Access (DMA)........................................... 180
`9.1.6 Multi-Level Caches and Hierarchical Coherence Protocols ............... 181
`9.2 Performance Optimizations ............................................................................. 184
`9.2.1 Migratory Sharing Optimization ........................................................ 184
`9.2.2 False Sharing Optimizations ............................................................... 185
`9.3 Maintaining Liveness ...................................................................................... 186
`9.3.1 Deadlock ............................................................................................. 186
`9.3.2 Livelock ............................................................................................... 189
`9.3.3 Starvation ............................................................................................ 192
`9.4 Token Coherence ............................................................................................. 193
`9.5 The Future of Coherence ................................................................................ 193
`9.6 References ........................................................................................................ 193
`
`9.
`
`Author Biographies .................................................................................................. 197
`
`

`
`

`
`1
`
`C H A P T E R 1
`Introduction to Consistency
`and Coherence
`
`Many modern computer systems and most multicore chips (chip multiprocessors) support shared
`memory in hardware. In a shared memory system, each of the processor cores may read and write to
`a single shared address space. These designs seek various goodness properties, such as high perfor-
`mance, low power, and low cost. Of course, it is not valuable to provide these goodness properties
`without first providing correctness. Correct shared memory seems intuitive at a hand-wave level,
`but, as this lecture will help show, there are subtle issues in even defining what it means for a shared
`memory system to be correct, as well as many subtle corner cases in designing a correct shared
`memory implementation. Moreover, these subtleties must be mastered in hardware implementa-
`tions where bug fixes are expensive. Even academics should master these subtleties to make it more
`likely that their proposed designs will work.
`We and many others find it useful to separate shared memory correctness into two sub-issues:
`consistency and coherence. Computer systems are not required to make this separation, but we find
`it helps to divide and conquer complex problems, and this separation prevails in many real shared
`memory implementations.
`It is the job of consistency (memory consistency, memory consistency model, or memory
`model) to define shared memory correctness. Consistency definitions provide rules about loads and
`stores (or memory reads and writes) and how they act upon memory. Ideally, consistency definitions
`would be simple and easy to understand. However, defining what it means for shared memory to
`behave correctly is more subtle than defining the correct behavior of, for example, a single-threaded
`processor core. The correctness criterion for a single processor core partitions behavior between one
`correct result and many incorrect alternatives. This is because the processor’s architecture mandates
`that the execution of a thread transforms a given input state into a single well-defined output state,
`even on an out-of-order core. Shared memory consistency models, however, concern the loads and
`stores of multiple threads and usually allow many correct executions while disallowing many (more)
`incorrect ones. The possibility of multiple correct executions is due to the ISA allowing multiple
`threads to execute concurrently, often with many possible legal interleavings of instructions from
`
`

`
`2 A PRIMER ON MEMORY CONSISTENCY AND CACHE COHERENCE
`
`different threads. The multitude of correct executions complicates the erstwhile simple challenge of
`determining whether an execution is correct. Nevertheless, consistency must be mastered to imple-
`ment shared memory and, in some cases, to write correct programs that use it.
`Unlike consistency, coherence (or cache coherence) is neither visible to software nor required.
`However, as part of supporting a consistency model, the vast majority of shared memory systems
`implement a coherence protocol that provides coherence. Coherence seeks to make the caches of
`a shared-memory system as functionally invisible as the caches in a single-core system. Correct
`coherence ensures that a programmer cannot determine whether and where a system has caches by
`analyzing the results of loads and stores. This is because correct coherence ensures that the caches
`never enable new or different functional behavior (programmers may still be able to infer likely cache
`structure using timing information).
`In most systems, coherence protocols play an important role in providing consistency. Thus,
`even though consistency is the first major topic of this primer, we begin in Chapter 2 with a brief
`introduction to coherence. The goal of this chapter is to explain enough about coherence to under-
`stand how consistency models interact with coherent caches, but not to explore specific coherence
`protocols or implementations, which are topics we defer until the second portion of this primer in
`Chapters 6–9. In Chapter 2, we define coherence using the single-writer–multiple-reader (SWMR)
`invariant. SWMR requires that, at any given time, a memory location is either cached for writing
`(and reading) at one cache or cached only for reading at zero to many caches.
`
`1.1
`
`CONSISTENCY (A.K.A., MEMORY CONSISTENCY, MEMORY
`CONSISTENCY MODEL, OR MEMORY MODEL)
`Consistency models define correct shared memory behavior in terms of loads and stores (memory
`reads and writes), without reference to caches or coherence. To gain some real-world intuition on
`why we need consistency models, consider a university that posts its course schedule online. As-
`sume that the Computer Architecture course is originally scheduled to be in Room 152. The day
`before classes begin, the university registrar decides to move the class to Room 252. The registrar
`sends an e-mail message asking the web site administrator to update the online schedule, and a few
`minutes later, the registrar sends a text message to all registered students