Trials@uspto.gov
`Tel: 571-272-7822
`
`Paper 7
`Entered: May 21, 2015
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SONY CORPORATION, SONY ELECTRONICS INC.,
`SONY MOBILE COMMUNICATIONS AB, and
`SONY MOBILE COMMUNICATIONS (USA) INC.,
`Petitioner,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`
`Case IPR2015-00158
`Patent 7,296,121 B2
`
`
`
`
`
`
`
`
`
`Before JENNIFER S. BISK, NEIL T. POWELL, and
`KERRY BEGLEY, Administrative Patent Judges.
`
`POWELL, Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`Tel: 571-272-7822
`
`Paper 7
`Entered: May 21, 2015
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SONY CORPORATION, SONY ELECTRONICS INC.,
`SONY MOBILE COMMUNICATIONS AB, and
`SONY MOBILE COMMUNICATIONS (USA) INC.,
`Petitioner,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`
`Case IPR2015-00158
`Patent 7,296,121 B2
`
`
`
`
`
`
`
`
`
`Before JENNIFER S. BISK, NEIL T. POWELL, and
`KERRY BEGLEY, Administrative Patent Judges.
`
`POWELL, Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`Case IPR2015-00158
`Patent 7,296,121 B2
`
`A. Background
`
`I. INTRODUCTION
`
`Sony Corporation, Sony Electronics Inc., Sony Mobile
`
`Communications AB, and Sony Mobile Communications (USA) Inc.
`
`(collectively, “Petitioner”) filed a Petition requesting an inter partes review
`
`of claims 1–3, 8, 11, 12, and 14–25 (the “challenged claims”) of U.S. Patent
`
`No. 7,296,121 B2 (Ex. 1001, “the ’121 patent”). Patent Owner, Memory
`
`Integrity, LLC, filed a Preliminary Response. Paper 6 (“Prelim. Resp.”).
`
`We have authority to determine whether to institute an inter partes
`
`review. 35 U.S.C. § 314(a); 37 C.F.R. § 42.4(a). The standard for
`
`instituting an inter partes review is set forth in 35 U.S.C. § 314(a), which
`
`provides that an inter partes review may not be instituted “unless the
`
`Director determines . . . there is a reasonable likelihood that the petitioner
`
`would prevail with respect to at least 1 of the claims challenged in the
`
`petition.”
`
`After considering the Petition and Preliminary Response, we
`
`determine that Petitioner has established a reasonable likelihood of
`
`prevailing in showing the unpatentability of claims 19–24. Accordingly, we
`
`institute inter partes review of these challenged claims. We decline to
`
`institute an inter partes review of claims 1–3, 8, 11, 12, 14–18, and 25.
`
`B. Related Matters
`
`The parties indicate that the ’121 patent is the subject of several
`
`proceedings in the United States District Court for the District of Delaware.
`
`Pet. 1; Paper 4, 1–2. In addition, another party filed four petitions seeking
`
`inter partes review of the ’121 patent—IPR2015-00159, IPR2015-00161,
`
`IPR2015-00163, and IPR2015-00172.
`
`2
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`Patent 7,296,121 B2
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`C. The Asserted Grounds of Unpatentability
`
`Petitioner contends that claims 1–3, 8, 11, 12, and 14–25 of the ’121
`
`patent are unpatentable under 35 U.S.C. §§ 102 and/or 103 based on the
`
`following grounds (Pet. 3):1
`
`Ground
`§ 102
`
`§ 103
`§ 103
`§ 103
`§ 103
`
`§ 103
`§ 103
`
`Reference(s)
`Koster2
`
`Koster
`Koster and Kuskin3
`Koster, Kuskin, and Park4
`Luick5 and Kosaraju6
`
`Challenged Claims
`1–3, 8, 11, 12, 14–16, and
`25
`17, 18, and 24
`19–23
`15 and 25
`1–3, 8, 11, 12, 14–18, 24,
`and 25
`Luick, Kosaraju, and Kuskin 19–23
`Luick, Kosaraju, Kuskin,
`15 and 25
`and Park
`
`D. The ’121 Patent
`
`The ’121 patent relates to accessing data in computer systems that
`
`include more than one processor. Ex. 1001, 1:23–24. Specifically, the ’121
`
`patent discusses multiple processor systems with a point-to-point
`
`architecture—a cluster of individual processors (also referred to as
`
`processing nodes) that are directly connected to each other through point-to-
`
`
`1 Petitioner also provides a declaration from Daniel J. Sorin, Ph.D. Ex.
`1013.
`2 U.S. Patent No. 7,698,509 B1 (Ex. 1005, “Koster”).
`3 Jeffrey Kuskin et al., The Stanford FLASH Multiprocessor, in
`PROCEEDINGS OF THE 21ST ANNUAL INTERNATIONAL SYMPOSIUM ON
`COMPUTER ARCHITECTURE 302 (1994) (Ex. 1006, “Kuskin”).
`4 S. Park & D.L. Dill, Verification of Cache Coherence Protocols by
`Aggregation of Distributed Transactions, 31 THEORY OF COMPUTING
`SYSTEMS 355 (1998) (Ex. 1007, “Park”).
`5 U.S. Patent No. 6,088,769 (Ex. 1008, “Luick”).
`6 U.S. Patent Application No. 2002/0073261 A1 (Ex. 1009, “Kosaraju”).
`
`3
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`point links, each with an associated cache memory. Id. at 4:38–40. To
`
`increase the number of available processors, multiple clusters may be
`
`connected. Id. at 4:50–53. Figure 1A is reproduced below.
`
`
`
`Figure 1A shows an example of a multiple cluster, multiple processor
`
`system described by the ’121 patent. Id. at 6:10–12. Figure 1A includes
`
`four processing clusters, 101, 103, 105, and 107, each of which can, in turn,
`
`include multiple processors. Id. at 6:12–14. The clusters are connected
`
`through point-to-point links 111a–f. Id. at 6:14–16.
`
`The ’121 patent explains that cache coherency problems can arise in
`
`such a system, because it may contain multiple copies of the same data. Id.
`
`at 1:26–38. For example, if the caches of two different processors have a
`
`copy of the same data block and both processors “attempt to write new
`
`values into the data block at the same time,” then the two caches may have
`
`different data values and the system may be “unable to determine what value
`
`to write through to system memory.” Id. at 1:37–45. Solutions to cache
`
`4
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`coherency problems often involve an increase in communication traffic and
`
`a resulting decrease in efficiency. Id. at 1:23–26, 2:46–48. The ’121 patent
`
`discloses “techniques . . . for increasing data access efficiency in a multiple
`
`processor system,” while also addressing cache coherency. Id. at 4:36–38.
`
`The ’121 patent discloses a system that includes a probe filtering unit.
`
`Id. at 2:52–65. A probe is defined as “[a] mechanism for eliciting a response
`
`from a node to maintain cache coherency in a system.” Id. at 5:45–47. As
`
`opposed to a traditional approach of broadcasting probes to all nodes, the
`
`probe filtering unit reduces traffic by intercepting the probes and
`
`transmitting them only to those nodes that require the information based on
`
`probe filtering information, i.e., “[a]ny criterion that can be used to reduce
`
`the number of clusters or nodes probed.” Id. at 2:52–3:5, 14:50–52; see id.
`
`at 28:29–58, 29:43–46. The probe filtering unit also may accumulate
`
`responses from those nodes selected to receive the probes and respond to the
`
`node from which the probe originated. Id. at 3:5–8, 28:59–67, 29:46–51.
`
`Figure 18 of the ’121 patent is reproduced below.
`
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`
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`Figure 18 shows a multiple processor system with a probe filtering
`
`unit. Id. at 3:61–63, 26:58–27:20, Fig. 18. Specifically, Figure 18 depicts
`
`multiple processor system 1800 with processing nodes 1802a–d
`
`interconnected by point-to-point communication links 1808a–e. Id. at
`
`26:58–27:1. System 1800 also includes probe filtering unit 1830 as well as
`
`I/O switch 1810, one or more Basic I/O systems (“BIOS”) 1804, I/O
`
`adapters 1816, 1820, and a memory subsystem with memory banks 1806a–
`
`d. Id. at 3:61–63, 26:58–27:20, Fig. 18.
`
`E. Illustrative Claim
`
`Claims 1, 16, and 25 of the ’121 patent are independent. Claim 1 is
`
`illustrative of the claimed subject matter and recites:
`
`6
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`Case IPR2015-00158
`Patent 7,296,121 B2
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`1. A computer system comprising a plurality of processing
`nodes interconnected by a first point-to-point architecture,
`
`each processing node having a cache memory associated
`therewith,
`
`the computer system further comprising a probe filtering unit
`which is operable to receive probes corresponding to memory
`lines from the processing nodes and to transmit the probes only
`to selected ones of the processing nodes with reference to probe
`filtering information representative of states associated with
`selected ones of the cache memories.
`
`Ex. 1001, 30:65–31:7 (line breaks added).
`
`A. Claim Construction
`
`II. ANALYSIS
`
`We interpret claims of an unexpired patent using the broadest
`
`reasonable construction in light of the specification of the patent in which
`
`they appear. 37 C.F.R. § 42.100(b); see In re Cuozzo Speed Techs., LLC.,
`
`778 F.3d 1271, 1281 (Fed. Cir. 2015). We presume a claim term carries its
`
`“ordinary and customary meaning,” which is “the meaning that the term
`
`would have to a person of ordinary skill in the art in question” at the time of
`
`the invention. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir.
`
`2007) (citation and quotations omitted). This presumption, however, is
`
`rebutted when the patentee acts as his own lexicographer by giving the term
`
`a particular meaning in the specification with “reasonable clarity,
`
`deliberateness, and precision.” In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir.
`
`1994).
`
`Petitioner and Patent Owner proffer proposed constructions of several
`
`claim terms. For purposes of this decision, we determine that only the claim
`
`terms discussed below require express construction.
`
`7
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`1. “probe”
`
`
`
`Petitioner argues that the ’121 patent expressly defines “probe,” as
`
`recited in challenged claims 1, 8, 11, 14–16, and 25. Pet. 16. Patent Owner
`
`does not respond to this argument. We agree that the ’121 patent defines the
`
`term “probe.” Ex. 1001, 5:45–47. On the record before us, we adopt this
`
`definition as the broadest reasonable construction of the claim term “probe”:
`
`“[a] mechanism for eliciting a response from a node to maintain cache
`
`coherency in a system.” Id.
`
`2. “probe filtering information”
`
`
`
`Petitioner argues that the ’121 patent expressly defines “probe
`
`filtering information,” as recited in challenged claims 1, 3, 16, and 25.
`
`Pet. 16. Patent Owner does not respond to this argument. We agree that the
`
`’121 patent defines the term “probe filter information.” Ex. 1001, 14:50–52.
`
`On the record before us, we adopt this definition as the broadest reasonable
`
`construction of the claim term “probe filtering information”: “[a]ny
`
`criterion that can be used to reduce the number of clusters or nodes probed.”
`
`Id.
`
`3. “states associated with selected ones of the cache memories”
`
`Claims 1, 16, and 25 recite “probe filtering information”
`
`“representative of states associated with selected ones of the cache
`
`memories.” Petitioner does not propose a construction of this claim
`
`language. Patent Owner proposes that the language means “cache coherence
`
`protocol states associated with data blocks stored in selected ones of the
`
`cache memories” where a “cache coherence protocol state” means
`
`the current state of a data block in a protocol used to
`maintain the coherency of caches, in which a data block
`
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`can only be in one current state at a time, and in which
`the current state can transition to a different state upon
`one or more triggering events or conditions.
`
`Prelim. Resp. 14–15.
`
`At this preliminary stage of this proceeding, for the reasons discussed
`
`below, we are not persuaded that Patent Owner’s proposal accurately
`
`represents the broadest reasonable construction of the term “states associated
`
`with selected ones of the cache memories.” For purposes of this decision,
`
`we do not adopt a construction of the term and instead address an aspect of
`
`its scope.
`
`We are not persuaded that the ’121 patent supports Patent Owner’s
`
`assertion that “states” refers solely to cache coherence protocol states. Id. at
`
`15–16. Patent Owner argues that “the specification explains that in some
`
`embodiments, ‘information’ which is stored “corresponds to the standard
`
`coherence protocol states which include ‘invalid’ (not cached in any
`
`remote clusters), ‘shared’ (cached as ‘clean’ and read-only), ‘modified’
`
`(cached as ‘dirty’ and read/write), and ‘owned’ (cached as ‘dirty’ but read-
`
`only).’” Id. at 15. Patent Owner then points to two examples of potential
`
`states given in the ’121 patent: “the four states of modified, owned, shared,
`
`and invalid” and “the five states of modified, exclusive, owned, shared, and
`
`invalid.” Id. (quoting Ex. 1001, 14:30–36) (emphasis omitted). Patent
`
`Owner also points to discussion in the ’121 patent of the probe filtering unit
`
`using a directory of shared states that “may be implemented as described
`
`above with reference to FIGS. 7 and 8” (Ex. 1001, 28:25–34), which show
`
`similar states in diagram form. Prelim. Resp. 15–16 (citing Ex. 1001,
`
`13:44–15:19, 28:25–34, Figs. 7, 8). The ’121 patent, however, sets these
`
`examples within broad language stating that “particular implementations
`
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`may use a different set of states” and “[t]he techniques of the present
`
`invention can be used with a variety of different possible memory line
`
`states.” Ex. 1001, 14:30–36. We are, thus, not persuaded that these
`
`examples limit the broadest reasonable construction of the term “states” to
`
`cache coherence protocol states, as asserted by Patent Owner.
`
`In addition, because we are not persuaded that the term “states” is
`
`limited to cache coherence protocol states, we are not persuaded by Patent
`
`Owner’s further limitations to the term “states associated with selected ones
`
`of the cache memories” based on aspects of cache coherence protocol states.
`
`See Prelim. Resp. 16–22.
`
`At this preliminary stage of this proceeding, we decline to adopt
`
`Patent Owner’s proposed construction of the term “states associated with
`
`selected ones of the cache memories.” Instead, for purposes of this decision,
`
`we conclude only that, on this record, the term is not limited to cache
`
`coherence protocol states and is broad enough to include the condition of
`
`presence—i.e., what is stored in cache memory. See Ex. 1001, 14:30–36,
`
`28:29–34 (“The PFU accepts the probe and looks up the address in its
`
`directory of shared cache states . . . [that] indicates where particular memory
`
`lines are cached within the cluster.”). This conclusion is further supported
`
`by extrinsic evidence, particularly the definition of “state” in MICROSOFT
`
`COMPUTER DICTIONARY: “[t]he condition at a particular time of any of
`
`numerous elements of computing—a device, a communications channel, a
`
`network station, a program, a bit, or other element—used to report on or to
`
`control computer operations.” Ex. 3001 (MICROSOFT COMPUTER
`
`DICTIONARY (5th ed. 2002)), 497–98.
`
`10
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`4. “cache coherence controller”
`
`Petitioner correctly contends that the ’121 patent defines “cache
`
`coherence controller,” as recited in challenged claim 3. Pet. 16. Patent
`
`Owner does not address this assertion. For purposes of this decision, we
`
`adopt this express definition as the broadest reasonable construction of
`
`“cache coherence controller”: “[a]ny mechanism or apparatus that can be
`
`used to provide communication between multiple processor clusters while
`
`maintaining cache coherence.” Ex. 1001, 7:2–5.
`
`5. “probe filtering unit”
`
`Petitioner and Patent Owner both offer constructions of “probe
`
`filtering unit,” relying primarily on the following discussion in the ’121
`
`patent:
`
`As mentioned above, the filtering of probes within a
`cluster, i.e., local probe filtering, may be implemented in
`systems having multiple clusters as well as systems
`having a single cluster of processors. In the former and
`as described above, the probe filtering functionalities
`described herein may be implemented in a cache
`coherence controller which facilitates communication
`between clusters. In the latter, these functionalities may
`be implemented in a device which will be referred to
`herein as a probe filtering unit (PFU) which may occupy
`a similar location in the cluster as the cache coherence
`controller, and may include some subset of the other
`functionalities of the cache coherence controller. In
`either case, it should be noted that the functionalities
`described may be implemented in a single device, e.g., a
`cache coherence controller or probe filtering unit, or be
`distributed among multiple devices
`including,
`for
`example, the processing nodes themselves. It should be
`understood that the use of the term “probe filtering unit”
`or “PFU” in the following discussion is not intended to
`
`11
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`be limiting or exclusive. Rather, any device or object
`operable to perform the described functionalities, e.g., a
`cache coherency controller as described herein, is within
`the scope of the invention.
`
`Ex. 1001, 26:36–57; see Pet. 17; Prelim. Resp. 11–14.
`
`In view of this disclosure, Petitioner contends that the proper
`
`construction of “probe filtering unit” encompasses a cache coherency
`
`controller. Pet. 17. Petitioner also focuses on the statement that “‘probe
`
`filtering unit’ or ‘PFU’ . . . is not intended to be limiting” and the statement
`
`that “any device or object operable to perform the described functionalities
`
`. . . is within the scope of the invention.” Id. In combination with these
`
`statements, Petitioner notes that certain claims recite certain functions for the
`
`“probe filtering unit.” Id. Based on these observations, Petitioner concludes
`
`that “the term ‘probe filtering unit’ means ‘a device or object operable to
`
`perform the claimed functionalities.’” Id.
`
`Patent Owner argues that “the proper construction of a probe filtering
`
`unit requires, at least, ‘an apparatus operable to filter probes within a single
`
`cluster of processors.’” Prelim. Resp. 11. Patent Owner contends that
`
`Petitioner’s construction improperly reads the term “probe filtering unit” out
`
`of the claims. Id. at 11–12. Additionally, Patent Owner argues that “[t]he
`
`specification defines ‘probe filtering unit’ in the paragraph first describing
`
`‘local probe filtering’—‘the filtering of probes within a cluster.’” Id. at 12.
`
`Patent Owner argues that Petitioner distorts the meaning of the disclosure in
`
`the ’121 patent, particularly the import of the statements that “the use of the
`
`term ‘probe filtering unit’ or ‘PFU’ in the following discussion is not
`
`intended to be limiting or exclusive” and that “any device or object operable
`
`to perform the described functionalities, e.g., a cache coherency controller as
`
`12
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`described herein, is within the scope of the invention.” Id. at 12–14. Patent
`
`Owner contends that, read in context, these statements mean that the term
`
`“probe filtering unit” is not limited to the specific embodiments discussed
`
`thereafter, but that a “probe filtering unit” performs the specific functionality
`
`of filtering probes within a single cluster of processors. Id.
`
`On this record, neither party persuades us to adopt fully its proposed
`
`claim construction. The cited portions of the ’121 patent contain a number
`
`of ambiguities. Neither party fully persuades us to resolve the ambiguities
`
`in favor of its proposed claim construction. We do agree, however, with
`
`Petitioner’s assertion that the broadest reasonable interpretation of “probe
`
`filtering unit” encompasses a cache coherency controller. See Pet. 17; Ex.
`
`1001, 26:52–57 (“It should be understood that the use of the term ‘probe
`
`filtering unit’ or ‘PFU’ in the following discussion is not intended to be
`
`limiting or exclusive. Rather, any device or object operable to perform the
`
`described functionalities, e.g., a cache coherency controller as described
`
`herein, is within the scope of the invention.”). In view of our analysis
`
`below, this conclusion suffices to resolve the issues presented at this stage.
`
`Accordingly, for purposes of this Decision, we do not further construe the
`
`term “probe filtering unit.”
`
`B. Real Parties-in-Interest
`
`Patent Owner argues in a footnote that it is possible that the Petition
`
`does not name all real parties-in-interest to this proceeding. Prelim. Resp. 7,
`
`n.2. Patent Owner notes that the Petition does not list as real parties-in-
`
`interest the petitioners in IPR2015-00159, IPR2015-00161, IPR2015-00163,
`
`and IPR2015-00172. Id. Patent Owner further notes that those Petitions and
`
`the Petition in this case both rely on Koster as prior art, “even though Koster
`
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`was not prior art of record in the prosecution of the ’121 Patent.” Id. Based
`
`on this, Patent Owner surmises that it is possible the Petitioners in the
`
`related cases and this one independently decided to assert Koster, but that it
`
`“is equally plausible or perhaps more plausible that both sets of petitioners
`
`cooperated to some extent in development of the present petitions.” Id.
`
`Patent Owner’s speculative arguments do not persuade us that the Petition
`
`fails to list all real parties-in-interest.
`
`C. The Effective Filing Date of the Challenged Claims
`
`Patent Owner argues that claims 1–3, 8, 15–18, and 25 are entitled to
`
`a priority date of November 4, 2002 and, therefore, Petitioner has not shown
`
`sufficiently that Koster—with a filing date of July 13, 2004—qualifies as
`
`prior art against these claims. Prelim. Resp. 27–32. Patent Owner “does not
`
`currently contend that claims 4–6, 9–12, and 19–24 are entitled [to the
`
`November 4, 2002, priority date].” Id. at 31 n.6.
`
`Petitioner proffers Koster as § 102(e) art. Pet. 7. There is no dispute
`
`that Koster’s filing date of July 13, 2004, is before the filing date of U.S.
`
`Application No. 10/966,161 (“the ’161 application”)—October 15, 2004—
`
`which issued as the ’121 patent. Patent Owner, however, asserts that
`
`claims 1–3, 8, 15–18, and 25 are entitled to the filing date of U.S.
`
`Application No. 10/288,347 (“the ’347 application”)—November 4, 2002—
`
`of which the ’161 application was a continuation-in-part. Prelim. Resp. 27–
`
`32. Petitioner disagrees. Pet. 4–7. Because Koster was filed after the ’347
`
`application, it is prior art only if Petitioner is correct and the challenged
`
`claims of the ’121 patent are not entitled to the filing date of the ’347
`
`application.
`
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`Petitioner argues that claims 1–3, 8, 11, 12, and 14–25 “are entitled to
`
`a priority date no earlier than October 15, 2004,” which is the filing date of
`
`the ’161 application. Pet. 5. In its arguments, Petitioner compares the
`
`disclosure of the ’121 patent to the disclosure of U.S. Patent No. 7,003,633
`
`(“the ’633 patent”), which is the patent that issued from the ’347 application.
`
`See id. at 5–7. Although the relevant issue is the disclosure in the ’347
`
`application, not the disclosure in the ’633 patent, we assume, for purposes of
`
`this Decision, that Petitioner discusses the disclosure in the ’633 patent as an
`
`indication of what disclosure the ’347 application contained when filed.
`
`Petitioner argues that the ’121 patent includes a significant amount of
`
`disclosure not present in the ’633 patent. Id. at 5.
`
`In particular, Petitioner argues that the ’633 patent “does not describe
`
`any of the numerous limitations related to the claimed ‘probe filtering unit’
`
`and its functionality.” Id. at 5–6. Petitioner argues that the term “probe
`
`filtering unit” does not appear anywhere in the ’633 patent, but was
`
`introduced in the ’121 patent. Id. at 6. Petitioner notes that the ’121 patent
`
`discusses a probe filtering unit and its function at column 2, lines 52–56, but
`
`the ’633 patent does not contain any description of a “unit” that performs
`
`probe filtering. Id. Petitioner adds that “the only diagram showing a
`
`multiprocessor architecture using a ‘probe filtering unit’ is Figure 18 of the
`
`’121 Patent, which is likewise absent from the ’633 Patent.” Id.
`
`Petitioner concedes that the ’633 patent discusses “probe filtering
`
`information.” Id. But Petitioner asserts that the definition of “probe
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`filtering information” changed from the ’633 patent to the ’121 patent. Id.
`
`Petitioner argues that the ’633 patent defined “probe filtering information”
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`as “[a]ny criterion that can be used to reduce the number of clusters probed
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`15
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`Case IPR2015-00158
`Patent 7,296,121 B2
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`from a home cluster.” Id. (quoting Ex. 1003 (’633 patent), 14:20–22). On
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`the other hand, Petitioner argues, “in the ’121 Patent, the definition of the
`
`term ‘probe filtering information’ was changed into ‘[a]ny criterion that can
`
`be used to reduce the number of clusters or nodes probed from a home
`
`cluster.” Id. at 6–7 (quoting Ex. 1001 (’121 patent), 14:50–52) (editing
`
`marks added by Petitioner). Petitioner asserts that the ’121 patent added
`
`many changes related to applying probe filtering techniques to nodes. Id. at
`
`7. Based on these arguments, Petitioner asserts that the “definition in the
`
`’633 Patent is admittedly unrelated to the claims of the ’121 Patent.”
`
`Id. at 6.
`
`Patent Owner disputes Petitioner’s arguments, asserting that the ’347
`
`application properly supports all limitations of claims 1–3, 8, 15–18, and 25.
`
`Prelim. Resp. 27–32. Regarding the claimed “probe filtering unit,” Patent
`
`Owner asserts that:
`
`The ’347 application also discloses “the computer system
`further comprising a probe filtering unit which is
`operable to receive probes corresponding to memory
`lines from the processing nodes and to transmit the
`probes only to selected ones of the processing nodes with
`reference to probe filtering information representative of
`states associated with selected ones of the cache
`memories” in Figures 2, 3, 7, 8, 11 and the corresponding
`discussion at Ex. 2006, 10:4-11:19, 21:31-24:16, 26:7-
`27:14. In particular, the ’347 application discloses a
`cache coherence controller 230 that receives probes from
`the processing nodes and then uses probe filtering
`information to transmit probes to a subset of the
`processing nodes. See id. The specification explains that
`“probe filter information is used to limit the number of
`probe requests
`transmitted
`to request and remote
`clusters.” Id. at 34:9-10.
`
`16
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`Patent 7,296,121 B2
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`Id. at 28–29.7 Patent Owner also quotes page 23, lines 20–23 and
`
`page 26, lines 7–13 of the ’347 application. Id. at 29. These
`
`portions of the ’347 application discuss probe filtering information
`
`and its use.
`
`Although the ’347 application does not use the term “probe filtering
`
`unit,” it does disclose a cache coherence controller that uses probe filtering
`
`information to filter probes. See, e.g., Ex. 2006, 10:24–11:19, 23:20–24:16,
`
`26:7–27:13, 34:9–10, Figs. 2, 8, 11. A cache coherence controller
`
`constitutes a “probe filtering unit” under the broadest reasonable
`
`construction of that term as used in the claims of the ’121 patent. See
`
`Section II.A.5, supra. Additionally, the probe filtering information
`
`disclosed in the ’347 application includes information used to reduce the
`
`number of clusters probed, which constitutes “probe filtering information”
`
`under the broadest reasonable construction of that term as used in the claims
`
`of the ’121 patent. See, e.g., Ex. 2006, 23:20–24:16, 26:7–27:14, 34:9–10,
`
`Figs. 8, 11; Section II.A.2, supra. We are persuaded that the ’347
`
`application’s disclosure related to a cache coherence controller and probe
`
`filtering information “reasonably conveys to those skilled in the art that the
`
`inventor had possession” of the claimed “probe filtering unit.” Ariad
`
`Pharms. v. Eli Lilly & Co., 598 F.3d 1336, 1351 (Fed. Cir. 2010) (en banc).
`
`
`7 Exhibit 2006 contains two sets of page numbers. The first set of page
`numbers appears in the upper right corner of each page and starts with “1”
`on the first page of the exhibit. The second set of page numbers appears in
`the lower middle portion of each page and starts with “1” on the second page
`of the exhibit. Patent Owner cites to the first set of page numbers. Prelim.
`Resp. 28 n.5. We also cite to the first set of page numbers.
`
`17
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`Case IPR2015-00158
`Patent 7,296,121 B2
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`Further, we are persuaded that the ’347 application provides proper
`
`support for all the other limitations of independent claims 1, 16, and 25 (see
`
`Prelim. Resp. 27–31 (citing Ex. 2006, 3:3–4, 10:4–11:19, 13:29–31, 15:10–
`
`13, 21:31–24:16, 26:7–27:14, 34:9–10, Figs. 1A, 1B, 2–4, 7, 8, 11)) and the
`
`additional limitations recited by dependent claims 2, 3, 8, 15, 17, and 18 (see
`
`Prelim. Resp. 31–32 (citing Ex. 2006, 10:24–30, 11:12–19, 12:12–14,
`
`15:10–13, 21:31–23:18, 25:13–26:5, Figs. 2, 7, 10)).
`
`Consequently, we are not persuaded that Petitioner has shown
`
`sufficiently that Koster is prior art to claims 1–3, 8, 15–18, and 25.
`
`Therefore, we are not persuaded that Petitioner has demonstrated a
`
`reasonable likelihood of prevailing in its challenge of claims 1–3, 8, 15, 16,
`
`and 25 as anticipated by Koster. For the same reason, we are not persuaded
`
`that Petitioner has demonstrated a reasonable likelihood of prevailing in its
`
`challenge of claims 17 and 18 as obvious over Koster, or in its challenge of
`
`claims 15 and 25 as obvious over Koster, Kuskin, and Park.
`
`D. Asserted Anticipation of Claims 11, 12, and 14 by Koster
`
`1. Overview of Koster
`
`Koster discloses a “snooping-based cache-coherence filter for a point-
`
`to-point connected multiprocessing node.” Ex. 1005, title. In Koster, when
`
`a microprocessor requests data that is not available in its local cache, it sends
`
`a request for that data to a snoop filter. Id. at abs. The snoop filter stores a
`
`copy of the tags of data stored in the local cache memories of each of the
`
`microprocessors. Id. When the snoop filter receives a request for data, it
`
`can determine which microprocessors have copies of the requested data and
`
`relay the data request only to those microprocessors. Id.
`
`Figure 9 of Koster is reproduced below.
`
`18
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`Case IPR2015-00158
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`
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`Figure 9 shows an exemplary flow of messages in multiprocessing node 180
`
`with four microprocessors 182, 184, 186, and 188 and snoop filter 192. Id.
`
`at 6:61–67. Microprocessor 182 requests data by issuing “broadcast A,”
`
`which is routed to snoop filter 192. Id. at 6:67–7:3. Snoop filter 192 has
`
`shadow tag memory 194, which stores copies of the tags of data stored in the
`
`local cache memories of microprocessors 182, 184, 186, and 188. Id. at 7:3–
`
`6, 6:9–17. Upon receipt of broadcast A, snoop filter 192 determines whether
`
`any of the other three microprocessors have a copy of the requested data. Id.
`
`In Figure 9, snoop filter 192 determines that microprocessor 188 has a copy
`
`of the requested data and forwards broadcast A to microprocessor 188. Id. at
`
`7:6–10. Next, microprocessor 188 sends “response B (having a copy of the
`
`requested data)” to snoop filter 192, which, in turn, forwards response B
`
`back to requesting microprocessor 182. Id. at 7:10–14.
`
`Koster notes that “[b]y forwarding response B through the snoop
`
`filter 192, the snoop filter 192 is able to update its shadow tag memory 194.”
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`19
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`Case IPR2015-00158
`Patent 7,296,121 B2
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`Id. at 7:15–16. Koster, however, also discloses embodiments in which “a
`
`response from a microprocessor may be routed directly back to a requesting
`
`microprocessor.” Id. at 7:17–19.
`
`2. Claims 11 and 12
`
`Claim 11 recites “wherein each of the processing nodes is
`
`programmed to complete a memory transaction after receiving a first
`
`number of responses to a first probe, the first number being fewer than the
`
`number of processing nodes.” Claim 12 depends from claim 11. Petitioner
`
`asserts that Koster’s disclosure related to Figure 9 discusses an example
`
`where microprocessor 182 receives only one response to a request for data.
`
`Pet. 22–23. Noting that Figure 9 shows four microprocessors, Petitioner
`
`argues that “[t]hus, the number of responses to the request is fewer than the
`
`number of microprocessors.” Id. at 23.
`
`In response, Patent Owner argues that Petitioner neither addresses the
`
`word “programmed” in claim 11, nor alleges that Koster discloses any type
`
`of programming. Prelim. Resp. 36; see Pet. 22–23. We agree with Patent
`
`Owner that given Petitioner’s failure to address any programming in Koster,
`
`whether explicit or inherent, Petitioner has not made a sufficient showing
`
`that Koster discloses “wherein each of the processing nodes is programmed
`
`to complete a memory transaction after receiving a first number of responses
`
`to a first probe.” For this reason, we are not persuaded that Petitioner has
`
`demonstrated a reasonable likelihood of prevailing in its assertion that
`
`claims 11 and 12 are anticipated by Koster.
`
`3. Claim 14
`
`Claim 14 recites “wherein the pro
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