Sony Corporation et al., Petitioners
`v.
`Memory Integrity, LLC, Patent Owner
`
`Before Jennifer S. Bisk, Neil T. Powell, and Kerry Begley,
`Administrative Patent Judges.
`
`Case No. IPR2015-00158
`Patent No. 7,296,121
`February 8, 2016
`
`Walter E. Hanley, Lead Counsel
`Zaed M. Billah, Backup Counsel
`
`
`v.
`Memory Integrity, LLC, Patent Owner
`
`Before Jennifer S. Bisk, Neil T. Powell, and Kerry Begley,
`Administrative Patent Judges.
`
`Case No. IPR2015-00158
`Patent No. 7,296,121
`February 8, 2016
`
`Walter E. Hanley, Lead Counsel
`Zaed M. Billah, Backup Counsel
`
`
`
`Grounds for Institution
`
`Trial Instituted On Claims 19-24:
`• Claims 19-23 obvious over Koster and Kuskin
`• Claim 24 obvious over Koster
`
`Institution Decision, Paper No. 7 at 35
`
`2
`
`
`
`Claim Construction of “States”
`
`Board: “[T]he term is not limited to cache coherence
`protocol states and is broad enough to include the
`condition of presence—i.e., what is stored in memory.”
`
`Patent Owner: The term “‘state’ means a cache coherence
`protocol state in the field of cache coherency.”
`
`Institution Decision, Paper No. 7 at 10; Patent Owner Response, Paper No. 17 at 5
`
`3
`
`
`
`The Board’s Construction of “States” is Correct
`
`’121 Patent:
`
`Sony-1001 at 14:30-36; Institution Decision, Paper No. 7 at 9-10; Petitioner’s Reply, Paper No. 25 at 2
`
`4
`
`
`
`The Board’s Construction of “States” is Correct
`
`Dr. Sorin: “A person of ordinary skill in the art would
`understand the term ‘states associated with selected ones
`of the cache memories’ to not be limited to cache
`coherence protocol states, and be broad enough to include
`the condition of presence—i.e., what is stored in cache
`memory.”
`
`Sony-1015 at ¶ 17; Petitioner’s Reply, Paper No. 25 at 4
`
`5
`
`
`
`Patent Owner’s Construction of “States” is Improper
`
`’121 Patent:
`
`“A construing court’s reliance on the specification must not go so far as to import
`limitations into the claims from examples or embodiments appearing only in the
`patent’s written description unless the specification makes clear that the patentee
`intends for the claims and the embodiments in the specification to be strictly
`coextensive.” Silicon Graphics, Inc. v. ATI Techs. Inc., 607 F.3d 784, 792 (Fed. Cir.
`2010)
`
`Sony-1001 at 14:30-36; Petitioner’s Reply, Paper No. 25 at 2-3
`
`6
`
`
`
`Koster Overview
`
`Koster:
`
`Sony-1005 at Fig. 7
`
`7
`
`
`
`Koster Overview
`Koster:
`
`Sony-1005 at Fig. 9
`
`8
`
`
`
`Koster Overview
`Koster:
`
`Sony-1005 at 7:1-14
`
`9
`
`
`
`Kuskin Overview
`
`Kuskin:
`
`Sony-1006 at Fig. 2.1
`
`10
`
`
`
`Kuskin Overview
`
`Kuskin:
`
`Sony-1006 at 303
`
`11
`
`
`
`’121 Patent: Claim 16
`
`’121 Patent:
`
`Sony-1001 at claim 16
`
`12
`
`
`
`Koster Discloses the Limitations of Claim 16
`
`Koster:
`
`Sony-1005 at Fig. 7, 5:66-6:2; Petition, Paper No. 1 at 19
`
`13
`
`
`
`’121 Patent: Claim 16
`
`’121 Patent:
`
`Sony-1001 at claim 16
`
`14
`
`
`
`Koster Discloses the Limitations of Claim 16
`
`Koster:
`
`Sony-1005 at Fig. 7; 6:16-17; Petition, Paper No. 1 at 19
`
`15
`
`
`
`’121 Patent: Claim 16
`
`’121 Patent:
`
`Sony-1001 at claim 16
`
`16
`
`
`
`Koster Discloses the Limitations of Claim 16
`
`Koster:
`
`Sony-1005 at Fig. 9
`
`17
`
`
`
`’121 Patent: Claim 16
`
`’121 Patent:
`
`Sony-1001 at claim 16
`
`18
`
`
`
`Koster Discloses “States” Under the Correct Construction
`
`Koster:
`
`Sony-1005 at 7:1-14; Petition, Paper No. 1 at 20
`
`19
`
`
`
`Koster Discloses the Limitations of Claim 16
`
`Koster:
`
`Sony-1005 at Fig. 9
`
`20
`
`
`
`’121 Patent: Claim 16
`
`’121 Patent:
`
`Sony-1001 at claim 16
`
`21
`
`
`
`Koster Discloses “States” Under the Correct Construction
`
`Koster:
`
`Sony-1005 at 7:1-14; Petition, Paper No. 1 at 20
`
`22
`
`
`
`Koster Discloses the Limitations of Claim 16
`
`Koster:
`
`Sony-1005 at Fig. 9
`
`23
`
`
`
`’121 Patent: Claim 16
`
`’121 Patent:
`
`Sony-1001 at claim 16
`
`24
`
`
`
`Koster Discloses the Limitations of Claim 16
`
`Koster:
`
`Sony-1005 at Fig. 9
`
`25
`
`
`
`Koster Discloses “States” Under the Correct Construction
`
`Koster:
`
`Sony-1005 at 6:8-17; 7:1-6; Petition, Paper No. 1 at 20; Petitioner’s Reply, Paper No. 25 at 5-6
`
`26
`
`
`
`Koster’s “States” Constitute “Probe Filtering Information”
`
`Board: “Probe filtering information” is construed to
`mean “any criterion that can be used to reduce the
`number of clusters or nodes probed.”
`
`Koster:
`
`Institution Decision, Paper No. 7 at 8; Sony-1005 at 6:57-60; Petition, Paper No. 1 at 20
`
`27
`
`
`
`Koster Discloses “States” Under the Correct Construction
`
`Dr. Oklobdzija:
`
`Q. But under the Board’s construction of “states,” which is different
`from yours, does Koster disclose states?
`
`***
`A. That is yes. Koster has tags and tags indicate presence, and if Board
`defines “presence” as a state, then under Board definition, they—
`they represent state.
`
`Dr. Sorin: “Under the correct construction of ‘states associated with selected
`ones of the cache memories,’ Koster discloses the limitation of ‘probe filtering
`information representative of states associated with selected ones of the cache
`memories’ in claim 16.”
`
`Petitioner’s Reply, Paper No. 25 at 6; Sony-1016 at 186:17-24; Sony-1015 at ¶ 20
`
`28
`
`
`
`Koster Discloses “States” Even Under Patent Owner’s Incorrect
`Construction
`Koster:
`
`Dr. Sorin: “Even assuming that ‘states’ [is] limited to ‘cache coherence states,’
`Koster discloses ‘states’ because Koster’s ‘shadow tag memory’ may be maintained
`as a ‘set-associative cache’ which may use a MOESI cache coherency protocol. . . .
`Through this disclosure, Koster meets the claim limitation of ‘probe filtering
`information representative of states associated with selected ones of the cache
`memories’ in claim 16 under the Patent Owner’s construction of ‘states.’”
`
`Petitioner’s Reply, Paper No. 25 at 6-7; Sony-1005 at 6:33-38; Sony-1015 at ¶ 21
`
`29
`
`
`
`’121 Patent: Claim 19
`
`’121 Patent:
`
`Sony-1001 at claim 19
`
`30
`
`
`
`Kuskin Discloses The Limitations of Claim 19
`
`Kuskin: “The MAGIC chip forms the heart of the node,
`integrating the memory controller . . . and a
`programmable protocol processor. This integration allows
`for low hardware overhead while supporting [] cache-
`coherence . . . protocols in a scalable and cohesive
`fashion.”
`
`Petition, Paper No. 1 at 26; Sony-1006 at 303; see also Sony-1006 at 304 (discussion cache coherence protocol)
`
`31
`
`
`
`’121 Patent: Claim 20
`
`’121 Patent:
`
`Sony-1001 at claim 20
`
`32
`
`
`
`Kuskin Discloses The Limitations of Claim 20
`
`Kuskin: “We currently have a detailed system-level
`simulator up and running. The simulator is written in
`C++ as a multithreaded memory simulator.”
`
`Petition, Paper No. 1 at 26-27; Sony-1006 at 311
`
`33
`
`
`
`’121 Patent: Claim 21
`
`’121 Patent:
`
`Sony-1001 at claim 21
`
`34
`
`
`
`Kuskin Discloses The Limitations of Claim 21
`
`Kuskin: “On the hardware design front we are busily
`coding the Verilog description of the MAGIC chip.”
`
`Dr. Sorin: “Kuskin teaches building and simulating a
`cache coherency controller using a hardware description
`language for a tangible chip. . . . Use of a Verilog
`description to create a tangible chip necessarily requires
`the creation of a simulatable representation comprising a
`netlist.”
`
`Petition, Paper No. 1 at 27; Sony-1006 at 311; Sony-1013 at ¶ 25
`
`35
`
`
`
`’121 Patent: Claims 22-23
`
`’121 Patent:
`
`Sony-1001 at claims 22-23
`
`36
`
`
`
`Kuskin Discloses The Limitations of Claims 22-23
`
`Kuskin: “On the hardware design front we are busily
`coding the Verilog description of the MAGIC chip.”
`
`Dr. Sorin: “Verilog is a hardware description language
`that was well known prior to 2000. . . . Prior to July 13,
`2004, it would have been obvious to a person of ordinary
`skill in the art to implement the ‘snoop filter’ of Koster
`using a hardware description language (as shown in
`Kuskin) because that was the only commonly used
`method in the industry for designing hardware.”
`
`Petition, Paper No. 1 at 28-29; Sony-1006 at 311; Sony-1013 at ¶¶ 24, 26
`
`37
`
`
`
`’121 Patent: Claim 24
`
`’121 Patent:
`
`Sony-1001 at claim 24
`
`38
`
`
`
`Claim 24 is Obvious Over Koster
`
`Dr. Sorin: “[A]t the time Koster was filed (July 13, 2004), it would have been
`obvious to one of ordinary skill in the art to implement the ‘snoop filter’ disclosed
`in Koster on an integrated circuit . . . . This is so because such an implementation
`was the most common, most performant, and least burdensome of the known
`methods at the time.”
`
`Dr. Sorin: “[A]t the time Koster was filed (July 13, 2004), integrated circuits
`were necessarily created with a set of semiconductor processing masks.
`Accordingly, it thus would have been obvious to one of ordinary skill in the art at
`this time to use a set of semiconductor processing masks representative of at least
`a portion of the ‘snoop filter’ disclosed in Koster to create an integrated circuit
`implementing the ‘snoop filter’ of Koster.”
`
`Petition, Paper No. 1 at 24-25; Sony-1013 at ¶¶ 20-21
`
`39
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