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`111111111111111111111111111
`
`(12) United States Patent
`Chen ct al.
`
`(10) Ilatent No.:
`(45) Date of Patent:
`
`US 6,538,647 Bl
`Ma r. 25, 2003
`
`(54) LOW·I>()Wl':Il. Lc n n ATA DRI VER t"OR
`sn:I'WISELY CHARGING
`
`(75)
`
`[uvcn!up.s: Slm nl,:-Li C he ll, Hsiuo.;lJu (TW);
`C hien-Vu VI, Taoyuan OW)
`
`(73) Assignee: Industria l Technology Rcscurch
`I n ~'1 itu tc OW)
`
`(oO ) Notice:
`
`Subject tQ any disclaimer, the term of this
`palent is cXlCnd.::d or adjusted under 35
`U.S.c. IS4(b) by 211 days.
`
`(21 ) AppJ. No: 09/606,576
`
`(22) hied:
`
`J un. 2~. ZOOO
`
`G09G 5{OO
`(51 )
`In t.CI.~ .
`(52) U.S. C I . ................................. ....... 345/211; 345/98
`(58)
`l<"ield of Searc h ..................... ... 3451204, 208- 215,
`345/690-693, 87,94- 96,98-100
`
`(56)
`
`R£'fet'('nccs Cited
`
`U.S. PATENT DOCUMENTS
`
`5,473,526 i\
`5,748, 165 A
`5,754,156 A
`5,764.225 A
`5,923,3 12 A
`6,27 1)H6 Bl
`
`12/1995 Svensson et al. ............. 363;60
`5/1998 Kubola et:l.l. ................ }45iS'(i
`5/1998 E, ha,! c! a1. ............... ... 345198
`6/1998 Koshobu ..... .............. 345/2 11
`711999 Okada c! al
`................. 345195
`812001 Jeong e! 31.
`..............•.•. 345187
`
`· 2/2002 Yoshida c! al. ......... 315/169.1
`6,35 1,076 Ill
`2IXJ2/0015017 AI · 2/1002 Kwag.
`345/89
`2002/004411 5 AI · 4/2002 Akihilo c! al .............. .. 345/87
`• cited by examiner
`
`I'rimary EXllmincr-Kent Chang
`A. ... ~istanl Exam;ner--.:rom V. Sheng
`(74) Allor-m.'); Agent, or nrm- Blakdy Sokoloff Ta ylor &
`Zafman
`
`(57)
`
`AllSTKACr
`
`A power_saving data driver for stepwisely applying alter.
`na!ing driving voltages with a predetermined number of
`Sleps to a plurality of data lines in a liqu id crystal display is
`disclosed. "l"he data driver is comprised of J clocking means.
`a plurality of reference voltages, and a plurality of analog
`voltage driver. The clock ing means is used for providing
`clock signals for stepwisely charging and discharging. The
`plurality of reference voltages work as steps of said step·
`wisely charging and discharging. "!be reference voltages are
`distributed between the system voltage and the ground. Each
`of the analog voltage driver corresponds to one of Ihe da ta
`lines. A given pixel is Slepwisely driven from a driving
`voltage o f the last pixel as a beginning voltage 10 J driving
`voltage of the given pixel as a targel voltage. 'lbe reference
`voltas"s lx:!w.,:"u tht b,,~innins voltage and Ih" targe! volt·
`age arc turned-on in order according to the clock signals
`generated by the clocking means.
`
`30 Claims, 4 Urawing Sheets
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`
`SHARP EXHIBIT 1013
`Sharp Corp., et al. v. Surpass Tech Innovation LLC
`IPR2015-00021
`
`Page 1 of 12
`
`

`
`u.s. Patent
`
`Mar. 25,2003
`
`Sheet I of 4
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`US 6,538,647 Bl
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`u.s. Patent
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`Mar. 25,2003
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`Sheet 3 of 4
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`US 6,538,647 Bl
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`Page 4 of 12
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`

`
`U.S. Patent
`
`Mar. 25, 2003
`
`Sheet 4 of 4
`
`US 6,538,647 Bl
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`Page 5 of 12
`
`

`
`1
`L.oW- Po w Ell. L CO I)ATA I)RI Vf:R I-OR
`STEP WISELY C IIARG I NG
`
`US 6,538,647 B I
`
`2
`Image quality displayed by the LeDs and the complexity
`of thc driver circuitry !Irc highly related to the methods of
`polarity inversion. There !Ire four major types of inversion of
`alternating polarities relative to the common midpoint
`voltage, i.e. frame inversion, column inversion , row
`inversion, and dot inversion. According to the frame
`inversion. every pixel on the display frame is first driven to
`its positive polarity during a first display cycle, and then
`driveu to its negative polarity during the second display
`10 cycle. The column inversion implies that each pixel in a da ta
`line is driven to the positive polarity, and the adjacent da ta
`line is driven to the negative polarity. According to the row
`inversion, if the pixels in a row are dr ivcn to the positivc
`polarity during the first row drive period, the pixcls in the
`t5 ne xt row will be driven to the negative pobrity during the
`second row drive period. According to the dot inversion, if
`a pixe l is chMged with Ihe positive polarity, the next pixel
`within the same row will be charged to the negative polarity,
`and the adjacent pixel
`in the same column but in the
`20 preceding or following row is also chargcd to the negativc
`pobr;ty. Although the drive circuitry of the dot inversion is
`the most oomplex one, it displays the best imagc propeny.
`For this reason, tbe dot inversion w ill be the main stream of
`the drive drcuitry in the ficld of the liquid crystal displays.
`'Ibe data driver suffers a relatively large capacity from the
`data line. In accordance with conventional teachings, power
`dissilJation of a circuit is directly related to the operating
`lrequency (I), the capacitance (Cl and tlx: 5{juare of the
`voltage (V~) applied to the capacitive elemen!. For this
`reason, the power dissipation of a data d river is significant.
`Especially, in the inversion schemes of the row inversion
`and the dot inversion, the charging/discharging processes for
`alternating polarities results in a very large power dc.sipa -
`tion.
`For this reason, it is very important for LCD industries 10
`develop a low-power LCD da ta driver.
`
`BACKGROUND OF THE INVENH ON
`(1 ) Field of lbe Invention
`lbc present invention relates generally 10 circuitry for
`driving an liquid crystal display (LC D) or Ihe like, and more
`particularly, 10 a circuit anu a method which largely reduce
`the consumed power for driving the data lines of lhe LCD
`display.
`(2) Dc.<;criplion of Ihe Related Art
`"ille breathtaking growth of the information and commu(cid:173)
`nication industries push forward Ihe fast development of
`LCD displays, which arc used in a large variety ofproducls
`including Ilolcbook compUicrs, haml-hcld computers, cellu(cid:173)
`lar phones. and many kinds of personal digital assistants
`(POAs) . The LCD displays are available in both gray-scale
`and oolor panels, and arc typically arranged as a matrix of
`intersecting hundreds or thousands of rows and columns.
`Generally, the intersection of each row amI column forms a
`pixel, wh05C brightness and <--olor arc defined by the elec(cid:173)
`tronic vollage applied thereto.
`lbe LCD monitors u~ in the notebook computers 25
`requires a relatively large number of such pixels to forro a
`pixel array. Referring now to FIG. t , a portion of a pixel
`array of an active matrix liquid crystal display according to
`the prior art is shown. The four pixels connected in the fifth
`row 5, the sixth row 6, the second colu mn 2, and the third 30
`column 3 of the array are shown. Each pixel is comprised of
`a switch 7 and a capacitor 8. ' Jb~ switdl of each pixel in tht
`same row is connected by a scan line. and the switch of each
`pixel ill the same column is connected by a data Hne, The
`lJJclllo<l uf <-UlllIOlliug Ilno illJdgt di~pldycu I)" II,e ",-"etll i~ 35
`to seleet one scan line at a time, and to apply control voltages
`th rough each data line to each column of the selected scan
`line. After all columns of the scle<;:ted scan line are applied
`the control voltages, the next scan line will be selected to
`apply control voltages through each data line to its corre-
`sponding column. After the completion of one display cycle
`during whi<;:h each row in the array has been selected, a new
`([isplay cycle Ix:gins, and the proces. .. is repeated to refresh
`the displayed image.
`'llle data lines arc driven by a data driver, which is 4S
`typically formed upon monolilhic integrated circuits.
`A.:tually, a color LCD monitor requires three times as many
`data driver outpul5 as the monochrome LCD monitor. The
`color LC D monitor requires three data driver outputs per
`pixel , one of each o( the threc primary colors (red, grecn, 50
`blue) to Ix: displayed. l llus, a typical VGA color liquid
`cry.~t~l di);play with 4M roW);xfi4() column); include); 1920
`data lines which mU5t be drivcn by a like number of column
`data driver outputs
`l be liquid crysta l displays arc capable of displaying 55
`images because the o ptical transmission chara<;:terlstics of
`liquid crystal material change in accordance with the mag(cid:173)
`ni tude of the applied e lectronic voltage_ However, the appli_
`cation of a steady DC voltage to a liquid crystal material for
`a long; period will permanently change and degrade its 60
`physical propertie .... For this reason, it is common to drive
`tho;: liquid crystal displays using drive techniques whid
`charge cach liquid crystal with voltagcs of alternating pclari(cid:173)
`tics relative to a common midpoint voltage value. 'Ibe
`voltages greater than and less than the .:ommon midpoint 65
`voltage represent the positive polarity and the negative
`polarity. respectively.
`
`01.0
`
`SUMMA RY 0 1; n l E INVENTI ON
`
`A<;:cordingly, it is a primary object of the present invention
`to provide a low-power LCD data driver.
`It i~ another object of the prescnt invention to provide a
`method of driving LCD's data lines with low power dissi(cid:173)
`pation.
`A power-saving data drive r for stepwisely applying alter·
`nating driving voltages with a predetermined numher of
`steps to a plurality of data lines in a liquid crystal display is
`disclosed. l be data driver is comprised of J clocking means,
`a plurality of reference voltages, and a pluralily of analog
`voltage driver. 'Ibe clock ing means is used for providing
`dock signals for stepwisely charging and discharging. l be
`plurality of reference voltages work as steps.of the step·
`wisely charging and discharging. The reference voltages arc
`distributed between the system voltage and the ground. Each
`of the analog voltage driver corresponds to one of the data
`lines. A given pixel is stepwisely driven from the driving
`voltage orlhe [aSI pixel as a bcginnin!:; voltage 10 Ih~ drivin!:;
`voltage of the giv~n pixel as a target voltage. 'Ibe reference
`voltages belween the beginning voltage and the targe t volt(cid:173)
`age are turned-on in order according to the clock signals
`generated by the clocking means.
`In one embodiment of the present invention, the prede(cid:173)
`termined number of steps is four and thus there arc three
`reference voltages, i.e. the fust reference voltage, the second
`reference volt!lge, !Ind the third reference voltage. l be
`second reference voltage is the common midpoint voltage of
`the alternating driving voltages. 'Ibe first reference voltage
`
`Page 6 of 12
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`

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`US 6,538,647 B I
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`3
`is 75% of the system voltage and the third reference voltage
`is 25% of the system voltage.
`[0 another embodiment of the present invention. the first
`reference voltage is a voltage corresponding 10 the positive
`polarity wilh 50% of optical transmission fale, and the third
`reference voltage is a voltage corresponding 10 the negative
`polarity wilh 50% of opticallransmission UIC.
`[n another embodiment of the present invention, Ihe first
`reference voltage i~ the positive voltage obtained by
`charging/discharging a capacitor connectcU [0 the analog 10
`voltage driver for a plurality of limes, and the third reference
`vollage is a negative voltage obtained by charging!
`discharging a capacitor connected 10 the analog voltage
`driver for a plurality of limes.
`
`BRIER DESCRIPTION OF THE DRAWINGS
`
`·Ibe accompanying drawing~ forming a material part of
`thb ~r iption, in wh ich
`FIG. 1 schematica lly illustrates a portion of a pixel array 20
`of an active matrix liquid crystal display according to the
`prior art.
`FIG. 2 .schematically illustrate the block diagram of the
`stepwise eharge/dise barge driver according to the prcsc01
`inventton.
`FIG. 3 schemalically illuS!ral~ the wavc diagrams of !l ,
`12, t3, t4, \but, and Vdac according to the prescnt invention.
`FIG. 4 schematically illustrates the block diagram of the
`an.alog voltage driver acoording to Ibe prtStnt iDvention.
`FIG. 5 schematicaJly illustrates the reference voltages
`according to an embodime01 of tbe prescnt invention.
`
`"
`
`4
`tion will be the conventional energy dissipalion divided by
`four, and thus largely reduccd. About Ihis theory, please refer
`to U.S. Pal. No. 5,473526 for more detai led.
`Referring now to FIG. 2, the block diagram ofthc driver
`circuitry for stepwisely charging and discharging according
`to the present invention is disclosed. ·llIe driver circuitry is
`compriscd of a clocking means 20, a plurality of reference
`voltages, and a plurality of analog voltage drivers 30. Each
`analog voltage driver corresponds to one of the plurality of
`data lines, wherein the first analog voltage drivers 30 1, the
`second analog voltage drivers 302, and the mth analog
`voltage driver 30 m are shown in FIG. 2.
`The clocking means 20 is uscd for generating clock
`signals for stepwisely c barging and discbarging. "J"be input
`t5 tenninal of the clocking nleans 20 is coupled to system clock
`ClK and RST, and its outpUlterminal provides clock signals
`tl, t2, t3.
`, tn for stepwisely charging and discharging to
`al1 of the analog voltage drivers induding the first analog
`voltage drivers 301, the second analog voltage drivers 302,
`and tht.: mth analog voltagt.: driver 30 tn, where!!) !) implies
`the predetermined !lumber of steps. For example, if the
`predetermined number of steps is four, the clocking means
`20 will provide four clock signals of II, t2, t3, and t4, as
`shown in FIG. 3.
`·Ibe number of the plurality of refe rence voltages is the
`predetermined number of steps minus one, and the plurality
`of refere nce voltages are distributed between the ~ystem
`voltage (Vdd) and the ground.
`The inpul tenninal of the lirsl analog voltage driver 3Ul
`is ooupled to the clocking means, the plurality of reference
`voltages VI,
`, Vn- I, the driving voltage Vdac1, the
`polarity 1', and the brightness information MSB (most sig.
`nificant hit). The OUlput tenninal of the fiN<t analog voltage
`35 driver JOI I>; coupled to the first da ta line for driving il. In
`addition, the other analog VOltage drivers such 35 the second
`analog voltage driver 302 !O the 10th analog vOllage driver
`30m have the same conncction rclationslJ ip. '!be OUiput
`tenninal of each analog VOltage is coupled to its corr~pond-
`-'0 Ing data line.
`Referring now to. FI G. 4, the bloo:k diagram of the analog
`voltage driver according to the present invention is dis(cid:173)
`closed. The inputlerminal of the analog ,·oltOlge driver JO is
`coupled to the driving voltage Vdac1 and the plurality of
`reference voltages VI, ... , Vn- l from Ihe switch control
`logic 25. Its outplll termi nal is coupled 10 its corresponding
`data line, i.e. the load 42. ·llIe analog voltage driver JO
`includes the first switch element and the other n-I switch
`clemenL<;, which can he MOS transistors. The n switch
`eiemenl:s in the analog voltage driver 30 are turned on or 01I
`in sequence depending on the polarity I' and the brightness
`information MSU. As a result, the stepwise charge and
`discharge can be well ach ieved, as shown in FIG . 3.
`·lbe driVing method according to the prescnt invention is
`described as follows. As mentioned above, it is common to
`drive the liquid 'rystal displays using drive techniques
`wbi,b (harge ea(h liquid (ry~tal with voJtage~ of alternation
`polarities relative to the (ommon midpoint voltage value,
`whieb is 50% of the system voltage Vdd. The positive
`60 polarity voltages imply the driving voltages between the
`system voltage Vdd and the common midpoint voltage. and
`the negative polarity voltages imply the driving ,'oltages
`between the common midpoint voltage and the ground.
`According to the normally black LCD panels, the liquid
`65 crystal layer tr3rrsmilS 00 light if no driving voltage is
`applied to. "llIe larger the driving voltage, the higher the
`optical transmission rate is. ·Ibis implies that a given pixel
`
`DESCRJIYI10N OF '11m PREFERRED
`EMBODIM ENTS
`
`·llIe present invemioo is rclated to a power.saving data
`driver for stepwisely applying alternating driving voltages
`with a predetermined number of steps to a plurality of data
`linc.'; in a liquid crystal display.
`As mentioned above, the liquid crystal display should be
`driven by alternation polarities relative to the 'OIlUIlOIl
`midpoint voltage value. For tbis reason, Ibe data line driver
`should keep c harging and dischargitlg the data lines
`continuously, especially in the case of row inversion and dot 4S
`inversion. According to the prescnt invemion, a plurality of
`switches ill the analog voltage driver are oootrol1cd by the
`polarities (I') and the MSl3s of the digital data of the driving
`VOltage so as to largely reduce the power dissipation.
`·Ibe driving voltage Vdae i~ derived from the traditional 50
`digital-analog-convener for driving the data lines. As men(cid:173)
`tioned in the background of the invention, the driving
`voltage Vda, is di rectly coupled to the data lines according
`to the prior art. ·llIal will result in largt.: powcr dissipation.
`In order to reduce the power dissipation. the method of 55
`stepwise charge and discharge is applied in the present
`inventIon.
`1 /2(CV~) for each charge!
`is
`The energy dissipated
`discharge process applied to a capacitive clement, where C
`is the capacitance of the capacitive clement and V is the
`maximum voltage in the charge or discharge process. In case
`the ehuge or discharge process is divided into n steps and
`the voltage variation of each stcp is VIti, the energy dissi·
`pation for each step is (1 I2XCV~)!n1 . As a result. the energy
`di<;sip~te of n steps is (U2)(CVz)/n, which is the conven·
`tional energy dissipation divided by n. For example, if the
`predetermined number of slep~ is four, Ihe energy dissipa-
`
`Page 7 of 12
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`US 6,538,647 B I
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`"
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`5
`is brighter when the driving voltage is closer 10 the system
`vollage Vdd or the ground. On the Olher hand, a pixel is
`darker wheo the driving voltage is ncar the common mid(cid:173)
`poilU voltage.
`According \0 the firsl embodiment of the present
`invention, the predetermined number ofSleps is fOUf, which
`implies that there arc rour steps for the analog voltage drivcr
`30 10 slcpwisdy charge and di;s(;hargc. Referring now 10
`FIG. 5, the reference voltages according to the lirsl embodi(cid:173)
`ment of the present ioveotion is disclosed . The midpoint
`voltage is b<.;1~cn the system voltage Vdd aod the ground,
`and called Vdd 50%. 1he olher two reference voltages, I.e.
`7:i% of the system vollagc (called Vdd 7.'>%) and 25% of the
`system voltage (called Vdd 25%), arc also shown in FIG. 5.
`Generally, the brightness of two adjaccllt pixcls arc close.
`For this reason, we ~uPI'0oo that the present pixel and the last
`pixel have mearly the same brightness and thus have the
`samc MS I3 and op ~ite polarities. The four switch clements
`for lurning-on Vdd 25%, Vdd 50%, Vud 75%, and the
`driving voltage arc turned on depending on the combinations
`of polarities I' and the brightness MSll of the current pixel
`as follows.
`\. P~itive IlOlarity (l'_l)_hright (MSB- l): turning on
`Vdd 25%, Vdd 50"h , Vdd 75%, and Ydac in order.
`2. Ncgative Polarity (l'-Q)-bright (MSO- l): turning on
`Vdd 75%, Vdd 5(f"A>, Vdd 25%, and Ydae in order.
`3. Positive polarity (P_ I )_dark (MSll_ O): turning on Vdu
`50%, and Vdac in order.
`4. Negative Polarity (P-o)-dark (MSB-O): turning on Ydd 30
`50%, and Vdae in order.
`In the liest case, a bright pixel will be driven by lhe
`positive polarity, so the driving voltage output from the
`digital-analog-converter (Vdac) is located between Vdd and
`Vdd 75%. In this embodiment, the M~ B of lhe last pixel is 35
`supposed to be the same with that of the present pixel but
`with opposite polarity, so tht driving voltage of the last pixel
`is located between the ground and Vdd 25%. For this reason,
`the pre.<;ent pixel is stepwisc ly dri ven from the driving
`voltage of the last pixel to Vdd 25%, Vdd 50%, Vdd 75%, olO
`and Vdac in order. As mentioned above, the power dissipa(cid:173)
`tion of the data line driver can be largely reduced by means
`of the stepwise charge.
`In the second case, a bright pixel will be driven by the
`negative polarity. so the driving voltage output from the 4S
`digital-analog-converter (Vdac) is located between the
`ground and Vdd 25%. In this embodiment, the MS 13 of the
`last pixel is supposed to be the ~me with tha t of the present
`pixel but with opposite polarity, so the driving voltage of the
`last pixd is Io.x:ah;d bt:hn;t:1i Vdd and Vtld 75%. f ur this 50
`reason, the present p ixel is stepwi~ly driven from the
`driving voltage of the last pixel to Vdd 75%, Vdd 50%, Vdu
`25%. and Vdae in order. As mentioned above, tile power
`dissipation of thc da ta line driver can be largely reduced by
`means of the stepwise discharge.
`In the third case, a d ark pixel will be driven by the positive
`polarity, so the driving vQltage output from the digital(cid:173)
`analog-converter (Vd ac) is located between Vdt! 5CYJt and
`Vdd 75%. In this embodiment, the MSB of lhe last pixel is
`supposed to be the same with tha t of the pre~nt pixel but 60
`with opposite polarity,.<;() the driving voltage of the last pixel
`is located octwecn Vdd 50% and Vdd 25%. For this reason,
`the present pixel is stepwiscly driven from the driving
`voltage of the last pixel to Vdd 50% and Vdac in order. A~
`mcntioncd abovc, the powcr dissipation of the data line 65
`drivcr can be largely reduccO by means of the stepwise
`charge.
`
`6
`In the fourth case, a dark pixel wil! be driven by the
`negative polarity, so the driving voltage output from the
`digital-analog-cOtlVerter (Vdac) is located betwecn Vdd
`50'1:> and Vdd 25%. In this embodiment, the MSll of the last
`pixel issupposed to be the same with tha t of the present pixel
`but with opposite polarilY, so the driving voltagc of thc la$!
`pixel is located between Vdd 5(f"A> and Vdd 75%. For this
`reason, the present pixel is stcpwisely driven from the
`drivi ng voltage of the last pixel to Vdd 50% and Vdae in
`10 order. As mentioned above, the power dissipation of the da ta
`line driver can be largely reduced by means of the stepwise
`discharge.
`According to the lirst embodiment of the prescnt
`invention, the MSO of 1he last pixel is suppose(1 to be the
`t5 same with that of the present pixel. llowever, in the actual
`practice, the MSO of the last pixel can be different to tha t of
`the present pixel. In order to take this is.~lIc into coosider.
`ation for further reducing tbe power dissipa tion, the circuit
`of the analog VOltage driver is modified according to the
`20 second embodiment. so that Vdd 25%, Vdd 50%, Vdd 75%,
`and Vdac can be turned on depending on the polarity, MSI3
`of the prc.<;ent pixel, and MSn of the last pixel (called Mp).
`·Ibere are total eight cases as follows:
`t. p .. t, MSI3 .. Mp .. t: turning on Vdd 25%, Vdd 50%, Vdd
`75%, and Vdae in order.
`2. P-o, MSI3 _Mp_t: turning on Vdd 75%, Vdd 50%, Vdd
`25%, and Vdae in order.
`3. 1'_1, MS13_ Mp-o: turning on Vdd 50%" and Vdac in
`order.
`4. P-o, MSB_ Mp-o: turning on Vdd 50'%, and Vdac in
`order.
`5.1' .. 1, MSB_ I, M p_O: turning on Vdd 50"Al, Vdd 75%,
`and Vdae in order
`6.1'-0, MSB-t, MI'-O: IU I Ui llg Ull V,h.l 50"4>, Vdd 25%,
`and Vdae in order.
`7. pat, MSI3-0, Mp_I: turning on Vdd 25%, Vdd 50%,
`and Vdac in order.
`R. p..o, MSI3 _0, Mp_ l· turning on VIi(1 75%, Vlid 50%,
`and Vdae in order.
`In the fi rst case, a bright pixel will be driven by the
`positive polarity, SO the driving VOltage output from the
`digital-analog-cotlVerter ( Vdac) is located between Vdd and
`Vdd 75%. In this case, the MSB of the last pixel is the same
`with the present pixel but with opposite polarity, so the
`drivi ng voltage of the last pixel is located between the
`ground aod Vdd 25%. For this reason, the present pixel is
`stepwiscly driven from the driving voltage of the last pixel
`to Vdd 25%, Vdd 50%, Vdd 75%, and Vdac in order. As
`tlIt:lltiullt:u above, tilt: power di~patiull uf tht: data lillt:
`driver can be largely reduced hy means of the stepwisc
`chargc.
`III the second case, a brig,lIt pixel will be drivell by the;
`negative polarity, so the driving voltage output from the
`55 digital-allalog+converter (Vdac) is located between the
`ground and Vdd 25%. In this case, the MSB of the last pixel
`is the same with the prescnt pixel but with opposite polarity,
`so the driving voltage of tbe last pixel is located between
`Vdd and Vdd 75%. For this reason, the present pixel is
`stepwiscly driven from the driving voltage of the last pixel
`tn Vdd 75%, Vdd 50%, Vdd 25%, and Vdac ill order. As
`mentioned above, the power dissipation of the data line
`driver can be largely reduced by means of the stepwise
`discharge.
`In the third case, a dark pixel will be driven by the positive
`polarity, so the driving voltage output from the digital(cid:173)
`analog-converter (Ydae) is located between Ydd 50% and
`
`Page 8 of 12
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`US 6,538,647 B I
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`7
`Vdd 75%. In this case, the MSB of the laS! pixel is the same
`Wilh the present pixel but wilh opposite polarity, so Ihe
`driving vollage of the last pixel i~ located belween Vdd 50%
`and Vdd 25%. For lhis reason, the present pixel is stcpwiscly
`driven from the driving voltage of the lasl pixel to Vdd 50%
`and Vdac in order. As mC[J!ioned above, the power dissipa(cid:173)
`tion of the data line driver can be lafi,ely reduccd by means
`of the stepwise charge.
`In the fourth case, a d~rk pixel will be driven by the
`negative polarity, so the driving vollage output from lhe 10
`digital-ana[og-converter (Ydac) is located between Vdd
`50% and Vdd 25%. In this case, lhe MSB of lhe laSI pixel
`is the same with the present pixel bUi wilh opposite polarity,
`so the driving vohagc of the last pixel is located between
`Vdd 50% and VdI 75%. FOlr this rcason, the present pixel is t5
`stepwisely driven frOlm the driving vOlllage of the la~t pixel
`to Vdd 50% and Vd~c in order. As mentioned ahove, the
`power dissipation of the data line driver can be largely
`reduced by means Olf the stepwise discha'Se.
`In the fifth cao;c, a hright pixel will be driven by Ihe
`positive pnlarity, so the driving vnllagc output frnm the
`digital.analog--converter (Vdac) is located between Vdd and
`Vdd 75%. In this case, the last pixel is a dark ene with
`nppnsite pnlarity, so the driving vnltage of the last pixel is
`locatctl between the Vdd 50% and Vdd 25%. Fer Ihi~ reason, 25
`the present pixel is stepwisely driven from the driving
`vohage nflhe last pixcl tn Vdd 50%, Vdd 75%, and Vdac in
`urver. As mentioned awv<:, the power lli'>Sipatiull uf th<: data
`line driver can be largely reducctl by means ef the ~tepwise
`charge.
`In the sixth case, a bright pixel will be driven by Ihe
`negative polarity, so the driving veltage output from the
`digital.analog.converter (Vdac) is located between the
`ground and Vdd 25%. In this case, tlx: last pixel is a dark one
`with opposite potanty, 50 the driving veltage ef the last pixet 35
`is located between the Vdd 50% and Vdd 75%. For this
`reason, the present p ixel is stepwiscly driven from Ihe
`driving voltage of the last pixel te Vdd 50%, Vdd 25%, and
`Vdac in order. A~ mentioned ahove, the ]lo wer dis.~ipatinn of
`the data line driver can be largely reduced by means of the
`stepwise discharge.
`[n the seventh case, a dark pixel will be driven by the
`positive polarity, so the driving voltage output from Ihe
`digital-ana[og--cOlnverter (Vdac) is located between Vdd
`50% and Vdd 75%. 10 tbis case. thc last pixel is a bright ooc
`with opposite polarity, so the driving voltage of the last pixel
`is locatcd between the grouod aod Vdd 25 %. For Ihis reasoo,
`the present pixel is stepwisely driven from the driving
`VOltage of the last pixclto Vdd 25%, Vdd 50%, and Vdac in
`urver. As mentioned awv~, the power llissipatiull uf thl: data
`line driver can be largely reducctl by means of the ~tepwise
`Charge.
`[n the eighth case, a dark pixel will be driven by Ihe
`ocgative polarity, so the driviog voltage output from Ihe
`digital.ana[og-converter (Vdac) is located between Vdd
`50% and Vdd 25%. In this case, the last pixel is a bright one
`with opposite polarity,.'jQ the driving voltage of the last pixel
`is located belwceo Veld and Vdd 75%. Fnr this reason, Ihe
`present pixel is stepwisely driven frnm the driving voltage of
`the last pixel to Vdd 75%, Vdd 50",0, and Vdac in order. A~
`menti()nctl aoove, the power dissipation of the data line
`driver can be largely reduced by means nf the stepwise
`discharge.
`[n the second embodiment, it is taken inte consideration
`that the gray-scale of the present pixc\ is different to that of
`the last pixel. Accordjog to the charge/discharge method of
`the preseot iovention. the MSB difference of the adjaceo!
`
`8
`two pixel will 00 more result in extra charge or discharge
`proce!;S. As a result, the power dissipation according In this
`embodiment can be further reduced.
`Accordiog to the fnregoiog two embodimelli. it is
`assumed that the liquid crystal has a lioear photo-e\cctonic
`re[atiore;hip, so as to set the reference vOlltages as Vdd 75%,
`Vdd 50"k , and Vdd 25% .
`Actually, the photo-electronic relationship is not neces(cid:173)
`sary to be linear. It I accordance with another embodiment of
`the present invention, the non-linear photo.electronic rela·
`tionship is taken into consideration. Besides the common
`midpoiot voltage, two more reference voltages arc applied.
`Ooe of them is a voltage corresponding to the positive
`po[arily with 50% of optical transmissino rate, and the Olher
`one is a VOltage correspondiog tOl the !legative polarity with
`50% of optical transmissi()n rate.
`In accorc[ance with another cmhodimcnt of the present
`inventinn, besides the common midpoint voltage, twn mnre
`reference voltages are appl ied. One Olf them is a positive
`20 vol1age obtained by charging/discharging a capacitor con(cid:173)
`nected tn the analog vohage driver for a p lurality of times,
`aod the other one is a negative VOltage ootainc<l by charging!
`discharging a capaciter connected tOl the analeg veltage
`driver fnr a plurality nf times.
`Of CQun;e, the predetermined number of steps is net
`neces.-;ary to be four. According to anOlther embodiment ef
`the preseot ioveotioo, the pre(]etermioed oumber of steps is
`twu. 111e eummun midpoiot vultag<: uf th<: ahnoatiog driv.
`ing voltages is defined as the reference veltage. wherein the
`30 tirst regioo is de!ioed by vohagcs between the system
`voltage aud the reference voltage and driven by the positive
`polarity, and the second region is ddined by voltages
`between the reference voh age and the ground, and driven by
`the oegative polarity.
`According to another embodimeot of the present
`inveminn, the predetermined number nf steps is eight, and
`thus the number of the plurality of reference voltages is
`seven, including the firsl reference voltage, the second
`reference vo1t~ge, Ihe Ihird reference voltage, Ihe fouMh
`4-0 reference voltage, the fifth refe rence voltage, the sixth
`refereoce, and the seventh refereoce vOlltage. l be fourth
`refereoce voltage is a COmmon midpoint VOltage of the
`alternating driving voltages. '(be fust region is dcfillCd by
`vOltages between the system VOltage aod the first reference
`4S voltage. and driven by the po