United States Patent 1191
`Cleeves
`
`[54] DISPOSABLE POST PROCESSING FOR
`SEMICONDUCTOR DEVICE FABRICATION
`
`[75] Inventor: James M. Cleeves, Redwood City,
`Calif.
`
`['73] Assignee: Cypress Semiconductor Corp., San
`Jose, Calif.
`
`[21] Appl. No.: 515,675
`[22] Filed:
`Aug. 17, 1995
`
`Related US. Application Data
`
`[62] Division of Ser. No. 179,615, Jan. 10, 1994, abandoned.
`
`[51] Int. C16 ................................................. .. H01L 21/283
`
`[52] US. Cl. . . . . . .
`. . . .. 437/195; 437/228; 430/313
`[58] Field of Search ................................... .. 437/180, 195,
`437/203, 228 I, 228 CL, 228 ST, 228 W,
`229; 156/6361; 430/313, 314, 317
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUIVIENTS
`
`3/1991
`4,997,790
`5,063,169 11/1991
`5,068,207 11/1991
`5,158,910 10/1992
`5,187,121
`2/1993
`> 5,219,787
`6/1993
`5,270,236 12/1993
`5,275,973
`1/1994
`5,283,208 2/1994
`5,319,247
`6/1994
`$352,630 10/1994
`5,382,545
`1/1995
`5,461,004 10/1995 Kim ..................................... .1 437/195
`
`OTHER PUBLICATIONS
`
`S. Wolf, “Silicon Processing for the VLSI Era” vol. II, pp.
`161,238,429,432, Jun. 1990.
`Fukase, et al, “A Margin-Free Contact Process Using An
`A1203 Etch-Stop layer For Higher Density Devices,”
`IEDM, Apr. 1992, pp. 837-840.
`
`USOO5710061A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,710,061
`Jan. 20, 1998
`
`Ueno, et al, “A Quarter-Micron Planarized Interconnection
`Technology With Self-Aligned Plug,” IEDM, Apr. 1992, pp.
`305-308.
`Kusters, et al, “A High Density 4Mbit dRAM Process Using
`a Fully Overlapping Bi?ine Contact (FoBIC) Trench Cell,”
`1987 Symposium on VLSI Technology Digest of Technical
`Papers, May 18-21, 1987/Karuizawa, pp. 93-94.
`Kakumu, et a1, “PASPAC (Planarized AllSilicide/Poly Si
`With Self Aligned Contact) With Low Contact Resistance
`and High Reliability in CMOS LSIs,” 1987 Symposium on
`VLSI Technology Digest of Technical Papers, May 18-21,
`1987/Karuizawa, pp. 77-78.
`Kenny, et al, “A Buried-Plate Trench Cell for a 64-Mb
`DRAM,” 1992 Symposium on VLSI Technology Digest of
`Technical Papers, Apr. 1992, pp. 14-15.
`Subbanna, et al, “A Novel Border-less Contact/Interconnect
`Technology Using Aluminum Oxide Etch Stop for High
`Performance SRAM and Logic,” Dec. 1993, pp. 441-444.
`Kusters, et al, “A Stacked Capacitor Cell with A Fully
`Self-Aligned Contact Process for High-Density Dynamic
`Random Access Memories,” Journal of the Electrochemical
`Society, vol. 139, No. 8, Aug. 1992, pp. 2318-2321.
`“Method for Forming Via Hole Formation,” IBM Technical
`Disclosure Bulletin, vol. 34, No. 10A, Mar. 1992, pp.
`219-220.
`
`(List continued on next page.)
`
`Primary Examiner-Charles L. Bowers, Jr.
`Assistant Examiner-Leon Radomsky
`Attorney, Agent or Firm—Blakely, Sokololf, Taylor &
`Zafman LLP
`
`[57]
`
`ABSTRACT
`
`A disposable post process allows openings to be created in
`a layer formed over a semiconductor wafer, for example to
`create self-aligned contacts. A layer of material is formed
`over a semiconductor wafer and subsequently patterned into
`posts which de?ne the location and shape of openings to be
`formed in a subsequently formed planar layer. After the
`planar layer is formed to surround the posts, the posts are
`removed to create openings in the planar layer. These
`openings may then be used to form suitable contacts.
`
`20 Claims, 8 Drawing Sheets
`
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`W
`
`SAMSUNG-1004.001
`
`

`

`5,710,061
`Page 2
`
`UI‘HER PUBLICATIONS
`“Self-Aligned, Borderless Polysilicon Contacts Using Poly
`silicon Pillars,” DBM Technical Disclosure Bulletin, vol. 35,
`No. 2, Jul. 1992, pp. 480-483.
`Wolf, et a1, “Silicon Processing for the VLSI Era, vol. 1:
`
`Process Technology,” Lithography 1: Optical Resist Mate
`rials and process Technology, 1986, pp. 453-454.
`
`S. Wolf, “Silicon Processing for the VLSI Era, vol. 2:
`Process Integration,” Multilevel-Interconnect Tehnology for
`VISI & U18], 1992, pp. 222-237.
`
`SAMSUNG-1004.002
`
`

`

`5,710,061
`fIOO
`
`r110
`
`130
`
`FORM PHOTOSENSITIVE
`MATERIAL OVER WAFER
`I
`PATTERN PHOTOSENSITIVE
`MATERIAL INTO POSTS
`I
`FORM PLANAR LAYER ‘K120
`AROUND POSTS
`I
`REMOVE POSTS
`TO CREATE OPENINGS
`I
`FORM MATERIAL
`INTO OPENINGS
`
`r140
`
`US. Patent
`
`Jan. 20, 1998
`
`Sheet 1 of 8
`
`FIG.
`
`1
`
`SAMSUNG-1004.003
`
`

`

`US. Patent
`
`Jan. 20, 1998
`
`Sheet 2 of 8
`
`5,710,061
`
`220 I
`
`21.0
`
`\
`
`201/
`
`i 211}
`W
`FIG. 2A
`
`221
`
`l 211}
`
`W
`FIG.
`2B
`
`SAMSUNG-1004.004
`
`

`

`U.S. Patent
`
`Jan. 20, 1998
`
`Sheet 3 of 8
`
`5,710,061
`
`/ 240
`
`/.___
`2111
`211) gm \ gm
`
`W
`FIG. 2 I)
`
`FIG. 2E
`
`SAMSUNG-1004.005
`
`

`

`US. Patent
`
`Jan. 20, 1998
`
`Sheet 4 0f 8
`
`5,710,061
`
`FOFIM ETCH-STOP
`LAYER
`
`30°
`
`DEPOSIT POST-MATERIAL f 310
`mm wAFER
`
`PATTERN POST-MATERIAL f 320
`INTO POSTS
`
`FORM PLANAR LAYER
`AROuNO POSTS
`
`REMOvE POSTS
`TO OREATE OPENINGS
`
`33°
`
`34°
`
`REMOVE ETCH-STOP LAYER
`FROM OPENINGS
`
`33°
`
`FORM MATERIAI. f 360
`INTO OPENINGS
`
`_ FIG.
`
`3
`
`SAMSUNG-1004.006
`
`

`

`US. Patent
`
`Jan. 20, 1998
`
`} Sheet 50f8
`
`5,710,061
`
`426
`
`420 f
`
`492
`
`405 l 411}
`
`LAJ
`
`W
`FIG. 4A
`
`427
`
`421
`
`FIG. 4C
`
`SAMSUNG-1004.007
`
`

`

`US. Patent
`
`Jan. 20, 1998
`
`Sheet 6 of 3
`
`5,710,061
`
`405‘;
`
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`
`{450
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`m
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`405
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`
`FIG. 4E
`
`SAMSUNG-1004.008
`
`

`

`US. Patent
`
`Jan. 20, 1998
`
`Sheet 7 of 8
`
`5,710,061
`
`m\\\\\\\\\\\\\V 56°
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`521b
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`W
`
`FIG. 5 C
`
`SAMSUNG-1004.009
`
`SAMSUNG-1004.009
`
`

`

`U.S. Patent
`
`Jan. 20, 1998
`
`Sheet 8 of 8
`
`5,710,061
`
`‘L. W
`
`FIG. 5])
`
`5590
`
`\
`
`J“ W
`
`' FIG. 5E
`
`FIG. 6
`
`SAMSUNG-1004.010
`
`

`

`5,710,061
`
`1
`DISPOSABLE POST PROCESSING FOR
`SEMICONDUCTOR DEVICE FABRICATION
`
`This is a divisional of application Ser. No. 08/179,615,
`?led Jan. 10, 1994, abandoned.
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates generally to the ?eld of
`semiconductor device fabrication and more particularly to
`the ?eld of forming openings in a layer for semiconductor
`device fabrication.
`2. Description of the Related Art
`Typically in semiconductor device fabrication processes,
`contact openings are created in dielectric layers formed over
`a semiconductor substrate and subsequently ?lled with a
`metal to provide for electrical connection to various diffu
`sion regions in the substrate. In typical contact processes,
`these openings are etched in the dielectric layer. However,
`since the contacts need to be insulated from various semi
`conductor device structures and layers in a semiconductor
`wafer, contact openings must be etched taking into account
`where these device structures and layers have been formed
`as the etch may inadvertently expose these structures or
`layers. Ifthe opening were to be ?lled with a metal, then, an
`electrical short will be created as the exposed structures or
`layers will be contacted by the ?lled metal.
`To avoid creating electrical shorts, contact openings are
`typically spaced apart from underlying structures or layers.
`Since any misalignment in the etching mask may also
`expose underlying structures or layers during the etch and
`hence cause electrical shorting, the spacing between the
`desired openings and the underlying structures or layers
`must also compensate for such misalignment This spacing
`requirement, however, limits the density of the device being
`fabricated as the contacts must be safely positioned away
`from underlying semiconductor device structures and layers.
`While the size of the contact openings may be made as small
`as possible not only to increase the device density but also
`to avoid electrical shorting, any reduction in the size of
`contact openings will be constrained by lithographic reso
`lution limits in patterning the openings.
`Self-aligned contact techniques have been developed to
`overcome the density and misalignment limitations of the
`above typical contact process. In a self-aligned contact
`process, an etch-stop layer must ?rst be deposited over the
`wafer to encapsulate the tops and sides of various semicon
`ductor device structures and layers prior to depositing the
`dielectric layer. Contact openings are then etched in the
`dielectric layer without risk of exposing the device struc
`tures or layas as the device structures and layers are
`protected by the encapsulating etch-stop layer. An anisotro
`pic etch is then used to remove the etch-stop layer covering
`the region in the contact openings to be contacted. When the
`contact openings are ?lled with metal, then, the device
`structures and layers will be insulated from the metal by the
`etch-stop layer and by any insulative layer covering the
`structures or layers, thus avoiding electrical shorts. Self
`aligned contact processes thus prove to be extremely useful
`in fabricating high-density devices without risk of electrical
`shorting. Indeed, electrical shorting is avoided despite any
`misalignment in the contact etch mask.
`Despite the above advantages gained from self-aligned
`contact processes, they nevertheless suffer many drawbacks.
`For example, the contact opening etch demands a highly
`selective etch chemistry in order to reliably etch into the
`
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`dielectric layer without etching the etch-stop layer. The high
`selectivity required for these etch chemistries is di?icult to
`achieve. Another drawback of the etch technique is that
`unwanted polymers may be formed in the contact openings
`when stopping on the etch-stop layer. Cleaning such poly
`mers from the contact openings only proves to make the
`contact process more di?icult, particularly where the contact
`openings have high aspect ratios.
`Furthermore, the device structures and layers in the wafer
`for typical self-aligned contact processes must be fully
`encapsulated in the etch-stop layer which includes forming
`a cap as well as sidewall spacers of the etch-stop material
`over each of the device structures and layers not only to fully
`protect the them from being exposed during the contact etch
`but also to insulate them from the contact metal. When a
`contact is formed between two closely spaced device
`structures, then, the area of contact to the underlying dilfu
`sion region becomes signi?cantly reduced because of the
`etch-stop sidewall spacers. A reduction in contact area only
`serves to increase the e?ective resistance of the contact.
`These sidewall spacers also create a higher aspect ratio for
`the contact opening. Consequently, the available contact ?ll
`methods which may be used for self-aligned contacts
`becomes limited as less contact frll methods will have the
`step coverage required to create reliable contacts.
`Thus, what is needed is a simpler self-aligned contact
`process for semiconductor device fabrication. What is also
`needed is a semiconductor device fabrication process for
`forming self-aligned contacts with decreased aspect ratios so
`as to provide larger contact areas and to reduce the step
`coverage required to create reliable contacts.
`
`BRIEF SUMMARY OF THE INVENTION
`‘The present invention advantageously simpli?es typical
`self-aligned processes for semiconductor device fabrication
`by eliminating the need to use a highly selective etch
`chemistry to etch contact openings for self-aligned contacts.
`The present invention also provides for decreased aspect
`ratios for self-aligned contacts by eliminating the need to
`have etch-stop sidewall spacers, thus providing for larger
`contact areas and reducing the step coverage required to
`create reliable contacts.
`In accordance with the present invention, a layer of a ?rst
`material is formed over a semiconductor wafer. This ?rst
`material layer is patterned to form a post over the wafer. A
`layer of a second material is formed over the wafer and
`around the post The post is removed to form an opening in
`the second material layer. The ?rst material may contain a
`photosensitive material, polysilicon, or other material. The
`opening in the second material layer may be ?lled with a
`third material. The second material may contain an insula
`tive material while the third material may contain a conduc
`tive material. The ?rst material may be patterned by etching
`the ?rst material to form the post. Also, the second material
`may be planarized.
`While the above advantages of the present invention have
`been described, other attendant advantages, objects, and
`uses of the present invention will become evident to one of
`ordinary skill in the art based on the following detailed
`description of the present invention with reference to the
`accompanying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`The present invention is illustrated by way of example
`and not limitation in the ?gures of the accompanying
`drawings in which like references indicate similar elements
`and in which:
`
`SAMSUNG-1004.011
`
`

`

`5,710,061
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`3
`FIG. 1 illustrates in the form of a flow diagram an
`exemplary method for disposable post processing for semi
`conductor device fabrication in accordance with the present
`invention;
`FIG. 2a illustrates a partial cross-sectional view of a
`semiconductor wafer after the formation of photosensitive
`material in accordance with the present invention;
`FIG. 2b illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 2a where the photosensitive material
`has been patterned to create a post in accordance with the
`present invention;
`FIG. 20 illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 2b where a planar layer has been
`formed around the post in accordance with the present
`invention;
`FIG. 2d illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 2c where the post has been removed to
`create an opening in accordance with the present invention;
`FIG. 2e illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 2d where the opening has been ?lled
`in accordance with the present invention;
`FIG. 3 illustrates in the form of a ?ow diagram another
`exemplary method for disposable post processing for semi
`conductor device fabrication in accordance with the present
`invention;
`FIG. 4a illustrates a partial cross-sectional view of a
`semiconductor water after the formation of an etch-stop
`layer, post-material layer, optional hard mask layer, and a
`patterned photoresist layer in accordance with the present
`invention;
`FIG. 4b illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 4a where the post-material has been
`patterned to create a post in accordance with the present
`invention;
`FIG. 40 illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 4b where a planar layer has been
`formed around the post in accordance with the present
`invention;
`FIG. 4d illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 40 where the post has been removed to
`create an opening in accordance with the present invention;
`FIG. 4e illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 4d where the opening has been ?lled
`in accordance with the present invention;
`FIG. 5a illustrates a partial cross-sectional view of a
`semiconductor wafer having a planar layer with two posts
`where a material has been formed over the planar layer in
`accordance with the present invention;
`FIG. 5b illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 5a where the material has been
`patterned to create a post in accordance with the present
`invention;
`FIG. 50 illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 5b where a planar layer has been
`formed around the post in accordance with the present
`invention;
`FIG. 5d illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 50 where the post has been removed to
`create an opening in accordance with the present invention;
`FIG. 5e illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 5d where the opening has been ?lled
`in accordance with the present invention; and
`FIG. 6 illustrates a partial cross-sectional view of a
`semiconductor wafer where an interconnect structure has
`been formed in accordance with the present invention.
`
`45
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`55
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`65
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`4
`DETAILED DESCRIPTION
`A speci?c embodiment or embodiments in accordance
`with the present invention for disposable post processing for
`semiconductor device fabrication is described. In the fol
`lowing description, numerous speci?c details are set forth
`such as speci?c thicknesses, materials, processing
`sequences, deposition methods, semiconductor devices, etc.,
`in order to provide a thorough understanding of the present
`invention. It will be evident, however, to one of ordinary
`skill in the art that the present invention may be practiced
`without these speci?c details. In other instances, well-known
`processing steps, equipment, etc., have not been described in
`particular detail so that the present invention is not unnec
`essarily obscured.
`FIG. 1 illustrates, in the form of a ?ow diagram, an
`exemplary method for disposable post processing for semi
`conductor device fabrication in accordance with the present
`invention. So as to better explain the method of FIG. 1,
`FIGS. 2a-2e will be used to illustrate the steps performed in
`the method of FIG. 1. For the disposable post processing of
`the semiconductor wafer partially illustrated in FIG. 2a-2e,
`a semiconductor substrate is provided, as illustrated in FIG.
`2a by substrate 200. This substrate may be a silicon
`substrate, yet it is to be appreciated that a variety of other
`types of semiconductor substrates may be used, for example,
`depending upon one’s speci?c design and/or functional
`requirements for the semiconductor device to be fabricated.
`Regardless of the type of substrate, various processing
`steps may be performed prior to the disposable post process
`in accordance with the present invention. For example,
`various isolation structures and semiconductor devices may
`be formed over the substrate prior to the disposable post
`process in accordance with the present invention, as illus
`trated in FIG. 2a where diffusion region 201, ?eld oxide
`region 202, and a MOS transistor including a polycrystalline
`silicon (polysilicon) gate 210 surrounded by an outer insu
`lative silicon dioxide (SiO2) layer 211 have been formed. It
`is to be understood, though, that the disposable post pro
`cessing in accordance with the present invention may be
`used after other semiconductor structures and various levels
`of semiconductor structures have been formed over the
`substrate. For example, the disposable post processing in
`accordance with the present invention may be used at any
`contact or via level in order to form contact openings and/or
`vias. It is to be further understood that the speci?c process
`ing steps performed may depend upon one’s speci?c design
`and/or functional requirements for the semiconductor device
`to be fabricated
`In Step 100 of FIG. 1, a photosensitive material is formed
`over the semiconductor wafer, as illustrated in FIG. 2a
`where a layer of photosensitive material 220 has been
`formed over the semiconductor wafer. This photosensitive
`material may include, for example, photoresist or a photo
`sensitive polyimide. The photosensitive material coated over
`the wafer preferably has a thickness which accounts for the
`highest topology of the wafer, any minimum insulation
`thickness needed over the wafer’s topology, and optionally
`an etch-back margin as this photoresist may later be etched
`as will be discussed below. For example, in coating the
`photosensitive material over the wafer illustrated in FIG. 2a,
`the thickness of photosensitive material 220 is preferably as
`great as if not greater than the thickness of polysilicon gate
`210 plus the thickness of oxide insulative layer 211 over
`polysilicon gate 210 plus the minimum insulation thickness
`needed over the MOS transistor formed by polysilicon gate
`210 and oxide insulative layer 211 plus an optional etch
`
`SAMSUNG-1004.012
`
`

`

`5,710,061
`
`5
`back margin to account for subsequent etching. While in this
`example photosensitive material 220 may be approximately
`10,000 angstroms (A) in thickness, other thicknesses may
`also be used.
`In Step 110 of FIG. 1, then, this photosensitive material is
`patterned into posts, as illustrated in FIG. 2b where post 221
`has been formed over substrate 200. The photosensitive
`material is patterned into posts by the exposure of radiation,
`for example ultra-violet light, through a mask and by the
`subsequent development of the photosensitive material. In
`one embodiment where the photosensitive material contains
`photoresist, a negative tone mask or an image reversal
`process using a positive tone mask may be used.
`Furthermore, the pro?le or cross-dimensions in various
`sections of the posts may be varied, for example, by con
`trolling the exposure energy when exposing the photoresist
`through the mask. After being patterned these photoresist
`posts are preferably cured using a deep ultra-violet (UV)
`light exposure to harden the photoresist in the posts. Here,
`the polymers in the photoresist will become cross-linked
`during the deep UV cure so as to prevent the photoresist
`posts from later ?owing or shrinking when exposed to
`elevated temperatures. As will be seen below, this may be
`needed in order for the posts to withstand subsequent
`processing steps.
`The photosensitive material may be patterned such that
`the remaining photosensitive material after development
`de?nes the desired shapes and locations of openings for a
`layer to be formed over the surface of the wafer. In other
`words, the photosensitive material is patterned to de?ne
`posts whose subsequent removal will create openings in an
`overlying layer formed over the wafer, for example, so that
`appropriate contacts and interconnects may be formed. It is
`to be appreciated that the posts may be of any shape and that
`the term post is not meant to be limited in meaning but rather
`includes, for example, any material used to de?ne the
`location and shape of openings for a subsequently formed
`layer. For example, the term post encompasses long thin
`lines of material to form long thin openings.
`In the illustration of FIG. 2b, photosensitive material 220
`has been patterned to form post 221 over diffusion region
`201 so as to later form a contact opening in an insulative
`layer to be formed over the surface of the wafer. With this
`contact opening, a contact may later be formed to provide
`for electrical connection to the underlying di?zusion region
`201 of substrate 200. It is to be appreciated that post 221 in
`this illustration is adjacent to and partially overlies the top of
`the MOS transistor.
`Next in Step 120 of FIG. 1 a planar layer is formed around
`the posts over the substrate. This is illustrated in FIG. 20
`where planar layer 230 has been formed around post 221
`over substrate 200. This layer may be an insulative layer
`formed, for example, by forming a CVD silicon dioxide
`(SiO2), Silicon nitride (Si3N4), borophosphosilicate glass
`(BPSG), a low-temperature oxide (LTO), an oxynitride, a
`polyimide, or any other suitable dielectric material using
`suitable methods. Such an insulative layer may also be
`formed by using a combination of two or more layers of
`suitable dielectric materials. It is to be appreciated that the
`formation of the layer which is to surround the posts as well
`as any etch-back, polishing, and/or re?ow of the overlying
`layer may involve heating the wafer to elevated tempera
`tures. Accordingly, where the photosensitive material used
`to create the posts contains photoresist, the posts have been
`preferably hardened as discussed above using a deep UV
`65
`cure so as to preserve the posts during such processing steps.
`Furthermore, the thiclmess of the layer surrounding the posts
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`may be of any thiclmess depending, for example, on any
`electrical isolation needed between an underlying layer and
`a layer to be subsequently formed, any structural
`requirements, or the amount required to provide planariza
`tion as well as any other design or functional requirements.
`In one embodiment, a spin-on glass (SOG) layer is ?rst
`formed over the wafer and subsequently cured, for example,
`at approximately 350 degrees Celsius, as is required to
`withstand subsequent polishing. This ?rst SOG layer is
`preferable since it is spun-on as a liquid and hence thor
`oughly ?lls and covers the surface of the wafer. Where
`photoresist posts are used, the ?rst SOG layer is then
`post-baked, for example, at approximately 350 degrees
`Celsius or other temperatures so that the ?rst SOG layer may
`withstand subsequent polishing. It is to be appreciated that
`for most photoresists which are used for the posts, this ?rst
`SOG layer may not be ?nally cured as any elevated tem
`peratures at or beyond approximately 400 degrees Celsius
`may cause considerable shrinkage of such photoresist posts
`and may make the photoresist posts more di?icult to remove.
`A doped tetraethyl orthosilicate (TEOS) based silicon diox
`ide (Si02) layer is then deposited over the ?rst SOG layer
`using a plasma-enhanced chemical vapor deposition
`(PECV D).
`In another embodiment, a silicate SOG is used to form the
`planar layer. This silicate SOG layer is preferable since it is
`spun-on as a liquid and hence thoroughly ?lls and covers the
`surface of the wafer, leaving a planar sin-face. Where pho
`toresist posts are used, this silicate SOG layer is then
`post-baked, for example, at approximately 250 degrees
`Celsius or other suitable temperatures to remove solvents
`prior to subsequent etching or at approximately 350 degrees
`Celsius or other suitable temperatures to withstand subse
`quent polishing as will be discussed below. It is to be
`appreciated that for most photoresists which are used for the
`posts, this ?rst SOG layer may not be ?nally cured as any
`elevated temperatures at or beyond approximately 400
`degrees Celsius may cause considerable shrinkage of such
`photoresist posts and may make the photoresist posts more
`dii?cult to remove.
`Once the layer to surround the posts has been formed, the
`layer may be planarized using suitable methods, for example
`with a planarizing etch-back or polishing technique. In one
`embodiment polishing may be performed using a chemical
`mechanical polishing (CMP) technique where a polish slurry
`with a chemis1ry including a colloidal silica may be used. In
`planarizing the overlying layer which surrounds the posts,
`the posts are preferably also planarized and exposed at the
`surface of the water so as to facilitate their later removal
`from the planar layer. Where, however, the overlying layer
`surrounding the posts is, for example, spun-on or re?own, a
`planarizing etch-back or polishing may not be necessary as
`the surface of the overlying layer may already be planar.
`Preferably, any residue formed over the posts, though, is
`removed so as to facilitate their later removal from the
`overlying layer. For example, in the embodiment discussed
`above where a silicate SOG is used to form the overlying
`planar layer, a ?uorine-based plasma oxide etch may be used
`to remove any residue from the SOG formation which
`remains over the top of the posts. In this manner, the wafer’s
`surface remains planar while the posts may be exposed for
`later removal. Furthermore, it is to be appreciated that where
`the overlying layer is spun-on, re?own, or is otherwise
`planar, the formation of the photosensitive material used to
`create the posts may not need to account for the etch-back
`margin discussed above with regard to the thickness of
`photosensitive material.
`
`SAMSUNG-1004.013
`
`

`

`5,710,061
`
`15
`
`25
`
`35
`
`7
`In Step 130 of FIG. 1, then, the posts are removed leaving
`respective openings throughout the planar layer, as illus
`trated in FIG. 2d where opening 240 has been formed in
`layer 230 by the removal of post 221. The technique used to
`remove the posts may depend on the material used for the
`posts as well as that used for the overlying planar layer.
`Preferably, the technique used to remove the posts causes
`little if any damage to the underlying surface, such as ion
`damage which may increase the resistance of the contacts
`formed from the openings. Furthermore, this technique
`preferably does not create any unwanted polymer formations
`which may have to be cleaned out of the openings. Where
`photoresist is used to create the posts, the posts may be, for
`example, ashed out using an oxygen plasma etch, etched out
`using a sulfuric acid, or dissolved using organic solvents.
`Such techniques will not damage the underlying substrate
`and will not form unwanted polymers in the openings.
`It is to be appreciated here that where the posts contain
`photoresist, the planar layer may now be ?nally cured
`following removal of the posts. For example, in the embodi
`ments discussed above where a SOG layer and a doped
`TEOS SiO2 layer are used to form the planar layer and
`where SOG is used to form the planar layer, these layers may
`be ?nally cured at approximately 700 degrees Celsius,
`although other temperatures may be used.
`Lastly, in Step 140 of FIG. 1, a material is formed in the
`openings, as illustrated in FIG. 2e where opening 240 has
`been ?lled with material 250. For example, the openings
`may be ?lled to create appropriate contacts or interconnect
`lines using a blanket CVD tungsten (W) deposition and
`etch-back process to ?ll the openings. Other methods as well
`as other suitable conductive materials, for example alumi
`num (Al) and polysilicon, may also be used to form suitable
`contacts from the openings. It is to be appreciated that the
`openings do not have to be completely ?lled to create
`suitable contacts to the underlying regions but rather any
`suitable conductive material may be formed in the opening
`so long as electrical connection is provided to the underlying
`regions. For example, a layer of conductive material may be
`formed only over the underlying region to be contacted and
`along a portion of a sidewall of the opening to provide
`suitable contact to the underlying region.
`FIG. 3 illustrates, in the form of a ?ow diagram, another
`exemplary method for disposable post processing for semi
`conductor device fabrication in accordance with the present
`invention. So as to better explain the method of FIG. 3,
`FIGS. 4a-4e will be used to illustrate the steps performed in
`the method of FIG. 3. It is to be understood that the above
`discussion regarding substrate 200 in the method of FIG. 1
`likewise applies for substrate 400, as illustrated in FIGS.
`4a-4e, in the method of FIG. 3. Furthermore, the above
`discussion regarding the various processing steps which may
`be performed prior to the disposable post process in accor
`dance with the present invention also applies for the method
`of FIG. 3. As illustrated in FIG. 4a, for example, a doped
`region 401, ?eld oxide region 402, and a MOS transistor
`including a polycrystalline silicon (polysilicon) gate 410
`surrounded by an outer insulative silicon dioxide (SiOQ
`layer 411 may be formed over substrate 400.
`In Step 300 of FIG. 3, an etch-stop layer is formed over
`the surface of the wafer, as illustrated in FIG. 4a where
`etch-stop layer 405 has been formed over substrate 400. In
`one embodiment this etch-stop layer is formed by growing
`in the range of approximately 30 A to approximately 200 A
`65
`of silicon dioxide (SiO2) over exposed silicon (Si) areas on
`the surface of the wafer. Alternatively, this oxide etch-stop
`layer may be deposited over the wafer. In either instance,
`
`8
`other oxide thicknesses may be used. Furthermore, other
`materials, for example a CVD deposited silicon nitride
`(Si3N4), may be used in forming this etch-stop layer. It is to
`be appreciated that the material chosen for this etch-stop
`may depend on other factors for reasons which will follow.
`In Step 310 of FIG. 3, a layer of material is formed over
`the semiconductor wafer, as illustrated in FIG. 4a where a
`layer of material 420 has been deposited over the semicon
`ductor wafer. This material may include, for example,
`polysilicon, aluminum, or tungsten, and for this discussion
`is termed “post-material.” Preferably, this post-material is
`chosen talo'ng into account that it will later be etched. In this
`connection, an etch-technique may be used which etches the
`post-material at a higher rate than the etch-stop material,
`thus preventing the underlying surface ?'om being damaged
`by the etch. In one embodiment where the etch-stop layer
`co