United States Patent [19]
`Cleeves
`
`[54] METHOD FOR REDUCED PITCH
`LITHOGRAPHY
`
`[75] Inventor: James M. Cleeves. Redwood City,
`Calif.
`
`[73] Assignee: Cypress Semiconductor Corporation, >
`Calif.
`
`[21] Appl. No.: 740,145
`[22] Filed:
`Oct. 22, 1996
`
`Related US. Application Data
`
`[63] Continuation of Ser. No. 361,595, Dec. 22, 1994, aban
`doned.
`
`[51] Int. (:1.6 ...................................................... .. G03F 7/20
`[52] US. Cl. ........................ .. 430/315; 430/313; 430/328;
`'
`430/330
`[58] Field of Search ................................... .. 430/311, 313,
`430/315, 324, 328, 330
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`US005652
`[11] Patent Number:
`[45] Date of Patent:
`
`5,652,084
`Jul. 29, 1997
`
`Ueno, et al., “A High Quarter-Micron Planarized Intercon
`nection Technology with Self-Aligned Plug”, IEDM, Apr.
`1992. pp. 305-308.
`Kusters, et al., “A High Density 4Mbit dRAM Process Using
`A Fully Overlapping Bitline Contact (FoBIC) Trench Cell”,
`1987 Symposium on VLSI Technology Digest of Technical
`Papers, May 18-21, 1987/Karuizawa, pp. 93-94.
`Kakumu, et al., “PASPAC (Planarized Al/Silicide/Poly Si
`with Self Aligned Contact) with Low Contact Resistance
`and High Reliability in CMOS LSIs”, 1987 Symposium on
`VLSI Technology Digest of Technical Papers, May 18-21,
`1987/Karuizawa, pp. 77-78.
`Kenny, et al., “A Buried-Plate Trench Cell for a 64-Mb
`DRAM”, 1992 Symposium on VLSI Technology Digest of
`Technical Papers, Apr. 1992, pp. 14-15.
`Subbanna, et al., “A Novel Borderless Contact/Interconnect
`Technology Using Aluminum Oxide Etch Stop for High
`Performance SRAM and Logic”, Dec. 1993, pp. 441-444.
`
`(List continued on next page.)
`
`Primary Examiner—Kathleen Duda
`Attomey, Agent, or Firm—Blakely, Sokolo?’, Taylor & Zaf
`man, LLP
`
`4,548,688 10/1985 Matthews .............................. .. 430/325
`4,775,609 10/1988 McFarland
`430/325
`
`[57]
`
`ABSTRACT
`
`3/1989 Ziger . . . . . . . .
`4,814,243
`5/1989 Orvek ......... ..
`4,826,756
`8/1989 Maheras et al. ..
`4,859,573
`2/1990 Collins ....... ..
`4,904,866
`3/1990 Suwa et al.
`4,908,656
`6/1990 McColgin
`4,931,351
`l/l991 Tsuji et a1.
`4,985,374
`5,158,910 10/1992 Cooper et a1.
`5,219,787
`6/1993 Carey et a1. ..
`
`5,270,236 12/1993 Rosner . . . . .
`
`. . . .. 430/30
`430/328
`.. 430/326
`250/4922
`355/53
`430/323
`.. 430/229
`.. 437/195
`.. 437/187
`
`. . . .. 437/48
`
`430/325
`4/1994 Angelopolus
`5,300,403
`257/760
`6/1994 Matsuura ....... ..
`5,319,247
`.. 430/312
`6/1994 Haraguchi et al.
`5,320,932
`5,352,630 10/1994 Kim et a1. ............................. .. 437/195
`
`OTHER PUBLICATIONS
`
`Fukase, et al, “A Margin-Free Contact Process Using An
`A1203 Etch-Stop Layer For High Density Devices”, IEDM,
`Apr. 1992, pp. 837-840.
`
`A lithographic patterning process uses multiple exposures to
`provide for relatively reduced pitch for features of a single
`patterned layer. A ?rst imaging layer is exposed to radiation
`in accordance with a ?rst pattern and developed. The result
`ing patterned layer is stabilized A second imaging layer is
`subsequently formed to surround the ?rst patterned layer,
`exposed to radiation in accordance with a second pattern,
`and developed to form a second patterned layer. As the ?rst
`patterned layer has been stabilized, the ?rst patterned layer
`remains with the second patterned layer to produce a single
`patterned layer. For another embodiment, a single imaging
`layer is patterned by exposure to radiation in accordance
`with two separate patterns. An exposed portion of the
`imaging layer is suitably stabilized to withstand subsequent
`lithographic process steps.
`
`16 Claims, 10 Drawing Sheets
`
`IOU f FORM FIRST IMAGING LAYER
`
`l
`
`110 \f
`
`PATTERN FIRST IMAGING LAYER IN
`ACCORDANCE WITH FIRST PATTERN
`
`1250f
`
`STADILIZE FIRST PATTERNED LAYER
`
`I
`
`FORM SECOND IMAGING LAYER
`
`I
`
`"of
`
`PATTERN SECOND IMAGING LAYER IN
`ACCORDANCE WITH 5ECOND PATTERN
`
`SAMSUNG-1001.001
`
`

`

`5,652,084
`Page 2
`
`OTHER PUBLICATIONS
`
`Kusters, et al., “A Stacked Capacitor Cell with a Fully
`Self-Aligned Contact Process for High-Density Dynamic
`Random Access Memories”, Journal of the Electrochemical
`Society. vol. 139, No. 8, Aug. 1992, pp. 2318-2321.
`“Method for Forming Via Hole Formation”. IBM Technical
`Disclosure Bulletin. vol. 34, No. 10A, Mar. 1992, pp.
`219-220.
`“Self-Aligned, Borderless Polysilicon Contacts Using Poly
`silicon Pillars”, IBM Technical Disclosure Bulletin, vol. 35,
`No. 2, Jul. 1992, pp. 480-483.
`S. Wolf, Ph.D., et a1., “Silicon Processing for the VLSI Era,
`vol. I: Process Technology”, Lithography I: Optical Resist
`Materials and Process Technology, 1986, pp. 453-454.
`S. Wolf. Ph.D., “Silicon Processing for the VLSI Era, vol. 2:
`Process Integration”, Multilevel-Interconnect Technology
`for VLSI & ULSI, 1992, pp. 222-237.
`‘Method to Incorporate Three Sets of Pattern Information in
`Two Photomasking Steps.” IBM Technical Disclosure Bul
`letin, vol. 32, No. 8A, pp. 218-219 (Jan. 1990).
`
`“Dual-Image Resist for Single-Exposure Self-Aligned Pro
`cessing,” IBM Technical Disclosure Bulletin, vol. 33, No. 2.
`pp. 447-449 (Jul. 1990).
`“Complementary Selective Writing by Direct-Write
`B-Beam/Optical Lithography Using Mixed Positive and
`Negative Resist,” IBM Technical Disclosure Bulletin, vol.
`33, No. 3A, pp. 62-63 (Aug. 1990).
`
`“Sub-Micron Channel Length CMOS Technology.” IBM
`Technical Disclosure Bulletin, vol. 33, N0. 4, pp. 227-232
`(Sep. 1990).
`‘Multilayer Circuit Fabrication Using Double Exposure of
`Positive Resist.” IBM Technical Disclosure Bulletin, vol. 36,
`No. 10, pp. 423-424 (Oct. 1993).
`
`Wolf, S., et a1., Silicon Processing for the VLSI Era, vol. 1:
`Process Technology, Lattice Press, Sunset Beach, Califor
`nia, pp. 407-458 (1986).
`
`SAMSUNG-1001.002
`
`

`

`US. Patent
`
`Jul. 29, 1997
`
`Sheet 1 of 10
`
`5,652,084
`
`100
`
`110
`
`I50
`
`140
`
`FORM FIRST IMAGING LAYER
`
`PATTERN FIRST IMAGING LAYER IN
`ACCORDANCE WITH FIRST PATTERN
`
`STABILIZE FIRST PATTERNED LAYER
`
`FORM SECOND IMAGING LAYER
`
`PATTERN SECOND IMAGING LAYER IN
`ACCORDANCE WITH SECOND PATTERN
`
`Fig.1 T
`
`SAMSUNG-1001.003
`
`

`

`US. Patent
`
`Jul. 29, 1997
`
`221
`
`222?
`
`5,652,084
`
`S 225
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`252
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`Fig.5
`
`292
`
`SAMSUNG-1001.004
`
`

`

`U.S. Patent
`
`Jul. 29, 1997
`
`Sheet 3 0f 10
`
`5,652,084
`
`241?
`
`24-2?
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`245 .m
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`
`SAMSUNG-1001.005
`
`

`

`US. Patent
`
`Jul. 29, 1997
`
`Sheet 4 of 10
`
`5,652,084
`
`500
`
`FORM IMAGING LAYER
`
`510
`
`ExRosE IMAGING LAYER IN
`ACCORDANCE WITH FIRST PATTERN
`
`52M STABILIZE EXPOSED PORTION OF IMAGING LAYER
`
`55
`
`EXPOGE IMAGING LAYER IN
`ACCORDANCE WITH SECOND PATTERN
`
`I
`
`5TA5ILIZE EXPOGED PORTION OF IMAGING LAYER
`
`55
`
`DEVELOP IMAGING LAYER
`
`Fig.6
`
`SAMSUNG-1001.006
`
`

`

`US. Patent
`
`Jul. 29, 1997
`
`Sheet 5 of 10
`
`5,652,084
`
`421
`
`425
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`
`SAMSUNG-1001.007
`
`SAMSUNG-1001.007
`
`
`
`

`

`US. Patent
`
`Jul. 29, 1997
`
`Sheet 6 of 10
`
`5,652,084
`
`
`
`7l3%VA
`
`Fig.1O
`
`SAMSUNG-1001.008
`
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`
`SAMSUNG-1001.008
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`
`

`

`U.S. Patent
`
`Jul. 29, 1997
`
`Sheet 7 0f 10
`
`5,652,084
`
`451
`
`452
`
`455
`
`Ls
`
`Fig.“
`
`SAMSUNG-1001.009
`
`

`

`U.S. Patent
`
`Jul. 29, 1997
`
`Sheet 8 0f 10
`
`5,652,084
`
`500
`
`510
`
`FORM IMAGING LAYER
`
`ExPosE IMAGING LAYER IN
`ACCORDANCE WITH FIRST PATTERN
`
`52M
`
`OTAEILIZE ExPOsEO PORTION OF
`IMAGING LAYER
`
`55
`
`EXPOSE IMAGING LAYER IN
`ACCORDANCE WITH SECOND PATTERN
`
`I
`
`DEVELOP IMAGING LAYER
`
`Fig.12
`
`SAMSUNG-1001.010
`
`

`

`US. Patent
`
`Jul. 29, 1997
`
`Sheet 9 of 10
`
`5,652,084
`
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`
`SAMSUNG-1001.011
`
`SAMSUNG-1001.011
`
`

`

`US. Patent
`
`Jul. 29, 1997
`
`Sheet 10 0f 10
`
`5,652,084
`
`641
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`SAMSUNG-1001.012
`
`

`

`1
`METHOD FOR REDUCED PITCH
`LITHOGRAPHY
`
`5,652,084
`
`2
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`This is a continuation of application Ser. N o. 08/361,595,
`?led Dec. 22. 1994. now abandoned.
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates generally to the ?eld of
`semiconductor fabrication. More particularly, the present
`invention relates to the ?eld of lithography processing for
`semiconductor fabrication.
`2. Description of the Related Art
`Lithography processes are typically used for semiconduc
`tor fabrication, for example to form a mask over a layer to
`be patterned in accordance with various functional and/or
`design requirements for fabricating a desired semiconductor
`device.
`For a typical lithography process, photoresist is deposited
`over the layer to be patterned and is exposed to ultraviolet
`radiation through a mask that de?nes the pattern to be
`formed in the photoresist. The photoresist is then developed
`to form a patterned photoresist layer over the underlying
`layer to be patterned. Those portions of the underlying layer
`that are not covered by photoresist may then be etched using
`suitable etch techniques and chemistries. The pattern in the
`photoresist is thus replicated in the underlying layer.
`Typical lithography processes, however, limit the size and
`density with which semiconductor devices may be fabri
`cated. For example, the minimum resolution capability of
`the lithography process determines the minimal pitch with
`which features for a patterned layer may be printed The
`minimum lithographic resolution for a patterning process
`may depend, for example, on the lens used in exposing
`photoresist to radiation through the mask.
`BRIEF SUMMARY AND OBJECTS OF THE
`INVENTION
`One object of the present invention is to provide for a
`relatively reduced pitch for features of a patterned layer.
`Another object of the present invention is to provide for
`the fabrication of relatively denser semiconductor devices.
`Another object of the present invention is to provide for
`the fabrication of relatively smaller-sized semiconductor
`devices.
`A lithography method for semiconductor fabrication
`using a semiconductor wafer is described. For the lithogra
`phy method, a ?rst imaging layer is formed over the semi
`conductor wafer. The ?rst imaging layer is patterned in
`accordance with a ?rst pattern to form a ?rst patterned layer.
`The ?rst patterned layer is stabilized. A second imaging
`layer is formed over the ?rst patterned layer such that the
`?rst patterned layer is surrounded by the second imaging
`layer. The second imaging layer is patterned in accordance
`with a second pattern to form a second patterned layer.
`Another lithography method for semiconductor fabrica
`tion using a semiconductor wafer is also described For the
`lithography method, an imaging layer is formed over the
`semiconductor wafer. A portion of the imaging layer is
`exposed to radiation in accordance with a ?rst pattern. The
`exposed portion of the imaging layer is stabilized. The
`imaging layer is patterned in accordance with a second
`pattern to form a patterned layer.
`Other objects, features. and advantages of the present
`invention will be apparent from the accompanying drawings
`and from the detailed description that follows below.
`
`10
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`The present invention is illustrated by way of example
`and not limitation in the ?gures of the accompanying
`drawings, in which like references indicate similar elements
`and in which:
`FIG. 1 illustrates, in ?ow diagram form, one lithography
`method for semiconductor fabrication;
`FIG. 2 illustrates a cross-sectional view of a semiconduc
`tor wafer having a ?rst imaging layer being exposed to
`radiation through a ?rst mask;
`FIG. 3 illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 2 after the ?rst imaging layer has been
`developed;
`FIG. 4 illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 3 where a second imaging layer is
`formed over the wafer and is being exposed to radiation
`through a second mask;
`FIG. 5 illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 4 after the second imaging layer has
`been developed;
`FIG. 6 illustrates, in ?ow diagram form, another lithog
`raphy method for semiconductor fabrication;
`FIG. 7 illustrates a cross-sectional view of a semiconduc
`tor wafer having an imaging layer being exposed to radiation
`through a ?rst mask;
`FIG. 8 illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 7 after an exposed portion of the
`imaging layer has been stabilized;
`FIG. 9 illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 8 Where the imaging layer is exposed
`to radiation through a second mask;
`FIG. 10 illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 9 after an exposed portion of the
`imaging layer has been stabilized;
`FIG. 11 illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 10 after the imaging layer has been
`developed;
`FIG. 12 illustrates, in ?ow diagram form, another lithog
`raphy method for semiconductor fabrication;
`FIG. 13 illustrates a cross-sectional view of a semicon
`ductor wafer having an imaging layer being exposed to
`radiation through a ?rst mask;
`FIG. 14 illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 13 after an exposed portion of the
`imaging layer has been stabilized;
`FIG. 15 illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 14 where the imaging layer is exposed
`to radiation through a second mask; and
`FIG. 16 illustrates a cross-sectional view of the semicon
`ductor wafer of FIG. 15 after the imaging layer has been
`developed
`
`DETAILED DESCRIPTION
`The following detailed description sets forth an embodi
`ment or embodiments in accordance with the present inven
`tion for method for reduced pitch lithography. In the fol
`lowing description, details are set forth such as speci?c
`materials, thicknesses, parameters, etc.. in order to provide
`a thorough understanding of the present invention. It will be
`evident. however. that the present invention may be prac
`ticed without these details. In other instances, well-known
`process steps, equipment, etc., have not been described in
`particular detail so as not to obscure the present invention.
`
`SAMSUNG-1001.013
`
`

`

`5,652,084
`
`15
`
`25
`
`35
`
`3
`FIG. 1 illustrates. in ?ow diagram form, one lithography
`method for semiconductor fabrication. For one embodiment,
`the method of FIG. 1 may be used for semiconductor
`fabrication using a semiconductor wafer, such as the semi
`conductor wafer illustrated in FIGS. 2. 3. 4. and 5 for
`example.
`For the method of FIG. 1. a semiconductor substrate 200
`is provided as illustrated in FIG. 2. Substrate 200 may
`include any suitable semiconductor material, including sili
`con (Si) for example.
`As illustrated in FIG. 2. a layer 210 may be formed over
`substrate 200. Layer 210 may include any suitable material
`and may be formed to any suitable thickness using any
`suitable technique depending. for example, on the purpose
`of layer 210 in fabricating a desired semiconductor device.
`Layer 210 may include one or more layers, including device.
`dielectric, contact. interconnect, and/or via layers for
`example. Layer 210 is not necessary to practice the method
`of FIG. 1.
`As one example. layer 210 may include a layer that is to
`be patterned in accordance with a subsequent mask layer
`formed over layer 210. Layer 210 may include a dielectric
`layer. including silicon dioxide (SiO2) for example, that is to
`be patterned for a contact or interconnect layer, for example.
`Layer 210 may also include a layer over which a via or
`interconnect layer is to be formed. Layer 210 may have
`exposed regions to be electrically coupled by vias or inter
`connects formed in a subsequent layer.
`For step 100 of FIG. 1, a ?rst imaging layer is formed over
`the semiconductor wafer. As illustrated in FIG. 2. an imag
`ing layer 220 is formed over layer 210. Imaging layer 220
`may include any suitable material formed to any suitable
`thickness using any suitable technique.
`For one embodiment. imaging layer 220 may include a‘
`suitable positive photoresist, for example, that has been
`spun-on to a thickness of approximately 10,000 Angstroms
`(A). Other suitable thiclmesses of positive photoresist. for
`example in the range of approximately 1.000 A to approxi
`mately 30.000 A, may also be used. For other embodiments,
`imaging layer 220 may include a suitable negative
`photoresist. a suitable radiation-sensitive polyimide, or other
`suitable radiation-sensitive materials for example. For this
`detailed description, the term radiation encompasses any
`energy radiated in the form of waves or particles. The term
`radiation may include ultraviolet (UV) light, x-ray radiation,
`electron beam or e-beam radiation, vacuum UV radiation, or
`ion beam radiation for example.
`For step 110 of FIG. 1, the ?rst imaging layer is patterned
`in accordance with a ?rst pattern to form a ?rst patterned
`layer. Any suitable lithographic patterning technique may be
`used and may depend. for example, on the material used for
`imaging layer 220.
`Where a positive-tone imaging material is used for imag
`ing layer 220, such as a suitable positive photoresist or a
`suitable positive-tone radiation-sensitive polyimide for
`example. imaging layer 220 may be exposed to radiation
`through a ?rst mask having opaque feature 222 and clear
`features 221 and 223 as illustrated in FIG. 2. The ?rst mask
`may include any suitable pattern of opaque and clear fea
`tures that may depend. for example, on the desired pattern to
`be formed in imaging layer 220. For this detailed
`description. the term mask encompasses a reticle, for
`example. for use in a step-and-repeat projection system.
`Imaging layer 220 may be exposed through the ?rst mask
`using any suitable form of radiation. The radiation serves to
`render soluble in a suitable developer that portion of imag
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`ing layer 220 exposed to radiation through clear features 221
`and 223. That portion of imaging layer 220 that has not been
`exposed to radiation remains relatively insoluble in the
`developer.
`Imaging layer 220 may then be developed in a suitable
`developer to form a ?rst patterned layer 232. As illustrated
`in FIG. 3, that portion of imaging layer 220 exposed to
`radiation through the ?rst mask is soluble in the developer
`and is thus dissolved from imaging layer 220. That portion
`of imaging layer 220 that has not been exposed to radiation
`is relatively insoluble in the developer. and thus remains to
`form ?rst patterned layer 232.
`For other embodiments where a suitable negative-tone
`imaging material is used for imaging layer 220, the negative
`tone imaging layer 220 may be exposed to any suitable form
`of radiation through a suitable negative-tone mask having
`opaque features 221 and 223 and a clear feature 222. for
`example. Negative-tone imaging materials may include a
`suitable negative photoresist, a suitable positive photoresist
`that is to be subjected to an image reversal process, or a
`suitable negative-tone radiation-sensitive polyimide for
`example. The negative-tone imaging layer 220 may be
`developed in a suitable developer to form a ?rst patterned
`layer 232 as illustrated in FIG. 3. That portion of imaging
`layer 220 exposed to radiation through the ?rst mask is
`relatively insoluble in the developer and thus remains to
`form ?rst patterned layer 232. That portion of imaging layer
`220 that has not been exposed to radiation is soluble in the
`developer and is thus dissolved from imaging layer 220.
`For step 120 of FIG. 1, the ?rst patterned layer is
`stabilized. Any suitable stabilization technique may be used
`and may depend for example, on the material used to form
`?rst patterned layer 232.
`First patterned layer 232 may be stabilized to withstand
`subsequent lithographic processing steps. First patterned
`layer 232 may be stabilized to withstand chemical transfor
`mation as a result of any subsequent exposure to radiation,
`for example. First patterned layer 232 may also be stabilized
`to withstand dissolution by solvents during a subsequent
`spin-on of photoresist, for example. First patterned layer 232
`may further be stabilized to withstand dissolution by a
`subsequent developer, for example.
`Where a positive photoresist is used to form ?rst patterned
`layer 232, a suitable deep ultraviolet (DUV) stabilization
`technique may be used to stabilize ?rst patterned layer 232.
`For one embodiment, ?rst patterned layer 232 may be
`irradiated with a DUV light source having a wavelength in
`the range of approximately 200 nanometers to approxi
`mately 400 nanometers, for example. and simultaneously
`heated with a temperature ramped up to approximately 230
`degrees Celsius, for example. over an approximately 60
`second period of time. for example. First patterned layer 232
`may be irradiated at that peak temperature for approximately
`5 seconds, for example. For other embodiments, ?rst pat
`terned layer 232 may be irradiated with a UV light source
`having other suitable wavelengths, for example in the range
`of approximately 100 nanometers to approximately 500
`nanometers. and may be heated to other suitable peak
`temperatures, for example in the range of approximately 120
`degrees Celsius to approximately 250 degrees Celsius. First
`patterned layer 232 may be irradiated at a peak temperature
`for any suitable length of time, for example in the range of
`approximately 2 seconds to approximately 60 seconds.
`Where ?rst patterned layer 232 includes a positive
`photoresist, ?rst patterned layer 232 may be stabilized using
`other suitable techniques. As one example. a pirst technique
`
`SAMSUNG-1001.014
`
`

`

`5,652,084
`
`5
`may be used to form a carbon ?uorine (CF4) skin over ?rst
`patterned layer 232 by exposing the photoresist to a ?uorine
`ambient. A silylation technique may also be used to form a
`silicon dioxide (SiO2) skin over ?rst patterned layer 232. For
`other embodiments, other suitable techniques may be used
`to form a hardened skin over ?rst patterned layer 232 to
`stabilize ?rst patterned layer 232. For still other
`embodiments, the positive photoresist of ?rst patterned layer
`232 may be subjected to a suitable heat treatment or to a
`suitable radiation treatment to stabilize ?rst patterned layer
`232.
`Stabilizing positive photoresist for ?rst patterned layer
`232 serves to neutralize photoactive compounds in the
`photoresist of ?rst patterned layer 232. Upon any subsequent
`exposure to radiation then, ?rst patterned layer 232 under
`goes minimal. if any, chemical transformation. The photo
`resist of ?rst patterned layer 232 may also be subjected to a
`subsequent spin-on of photoresist with relatively minimal, if
`any, dissolution by solvents of the subsequent photoresist
`layer. The photoresist of ?rst patterned layer 232 may further
`be subjected to a subsequent development with relatively
`minimal, if any, dissolution by a developer.
`For other embodiments where a negative photoresist is
`used to form ?rst patterned layer 232, ?rst patterned layer
`232 may be stabilized while ?rst patterned layer 232 is being
`patterned. Because ?rst patterned layer 232 is formed from
`that portion of negative photoresist that has been exposed to
`radiation and rendered relatively insoluble in a developer,
`the negative photoresist of ?rst patterned layer 232 is able to
`withstand chemical transformation from any subsequent
`exposure to radiation and is able to withstand dissolution by
`a subsequent developer. The photoresist of ?rst patterned
`layer 232, however, may be subjected to a suitable stabili
`zation technique as necessary to withstand dissolution by
`solvents during a subsequent spin-on of photoresist, for
`example. A suitable DUV stabilization technique, a suitable
`?rst technique, a suitable silylation technique, a suitable heat
`treatment, or a suitable radiation treatment, for example,
`may be used to stabilize the negative photoresist of ?rst
`patterned layer 232.
`For still other embodiments where a negative-tone
`radiation-sensitive polyimide is used to form ?rst patterned
`layer 232, ?rst patterned layer 232 may be stabilized while
`?rst patterned layer 232 is being patterned. Because ?rst
`patterned layer 232 is formed from that portion of polyimide
`that has been exposed to radiation and rendered relatively
`insoluble in a developer, the polyimide of ?rst patterned
`layer 232 is able to withstand chemical transformation from
`any subsequent exposure to radiation and is able to with
`stand dissolution by a subsequent developer. The polyimide
`of ?rst patterned layer 232, however, may be subjected to a
`suitable stabilization technique, such as by heat treatment
`for ?nal curing for example, as necessary to withstand
`dissolution by the formation of a subsequent layer over ?rst
`patterned layer 232, for example.
`For step 130 of FIG. 1, a second imaging layer is formed
`over the semiconductor wafer. As illustrated in FIG. 4, an
`imaging layer 240 is formed over ?rst patterned layer 232
`and over layer 210. Imaging layer 240 is formed to surround
`?rst patterned layer 232 on the sidewalls of ?rst patterned
`layer 232. Imaging layer 240 may optionally be formed to
`cover the top of ?rst patterned layer 232 as well. Imaging
`layer 240 may include any suitable material fonned to any
`suitable thickness using any suitable technique.
`For one embodiment. imaging layer 240 may include a
`suitable positive photoresist, for example. that has been
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`spun-on to a thickness of approximately 10,000 A. Other
`suitable thicknesses of positive photoresist, for example
`thicknesses approximately equal to or greater than that of
`?rst patterned layer 232, may also be used. Imaging layer
`240 may include other suitable materials, including a suit
`able negative photoresist, a suitable radiation-sensitive
`polyimide, or other suitable radiation-sensitive materials for
`example. For embodiments where photoresist is spun-on to
`form imaging layer 240, ?rst patterned layer 232 has pref
`erably been stabilized to withstand dissolution by solvents
`during spin-on of the photoresist for imaging layer 240.
`For step 140 of FIG. 1. the second imaging layer is
`patterned in accordance with a second pattern to form a
`second patterned layer. Any suitable lithographic patterning
`technique may be used and may depend, for example, on the
`material used for imaging layer 240.
`Where a positive-tone imaging material is used for imag
`ing layer 240, such as a suitable positive photoresist or a
`suitable positive-tone radiation-sensitive polyimide for
`example, imaging layer 240 may be exposed to radiation
`through a second mask having opaque features 242 and 244
`and clear features 241, 243, and 245 as illustrated in FIG. 4.
`The second mask may include any suitable pattern of opaque
`and clear features that may depend, for example. on the
`desired pattern to be formed in imaging layer 240.
`Imaging layer 240 may be exposed through the second
`mask using any suitable form of radiation. The radiation
`serves to render soluble in a suitable developer that portion
`of imaging layer 240 exposed to radiation through clear
`features 241, 243, and 245. That portion of imaging layer
`240 that has not been exposed to radiation remains relatively
`insoluble in the developer. As ?rst patterned layer 232 has
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`been stabilized, ?rst patterned layer 232 undergoes if any, chemical transformation as a result of any exposure
`
`to radiation for patterning imaging layer 240.
`Preferably, ?rst patterned layer 232 does not atfect in a
`material manner the lithographic patterning of imaging layer
`240. That is, ?rst patterned layer 232 preferably does not
`materially aifect the desired patterning of imaging layer 240,
`for example, by re?ecting any radiation. First patterned layer
`232 may be treated using any suitable processing technique,
`such as bleaching or baking for example. as necessary to
`avoid or minimize adverse effects by ?rst patterned layer
`232 in patterning imaging layer 240. For one embodiment,
`the material used for ?rst patterned layer 232 may match or
`substantially match the optical and mass properties, for
`example. of the material used for imaging layer 240 so as
`avoid or minimize any re?ection of radiation in patterning
`imaging layer 240.
`Imaging layer 240 may then be developed in a suitable
`developer to form a second patterned layer that includes
`features 251 and 253. As illustrated in FIG. 5, that portion
`of imaging layer 240 exposed to radiation through the
`second mask is soluble in the developer and is thus dissolved
`from imaging layer 240. That portion of imaging layer 240
`that has not been exposed to radiation is relatively insoluble
`in the developer, and thus remains to form features 251 and
`253 for the second patterned layer. As ?rst patterned layer
`232 has been stabilized, ?rst patterned layer 232 is relatively
`insoluble in developer and thus undergoes relatively
`minimal, if any, dissolution for the development of imaging
`layer 240.
`For other embodiments where a suitable negative-tone
`imaging material is used for imaging layer 240. the negative
`tone imaging layer 240 may be exposed to any suitable form
`of radiation through a suitable negative-tone mask having
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`opaque features 241, 243, and 245 and clear features 242 and
`244. for example. Negative-tone imaging materials may
`include a suitable negative photoresist. a suitable positive
`photoresist that is to be subjected to an image reversal
`process. or a suitable negative-tone radiation-sensitive poly
`imide for example. The negative-tone imaging layer 240
`may be developed in a suitable developer to form features
`251 and 253 for the second patterned layer as illustrated in
`FIG. 5. That portion of imaging layer 240 exposed to
`radiation through the second mask is relatively insoluble in
`the developer and thus remains to form features 251 and
`253. That portion of imaging layer 240 that has not been
`exposed to radiation is soluble in the developer and is thus
`dissolved from imaging layer 240.
`For one embodiment for the method of FIG. 1, a suitable
`positive photoresist may be used for both imaging layers 220
`and 240 while a suitable deep ultraviolet (DUV) stabiliza
`tion technique may be used to stabilize the positive photo
`resist for ?rst patterned layer 232. For another embodiment.
`a suitable negative photoresist may be used for both imaging
`layers 220 and 240.
`For a further embodiment for the method of FIG. 1,
`imaging layer 220 may include a suitable positive photore
`sist and may be exposed through a suitable negative-tone
`mask. Imaging layer 220 may then be subjected to a suitable
`image reversal process to form ?rst patterned layer 232. The
`image reversal process preferably serves to stabilize ?rst
`patterned layer 232. The photoresist of ?rst patterned layer
`232. however, may be subjected to a suitable stabilization
`technique such as a suitable DUV stabilization technique for
`example. as necessary to withstand dissolution by solvents
`during a subsequent spin-on of photoresist. Imaging layer
`240 for this embodiment may include any suitable material
`and may be patterned using any suitable lithographic pat
`terning technique to form the second patterned layer.
`As a result of the method of FIG. 1, a single patterned
`layer is formed over layer 210 as illustrated in FIG. 5. This
`single patterned layer is formed from the patterning of
`imaging layer 220 and the subsequent patterning of imaging
`layer 240.
`FIG. 6 illustrates. in ?ow diagram form, another lithog
`raphy method for semiconductor fabrication. For one
`embodiment, the method of FIG. 6 may be used for semi
`conductor fabrication using a semiconductor wafer, such as
`the semiconductor wafer illustrated in FIGS. 7, 8, 9, 10. and
`11 for example.
`For the method of a FIG. 6. a semiconductor substrate 400
`is provided as illustrated in FIG. 7. Substrate 400 may
`include any suitable semiconductor material, including sili
`con (Si) for example.
`As illustrated in FIG. 7. a layer 410 may be formed over
`substrate 400. Layer 410 may include any suitable material
`and may be formed to any suitable thickness using any
`suitable