`Technical Reference
`Manual
`
`Cypress Semiconductor
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`EZ-USB FX2 Technical Reference Manual,
`Version 2.1.
`
`Copyright © 2000, 2001
`Cypress Semiconductor Corporation.
`
`All rights reserved.
`
`List of Trademarks
`
`Cypress, the Cypress Logo, EZ-USB, Making USB Universal, Xcelerator, and ReNumeration are
`trademarks or registered trademarks of Cypress Semiconductor Corporation. Macintosh is a regis-
`tered trademark of Apple Computer, Inc. Windows is a registered trademark of Microsoft Corpora-
`tion. I²C is a registered trademark of Philips Electronics. All other product or company names used
`in this manual may be trademarks, registered trademarks, or servicemarks of their respective own-
`ers.
`
`Exhibit 2058 - Page 02 of 460
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`Table of Contents
`
`Chapter 1. Introducing EZ-USB FX2
` 1.1 Introduction....................................................................................................................................1-1
` 1.2 An Introduction to USB..................................................................................................................1-1
` 1.3 The USB Specification ..................................................................................................................1-2
` 1.4 Host Is Master ...............................................................................................................................1-3
` 1.5 USB Direction................................................................................................................................1-3
` 1.6 Tokens and PIDs...........................................................................................................................1-3
` 1.6.1 Receiving Data from the Host..........................................................................................1-5
` 1.6.2 Sending Data to the Host.................................................................................................1-5
` 1.7 USB Frames..................................................................................................................................1-5
` 1.8 USB Transfer Types......................................................................................................................1-6
` 1.8.1 Bulk Transfers..................................................................................................................1-6
` 1.8.2 Interrupt Transfers ...........................................................................................................1-6
` 1.8.3 Isochronous Transfers .....................................................................................................1-7
` 1.8.4 Control Transfers............................................................................................................1-7
` 1.9 Enumeration ..................................................................................................................................1-8
` 1.9.1 Full-Speed / High-Speed Detection .................................................................................1-8
` 1.10 The Serial Interface Engine (SIE)................................................................................................1-9
` 1.11 ReNumeration™........................................................................................................................1-10
` 1.12 EZ-USB FX2 Architecture .........................................................................................................1-11
` 1.13 FX2 Feature Summary ..............................................................................................................1-13
` 1.14 FX2 Integrated Microprocessor .................................................................................................1-13
` 1.15 FX2 Block Diagram ...................................................................................................................1-15
` 1.16 Packages...................................................................................................................................1-16
` 1.16.1 56-Pin Package ...........................................................................................................1-16
` 1.16.2 100-Pin Package .........................................................................................................1-17
` 1.16.3 128-Pin Package .........................................................................................................1-17
` 1.16.4 Signals Available in the Three Packages ....................................................................1-17
` 1.17 Package Diagrams ....................................................................................................................1-20
` 1.18 FX2 Endpoint Buffers ................................................................................................................1-23
` 1.19 External FIFO Interface .............................................................................................................1-25
` 1.20 EZ-USB FX2 Product Family....................................................................................................1-28
`
`Chapter 2. Endpoint Zero
` 2.1 Introduction....................................................................................................................................2-1
` 2.2 Control Endpoint EP0....................................................................................................................2-2
` 2.3 USB Requests...............................................................................................................................2-5
` 2.3.1 Get Status........................................................................................................................2-7
` 2.3.2 Set Feature ....................................................................................................................2-10
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` 2.3.3 Clear Feature .................................................................................................................2-11
` 2.3.4 Get Descriptor ...............................................................................................................2-12
`2.3.4.1 Get Descriptor-Device........................................................................................2-14
`2.3.4.2 Get Descriptor-Device Qualifier .........................................................................2-15
`2.3.4.3 Get Descriptor-Configuration .............................................................................2-15
`2.3.4.4 Get Descriptor-String .........................................................................................2-16
`2.3.4.5 Get Descriptor-Other Speed Configuration........................................................2-16
` 2.3.5 Set Descriptor................................................................................................................2-17
`2.3.5.1 Set Configuration ...............................................................................................2-20
` 2.3.6 Get Configuration ..........................................................................................................2-20
` 2.3.7 Set Interface ..................................................................................................................2-21
` 2.3.8 Get Interface..................................................................................................................2-22
` 2.3.9 Set Address ...................................................................................................................2-22
` 2.3.10 Sync Frame .................................................................................................................2-23
` 2.3.11 Firmware Load.............................................................................................................2-24
`
`Chapter 3. Enumeration and ReNumeration™
` 3.1 Introduction ...................................................................................................................................3-1
` 3.2 FX2 Startup Modes .......................................................................................................................3-1
` 3.3 The Default USB Device ..............................................................................................................3-3
` 3.4 EEPROM Boot-load Data Formats ...............................................................................................3-4
` 3.4.1 No EEPROM or Invalid EEPROM...................................................................................3-4
` 3.4.2 Serial EEPROM Present, First Byte is 0xC0 ...................................................................3-5
` 3.4.3 Serial EEPROM Present, First Byte is 0xC2 ...................................................................3-6
` 3.5 EEPROM Configuration Byte ........................................................................................................3-8
` 3.6 The RENUM Bit.............................................................................................................................3-9
` 3.7 FX2 Response to Device Requests (RENUM=0)........................................................................3-10
` 3.8 FX2 Vendor Request for Firmware Load ....................................................................................3-11
` 3.9 How the Firmware ReNumerates................................................................................................3-12
` 3.10 Multiple ReNumerations™ ........................................................................................................3-12
`
`Chapter 4. Interrupts
` 4.1 Introduction ...................................................................................................................................4-1
` 4.2 SFRs .............................................................................................................................................4-2
` 4.2.1 803x/805x Compatibility ..................................................................................................4-5
` 4.3 Interrupt Processing ......................................................................................................................4-6
` 4.3.1 Interrupt Masking.............................................................................................................4-6
`4.3.1.1 Interrupt Priorities.................................................................................................4-7
` 4.3.2 Interrupt Sampling ...........................................................................................................4-8
` 4.3.3 Interrupt Latency..............................................................................................................4-8
` 4.4 USB-Specific Interrupts.................................................................................................................4-8
` 4.4.1 Resume Interrupt.............................................................................................................4-8
` 4.4.2 USB Interrupts.................................................................................................................4-9
`4.4.2.1 SUTOK, SUDAV Interrupts ................................................................................4-12
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`4.4.2.2 SOF Interrupt .....................................................................................................4-13
`4.4.2.3 Suspend Interrupt...............................................................................................4-13
`4.4.2.4 USB RESET Interrupt ........................................................................................4-13
`4.4.2.5 HISPEED Interrupt.............................................................................................4-13
`4.4.2.6 EP0ACK Interrupt...............................................................................................4-13
`4.4.2.7 Endpoint Interrupts.............................................................................................4-14
`4.4.2.8 In-Bulk-NAK (IBN) Interrupt................................................................................4-14
`4.4.2.9 EPxPING Interrupt .............................................................................................4-14
`4.4.2.10 ERRLIMIT Interrupt ..........................................................................................4-15
`4.4.2.11 EPxISOERR Interrupt ......................................................................................4-15
` 4.5 USB-Interrupt Autovectors ..........................................................................................................4-15
` 4.5.1 USB Autovector Coding .................................................................................................4-17
` 4.6 I²C-Compatible Bus Interrupt.......................................................................................................4-18
` 4.7 FIFO/GPIF Interrupt (INT4) .........................................................................................................4-19
` 4.8 FIFO/GPIF-Interrupt Autovectors ................................................................................................4-20
` 4.8.1 FIFO/GPIF Autovector Coding.......................................................................................4-21
`
`Chapter 5. Memory
` 5.1 Introduction....................................................................................................................................5-1
` 5.2 Internal Data RAM.........................................................................................................................5-1
` 5.2.1 The Lower 128.................................................................................................................5-2
` 5.2.2 The Upper 128.................................................................................................................5-2
` 5.2.3 SFR (Special Function Register) Space ..........................................................................5-2
` 5.3 External Program Memory and External Data Memory.................................................................5-3
` 5.3.1 56- and 100-pin FX2 ........................................................................................................5-4
` 5.3.2 128-pin FX2 .....................................................................................................................5-4
` 5.4 FX2 Memory Maps ........................................................................................................................5-5
` 5.5 “Von-Neumannizing” Off-Chip Program and Data Memory...........................................................5-8
` 5.6 On-Chip Data Memory at 0xE000-0xFFFF ...................................................................................5-9
`
`Chapter 6. Power Management
` 6.1 Introduction....................................................................................................................................6-1
` 6.2 USB Suspend................................................................................................................................6-3
` 6.2.1 SUSPEND Register .........................................................................................................6-4
` 6.3 Wakeup/Resume...........................................................................................................................6-4
` 6.3.1 Wakeup Interrupt .............................................................................................................6-5
` 6.4 USB Resume (Remote Wakeup) ..................................................................................................6-6
` 6.4.1 WU2 Pin...........................................................................................................................6-6
`
`Chapter 7. Resets
` 7.1 Introduction....................................................................................................................................7-1
` 7.2 Power-On Reset (POR).................................................................................................................7-2
` 7.3 Releasing the CPU Reset .............................................................................................................7-3
` 7.3.1 RAM Download................................................................................................................7-3
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` 7.3.2 EEPROM Load ................................................................................................................7-3
` 7.3.3 External ROM ..................................................................................................................7-3
` 7.4 CPU Reset Effects ........................................................................................................................7-4
` 7.5 USB Bus Reset .............................................................................................................................7-4
` 7.6 FX2 Disconnect.............................................................................................................................7-5
` 7.7 Reset Summary ...........................................................................................................................7-5
`
`Chapter 8. Access to Endpoint Buffers
` 8.1 Introduction ...................................................................................................................................8-1
` 8.2 FX2 Large and Small Endpoints ...................................................................................................8-1
` 8.3 High-Speed and Full-Speed Differences.......................................................................................8-2
` 8.4 How the CPU Configures the Endpoints .......................................................................................8-3
` 8.5 CPU Access to FX2 Endpoint Data...............................................................................................8-4
` 8.6 CPU Control of FX2 Endpoints .....................................................................................................8-5
` 8.6.1 Registers That Control EP0, EP1IN, and EP1OUT.........................................................8-5
`8.6.1.1 EP0CS .................................................................................................................8-5
`8.6.1.2 EP0BCH and EP0BCL.........................................................................................8-7
`8.6.1.3 USBIE, USBIRQ ..................................................................................................8-7
`8.6.1.4 EP01STAT ...........................................................................................................8-8
`8.6.1.5 EP1OUTCS..........................................................................................................8-8
`8.6.1.6 EP1OUTBC..........................................................................................................8-9
`8.6.1.7 EP1INCS..............................................................................................................8-9
`8.6.1.8 EP1INBC..............................................................................................................8-9
` 8.6.2 Registers That Control EP2, EP4, EP6, EP8................................................................8-10
`8.6.2.1 EP2468STAT .....................................................................................................8-10
`8.6.2.2 EP2ISOINPKTS, EP4ISOINPKTS, EP6ISOINPKTS, EP8ISOINPKTS .............8-10
`8.6.2.3 EP2CS, EP4CS, EP6CS, EP8CS......................................................................8-11
`8.6.2.4 EP2BCH:L, EP4BCH:L, EP6BCH:L, EP8BCH:L................................................8-12
` 8.6.3 Registers That Control All Endpoints.............................................................................8-13
`8.6.3.1 IBNIE, IBNIRQ, NAKIE, NAKIRQ.......................................................................8-14
`8.6.3.2 EPIE, EPIRQ......................................................................................................8-15
`8.6.3.3 USBERRIE, USBERRIRQ, ERRCNTLIM, CLRERRCNT..................................8-16
`8.6.3.4 TOGCTL ............................................................................................................8-16
` 8.7 The Setup Data Pointer...............................................................................................................8-17
` 8.7.1 Transfer Length .............................................................................................................8-19
` 8.7.2 Accessible Memory Spaces ..........................................................................................8-19
` 8.8 Autopointers ................................................................................................................................8-19
`
`Chapter 9. Slave FIFOs
` 9.1 Introduction ...................................................................................................................................9-1
` 9.2 Hardware.......................................................................................................................................9-2
` 9.2.1 Slave FIFO Pins ..............................................................................................................9-3
` 9.2.2 FIFO Data Bus (FD) ........................................................................................................9-4
` 9.2.3 Interface Clock (IFCLK) ...................................................................................................9-5
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` 9.2.4 FIFO Flag Pins (FLAGA, FLAGB, FLAGC, FLAGD)........................................................9-6
` 9.2.5 Control Pins (SLOE, SLRD, SLWR, PKTEND, FIFOADR[1:0]).......................................9-8
` 9.2.6 Slave FIFO Chip Select (SLCS) ....................................................................................9-10
` 9.2.7 Implementing Synchronous Slave FIFO Writes.............................................................9-10
` 9.2.8 Implementing Synchronous Slave FIFO Reads.............................................................9-13
` 9.2.9 Implementing Asynchronous Slave FIFO Writes ...........................................................9-15
` 9.2.10 Implementing Asynchronous Slave FIFO Reads .........................................................9-17
` 9.3 Firmware .....................................................................................................................................9-19
` 9.3.1 Firmware FIFO Access ..................................................................................................9-19
` 9.3.2 EPx Memories ...............................................................................................................9-20
` 9.3.3 Slave FIFO Programmable-Level Flag (PF) ..................................................................9-21
` 9.3.4 Auto-In / Auto-Out Modes..............................................................................................9-22
` 9.3.5 CPU Access to OUT Packets, AUTOOUT = 1...............................................................9-23
` 9.3.6 CPU Access to OUT Packets, AUTOOUT = 0...............................................................9-24
` 9.3.7 CPU Access to IN Packets, AUTOIN = 1.......................................................................9-27
` 9.3.8 Access to IN Packets, AUTOIN=0 .................................................................................9-30
` 9.3.9 Auto-In / Auto-Out Initialization......................................................................................9-31
` 9.3.10 Auto-Mode Example: Synchronous FIFO IN Data Transfers.......................................9-32
` 9.3.11 Auto-Mode Example: Asynchronous FIFO IN Data Transfers .....................................9-33
` 9.4 Switching Between Manual-Out and Auto-Out...........................................................................9-33
`
`Chapter 10. General Programmable Interface (GPIF)
` 10.1 Introduction................................................................................................................................10-1
` 10.1.1 Typical GPIF Interface .................................................................................................10-3
` 10.2 Hardware...................................................................................................................................10-5
` 10.2.1 The External GPIF Interface........................................................................................10-5
` 10.2.2 Default GPIF Pins Configuration..................................................................................10-6
` 10.2.3 Six Control OUT Signals..............................................................................................10-7
`10.2.3.1 Control Output Modes ......................................................................................10-7
` 10.2.4 Six Ready IN signals....................................................................................................10-7
` 10.2.5 Nine GPIF Address OUT signals .................................................................................10-7
` 10.2.6 Three GSTATE OUT signals .......................................................................................10-8
` 10.2.7 8/16-Bit Data Path, WORDWIDE = 1 (default) and WORDWIDE = 0 .........................10-8
` 10.2.8 Byte Order for 16-bit GPIF Transactions .....................................................................10-8
` 10.2.9 Interface Clock (IFCLK) ...............................................................................................10-8
` 10.2.10 Connecting GPIF Signal Pins to Hardware..............................................................10-10
` 10.2.11 Example GPIF Hardware Interconnect....................................................................10-10
` 10.3 Programming the GPIF Waveforms ........................................................................................10-11
` 10.3.1 The GPIF Registers ...................................................................................................10-12
` 10.3.2 Programming GPIF Waveforms.................................................................................10-12
`10.3.2.1 The GPIF IDLE State .....................................................................................10-12
`10.3.2.1.1 GPIF Data Bus During IDLE.............................................................10-13
`10.3.2.1.2 CTL Outputs During IDLE..................................................................10-13
`10.3.2.2 Defining States...............................................................................................10-14
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`10.3.2.2.1 Non-Decision Point (NDP) States......................................................10-14
`10.3.2.2.2 Decision Point (DP) States................................................................10-16
` 10.3.3 Re-Executing a Task Within a DP State ....................................................................10-18
` 10.3.4 State Instructions.......................................................................................................10-21
`10.3.4.1 Structure of the Waveform Descriptors ..........................................................10-25
` 10.4 Firmware .................................................................................................................................10-26
` 10.4.1 Single-Read Transactions .........................................................................................10-33
` 10.4.2 Single-Write Transactions .........................................................................................10-38
` 10.4.3 FIFO-Read and FIFO-Write Transactions .................................................................10-41
`10.4.3.1 Transaction Counter ......................................................................................10-41
`10.4.3.2 Reading the Transaction-Count Status in a DP State....................................10-42
` 10.4.4 GPIF Flag Selection ..................................................................................................10-42
` 10.4.5 GPIF Flag Stop..........................................................................................................10-42
`10.4.5.1 Performing a FIFO-Read Transaction............................................................10-43
` 10.4.6 Firmware Access to IN packet(s), (AUTOIN=1).........................................................10-48
` 10.4.7 Firmware Access to IN Packet(s), (AUTOIN = 0) ......................................................10-49
`10.4.7.1 Performing a FIFO-Write Transaction ............................................................10-52
` 10.4.8 Firmware access to OUT packets, (AUTOOUT=1) ...................................................10-56
` 10.4.9 Firmware access to OUT packets, (AUTOOUT = 0) .................................................10-57
` 10.4.10 Burst FIFO Transactions .........................................................................................10-59
` 10.5 UDMA Interface.......................................................................................................................10-63
`
`Chapter 11. CPU Introduction
` 11.1 Introduction ...............................................................................................................................11-1
` 11.2 8051 Enhancements .................................................................................................................11-2
` 11.3 Performance Overview..............................................................................................................11-3
` 11.4 Software Compatibility ..............................................................................................................11-4
` 11.5 803x/805x Feature Comparison...................................................................................