CY7C68013A, CY7C68014A
`CY7C68015A, CY7C68016A
`EZ-USB® FX2LP™ USB Microcontroller
` High-Speed USB Peripheral Controller
`
`EZ-USB FX2LP™ USB Microcontroller High Speed USB Peripheral Controller
`
`Features
`■ USB 2.0 USB IF high speed certified (TID # 40460272)
`■ Single chip integrated USB 2.0 transceiver, smart SIE, and
`enhanced 8051 microprocessor
`■ Fit, form, and function compatible with the FX2
`❐ Pin compatible
`❐ Object code compatible
`❐ Functionally compatible (FX2LP is a superset)
`■ Ultra low power: ICC No more than 85 mA in any mode
`❐ Ideal for bus and battery powered applications
`■ Software: 8051 code runs from:
`❐ Internal RAM, which is downloaded through USB
`❐ Internal RAM, which is loaded from EEPROM
`❐ External memory device (128 pin package)
`■ 16 KB of on-chip code/data RAM
`■ Four programmable BULK, INTERRUPT, and
`ISOCHRONOUS endpoints
`❐ Buffering options: Double, triple, and quad
`■ Additional programmable (BULK/INTERRUPT) 64-byte
`endpoint
`■ 8-bit or 16-bit external data interface
`■ Smart media standard ECC generation
`■ GPIF (general programmable interface)
`❐ Enables direct connection to most parallel interfaces
`❐ Programmable waveform descriptors and configuration
`registers to define waveforms
`❐ Supports multiple ready (RDY) inputs and Control (CTL)
`outputs
`■ Integrated, industry standard enhanced 8051
`❐ 48 MHz, 24 MHz, or 12 MHz CPU operation
`❐ Four clocks per instruction cycle
`❐ Two USARTs
`❐ Three counter/timers
`❐ Expanded interrupt system
`❐ Two data pointers
`
`■ 3.3 V operation with 5 V tolerant inputs
`■ Vectored USB interrupts and GPIF/FIFO interrupts
`■ Separate data buffers for the setup and data portions of a
`CONTROL transfer
`■ Integrated I2C controller, runs at 100 or 400 kHz
`■ Four integrated FIFOs
`❐ Integrated glue logic and FIFOs lower system cost
`❐ Automatic conversion to and from 16-bit buses
`❐ Master or slave operation
`❐ Uses external clock or asynchronous strobes
`❐ Easy interface to ASIC and DSP ICs
`■ Available in commercial and industrial temperature grade
`(all packages except VFBGA)
`Features (CY7C68013A/14A only)
`■ CY7C68014A: Ideal for Battery Powered Applications
`❐ Suspend current: 100 A (typ)
`■ CY7C68013A: Ideal for Non Battery Powered Applications
`❐ Suspend current: 300 A (typ)
`■ Available in Five Pb-free Packages with Up to 40 GPIOs
`❐ 128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin
`QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin
`VFBGA (24 GPIOs)
`Features (CY7C68015A/16A only)
`■ CY7C68016A: Ideal for Battery Powered Applications
`❐ Suspend current: 100 A (typ)
`■ CY7C68015A: Ideal for Non Battery Powered Applications
`❐ Suspend current: 300 A (typ)
`■ Available in Pb-free 56-pin QFN Package (26 GPIOs)
`■ Two more GPIOs than CY7C68013A/14A enabling additional
`features in same footprint
`
`Errata: For information on silicon errata, see “Errata” on page 64. Details include trigger conditions, devices affected, and proposed workaround.
`
`Cypress Semiconductor Corporation
`Document Number: 38-08032 Rev. *W
`
`•
`
`198 Champion Court
`
`•
`
`San Jose, CA 95134-1709
`
`408-943-2600
`•
` Revised July 19, 2013
`
`Exhibit 2035 - Page 01 of 68
`
`

`

`CY7C68013A, CY7C68014A
`CY7C68015A, CY7C68016A
`
`Abundant I/O
`including two USARTs
`
`General
`programmable I/F
`to ASIC/DSP or bus
`standards such as
`ATAPI, EPP, etc.
`
`I2C
`Master
`
`Additional I/Os (24)
`
`GPIF
`
`ADDR (9)
`
`RDY (6)
`CTL (6)
`
`ECC
`
`Data (8)
`
`Address (16) / Data Bus (8)
`
`4 kB
`FIFO
`
`8/16
`
`Up to 96 MBytes/s
`burst rate
`
`Logic Block Diagram
`
`24 MHz
`Ext. XTAL
`
`High performance micro
`using standard tools
`with lower-power options
`
`Address (16)
`
`8051 Core
`12/24/48 MHz,
`four clocks/cycle
`
`FX2LP
`
`VCC
`
`x20
`PLL
`
`/0.5
`/1.0
`/2.0
`
`1.5k
`connected for
`full speed
`
`D+
`
`D–
`
`USB
`2.0
`XCVR
`
`Integrated
`full speed and
`high speed
`XCVR
`
`16 KB
`RAM
`
`CY
`Smart
`USB
`1.1/2.0
`Engine
`
`Enhanced USB core
`Simplifies 8051 code
`
`“Soft Configuration”
`Easy firmware changes
`
`FIFO and endpoint memory
`(master or slave operation)
`
`Cypress’s EZ-USB® FX2LP (CY7C68013A/14A) is a low
`power version of the EZ-USB FX2(CY7C68013), which is a
`highly integrated, low power USB 2.0 microcontroller. By
`integrating the USB 2.0 transceiver, serial interface engine (SIE),
`enhanced 8051 microcontroller, and a programmable peripheral
`interface in a single chip,
`Cypress has created a cost effective solution that provides
`superior time-to-market advantages with low power to enable
`bus powered applications.
`The ingenious architecture of FX2LP results in data transfer
`rates of over 53 Mbytes per second, the maximum allowable
`USB 2.0 bandwidth, while still using a low cost 8051
`microcontroller in a package as small as a 56 VFBGA (5 mm x 5
`mm). Because it incorporates the USB 2.0 transceiver, the
`FX2LP is more economical, providing a smaller footprint solution
`
`than USB 2.0 SIE or external transceiver implementations. With
`EZ-USB FX2LP, the Cypress Smart SIE handles most of the
`USB 1.1 and 2.0 protocol in hardware, freeing the embedded
`microcontroller for application specific functions and decreasing
`development time to ensure USB compatibility.
`The General Programmable Interface (GPIF) and Master/Slave
`Endpoint FIFO (8-bit or 16-bit data bus) provides an easy and
`glueless interface to popular interfaces such as ATA, UTOPIA,
`EPP, PCMCIA, and most DSP/processors.
`The FX2LP draws less current than the FX2 (CY7C68013), has
`double the on-chip code/data RAM, and is fit, form and function
`compatible with the 56, 100, and 128 pin FX2.
`Five packages are defined for the family: 56 VFBGA, 56 SSOP,
`56 QFN, 100 TQFP, and 128 TQFP.
`
`Document Number: 38-08032 Rev. *W
`
`Page 2 of 68
`
`Exhibit 2035 - Page 02 of 68
`
`

`

`Contents
`Applications ......................................................................4
`Functional Overview ........................................................4
`USB Signaling Speed ..................................................4
`8051 Microprocessor ...................................................4
`I2C Bus ........................................................................4
`Buses ..........................................................................4
`USB Boot Methods ......................................................5
`ReNumeration .............................................................5
`Bus-Powered Applications ..........................................5
`Interrupt System ..........................................................5
`Reset and Wakeup ......................................................7
`Program/Data RAM .....................................................8
`Register Addresses ...................................................10
`Endpoint RAM ...........................................................11
`External FIFO Interface .............................................12
`GPIF ..........................................................................13
`ECC Generation[7] ................................................................... 13
`USB Uploads and Downloads ...................................13
`Autopointer Access ...................................................13
`I2C Controller .............................................................14
`Compatible with Previous Generation EZ-USB FX2 .14
`CY7C68013A/14A and CY7C68015A/16A Differences 14
`Pin Assignments ............................................................15
`CY7C68013A/15A Pin Descriptions ..........................22
`Register Summary ..........................................................30
`Absolute Maximum Ratings ..........................................37
`Operating Conditions .....................................................37
`Thermal Characteristics .................................................37
`DC Characteristics .........................................................38
`USB Transceiver .......................................................38
`AC Electrical Characteristics ........................................39
`USB Transceiver .......................................................39
`Program Memory Read .............................................39
`Data Memory Read ...................................................40
`Data Memory Write ...................................................41
`
`CY7C68013A, CY7C68014A
`CY7C68015A, CY7C68016A
`
`PORTC Strobe Feature Timings ............................... 42
`GPIF Synchronous Signals ....................................... 43
`Slave FIFO Synchronous Read ................................. 44
`Slave FIFO Asynchronous Read ............................... 45
`Slave FIFO Synchronous Write ................................. 46
`Slave FIFO Asynchronous Write ............................... 47
`Slave FIFO Synchronous Packet End Strobe ........... 47
`Slave FIFO Asynchronous Packet End Strobe ......... 48
`Slave FIFO Output Enable ........................................ 49
`Slave FIFO Address to Flags/Data ............................ 49
`Slave FIFO Synchronous Address ............................ 49
`Slave FIFO Asynchronous Address .......................... 50
`Sequence Diagram .................................................... 50
`Ordering Information ...................................................... 55
`Ordering Code Definitions ......................................... 55
`Package Diagrams .......................................................... 56
`PCB Layout Recommendations .................................... 61
`Quad Flat Package No Leads (QFN) Package
`Design Notes ................................................................... 62
`Acronyms ..........................................................................63
`Document Conventions ...................................................63
`Units of Measure ....................................................... 63
`Errata ............................................................................... 64
`Part Numbers Affected .............................................. 64
`CY7C68013A/14A/15A/16A Qualification Status ...... 64
`CY7C68013A/14A/15A/16A Errata Summary ........... 64
`Document History Page ................................................. 65
`Sales, Solutions, and Legal Information ...................... 68
`Worldwide Sales and Design Support ....................... 68
`Products .................................................................... 68
`PSoC® Solutions ...................................................... 68
`Cypress Developer Community ................................. 68
`Technical Support ..................................................... 68
`
`Document Number: 38-08032 Rev. *W
`
`Page 3 of 68
`
`Exhibit 2035 - Page 03 of 68
`
`

`

`CY7C68013A, CY7C68014A
`CY7C68015A, CY7C68016A
`
`Figure 2-1. Crystal Configuration
`24 MHz
`
`C1
`
`C2
`
`12 pf
`
`12 pf
`
`20 × PLL
`
`12 pF capacitor values assumes a trace capacitance
`of 3 pF per side on a four-layer FR4 PCA
`
`The CLKOUT pin, which can be three-stated and inverted using
`internal control bits, outputs the 50% duty cycle 8051 clock, at
`the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz.
`
`2.2.2 USARTs
`FX2LP contains two standard 8051 USARTs, addressed through
`Special Function Register (SFR) bits. The USART interface pins
`are available on separate I/O pins, and are not multiplexed with
`port pins.
`UART0 and UART1 can operate using an internal clock at
`230 KBaud with no more than 1% baud rate error. 230 KBaud
`operation is achieved by an internally derived clock source that
`generates overflow pulses at the appropriate time. The internal
`clock adjusts for the 8051 clock rate (48 MHz, 24 MHz, and
`12 MHz) such that it always presents the correct frequency for
`230 KBaud operation.[1]
`2.2.3 Special Function Registers
`Certain 8051 SFR addresses are populated to provide fast
`access to critical FX2LP functions. These SFR additions are
`shown in Table 1 on page 5. Bold type indicates non standard,
`enhanced 8051 registers. The two SFR rows that end with “0”
`and “8” contain bit addressable registers. The four I/O ports A to
`D use the SFR addresses used in the standard 8051 for ports 0
`to 3, which are not implemented in FX2LP. Because of the faster
`and more efficient SFR addressing, the FX2LP I/O ports are not
`addressable in external RAM space (using the MOVX
`instruction).
`2.3 I2C Bus
`FX2LP supports the I2C bus as a master only at 100/400 KHz.
`SCL and SDA pins have open-drain outputs and hysteresis
`inputs. These signals must be pulled up to 3.3V, even if no I2C
`device is connected.
`2.4 Buses
`All packages, 8-bit or 16-bit “FIFO” bidirectional data bus,
`multiplexed on I/O ports B and D. 128-pin package: adds 16-bit
`output-only 8051 address bus, 8-bit bidirectional data bus.
`
`1. Applications
`■ Portable video recorder
`■ MPEG/TV conversion
`■ DSL modems
`■ ATA interface
`■ Memory card readers
`■ Legacy conversion devices
`■ Cameras
`■ Scanners
`■ Wireless LAN
`■ MP3 players
`■ Networking
`The “Reference Designs” section of the Cypress web site
`provides additional tools for typical USB 2.0 applications. Each
`reference design comes complete with firmware source and
`object code, schematics, and documentation. Visit
`www.cypress.com for more information.
`2. Functional Overview
`2.1 USB Signaling Speed
`FX2LP operates at two of the three rates defined in the USB
`Specification Revision 2.0, dated April 27, 2000:
`■ Full speed, with a signaling bit rate of 12 Mbps
`■ High speed, with a signaling bit rate of 480 Mbps
`FX2LP does not support the low speed signaling mode of
`1.5 Mbps.
`2.2 8051 Microprocessor
`The 8051 microprocessor embedded in the FX2LP family has
`256 bytes of register RAM, an expanded interrupt system, three
`timer/counters, and two USARTs.
`
`2.2.1 8051 Clock Frequency
`FX2LP has an on-chip oscillator circuit that uses an external
`24 MHz (±100 ppm) crystal with the following characteristics:
`■ Parallel resonant
`■ Fundamental mode
`■ 500 W drive level
`■ 12 pF (5% tolerance) load capacitors
`An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz,
`as required by the transceiver/PHY and internal counters divide
`it down for use as the 8051 clock. The default 8051 clock
`frequency is 12 MHz. The clock frequency of the 8051 can be
`changed by the 8051 through the CPUCS register, dynamically.
`
`Note
`1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0, UART1, or both respectively.
`
`Document Number: 38-08032 Rev. *W
`
`Page 4 of 68
`
`Exhibit 2035 - Page 04 of 68
`
`

`

`CY7C68013A, CY7C68014A
`CY7C68015A, CY7C68016A
`
`Table 1. Special Function Registers
`x
`8x
`9x
`IOA
`IOB
`0
`EXIF
`1
`SP
`MPAGE
`2
`DPL0
`3
`DPH0
`–
`DPL1
`4
`–
`DPH1
`5
`–
`DPS
`6
`–
`7
`PCON
`–
`8
`TCON
`SCON0
`9
`TMOD
`SBUF0
`AUTOPTRH1
`A
`TL0
`AUTOPTRL1
`B
`TL1
`reserved
`C
`TH0
`AUTOPTRH2
`D
`TH1
`CKCON
`AUTOPTRL2
`E
`reserved
`F
`–
`
`Bx
`IOD
`IOE
`OEA
`OEB
`OEC
`OED
`OEE
`–
`IP
`–
`EP01STAT
`GPIFTRIG
`
`Ax
`IOC
`INT2CLR
`INT4CLR
`–
`–
`–
`–
`–
`IE
`–
`EP2468STAT
`EP24FIFOFLGS
`EP68FIFOFLGS
`GPIFSGLDATH
`–
`GPIFSGLDATLX
`–
`AUTOPTRSET-UP GPIFSGLDATLNOX
`
`Cx
`SCON1
`SBUF1
`–
`–
`–
`–
`–
`–
`T2CON
`–
`RCAP2L
`RCAP2H
`TL2
`TH2
`–
`–
`
`Ex
`Dx
`PSW ACC
`–
`–
`–
`–
`–
`–
`–
`–
`–
`–
`–
`–
`–
`–
`EICON
`EIE
`–
`–
`–
`–
`–
`–
`–
`–
`–
`–
`–
`–
`–
`–
`
`Fx
`B
`–
`–
`–
`–
`–
`–
`–
`EIP
`–
`–
`–
`–
`–
`–
`–
`
`2.5 USB Boot Methods
`During the power up sequence, internal logic checks the I2C port
`for the connection of an EEPROM whose first byte is either 0xC0
`or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM
`in place of the internally stored values (0xC0), or it boot-loads the
`EEPROM contents into internal RAM (0xC2). If no EEPROM is
`detected, FX2LP enumerates using internally stored descriptors.
`The default ID values for FX2LP are VID/PID/DID (0x04B4,
`0x8613, 0xAxxx where xxx = Chip revision).[2]
`Table 2. Default ID Values for FX2LP
`Default VID/PID/DID
`0x04B4 Cypress Semiconductor
`0x8613 EZ-USB FX2LP
`0xAnnn Depends on chip revision
`(nnn = chip revision where first
`silicon = 001)
`
`Vendor ID
`Product ID
`Device release
`
`2.6 ReNumeration
`Because the FX2LP’s configuration is soft, one chip can take on
`the identities of multiple distinct USB devices.
`When first plugged into USB, the FX2LP enumerates
`automatically and downloads firmware and USB descriptor
`tables over the USB cable. Next, the FX2LP enumerates again,
`this time as a device defined by the downloaded information.
`This patented two step process called ReNumeration happens
`instantly when the device is plugged in, without a hint that the
`initial download step has occurred.
`
`Two control bits in the USBCS (USB Control and Status) register,
`control the ReNumeration process: DISCON and RENUM. To
`simulate a USB disconnect, the firmware sets DISCON to 1. To
`reconnect, the firmware clears DISCON to 0.
`Before reconnecting, the firmware sets or clears the RENUM bit
`to indicate whether the firmware or the Default USB Device
`handles device requests over endpoint zero: if RENUM = 0, the
`Default USB Device handles device requests; if RENUM = 1, the
`firmware services the requests.
`2.7 Bus-Powered Applications
`The FX2LP fully supports bus powered designs by enumerating
`with less than 100 mA as required by the USB 2.0 specification.
`2.8 Interrupt System
`2.8.1 INT2 Interrupt Request and Enable Registers
`FX2LP implements an autovector feature for INT2 and INT4.
`There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF)
`vectors. See EZ-USB Technical Reference Manual (TRM) for
`more details.
`
`2.8.2 USB Interrupt Autovectors
`The main USB interrupt is shared by 27 interrupt sources. To
`save the code and processing time that is required to identify the
`individual USB interrupt source, the FX2LP provides a second
`level of interrupt vectoring, called Autovectoring. When a USB
`interrupt is asserted, the FX2LP pushes the program counter to
`its stack, and then jumps to the address 0x0043 where it expects
`to find a “jump” instruction to the USB Interrupt service routine.
`
`Note
`2. The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
`
`Document Number: 38-08032 Rev. *W
`
`Page 5 of 68
`
`Exhibit 2035 - Page 05 of 68
`
`

`

`USB INTERRUPT TABLE FOR INT2
`Source
`SUDAV
`SOF
`SUTOK
`SUSPEND
`USB RESET
`HISPEED
`EP0ACK
`
`CY7C68013A, CY7C68014A
`CY7C68015A, CY7C68016A
`
`Notes
`
`Setup data available
`Start of frame (or microframe)
`Setup token received
`USB suspend request
`Bus reset
`Entered high speed operation
`FX2LP ACK’d the CONTROL Handshake
`reserved
`EP0-IN ready to be loaded with data
`EP0-OUT has USB data
`EP1-IN ready to be loaded with data
`EP1-OUT has USB data
`IN: buffer available. OUT: buffer has data
`IN: buffer available. OUT: buffer has data
`IN: buffer available. OUT: buffer has data
`IN: buffer available. OUT: buffer has data
`IN-Bulk-NAK (any IN endpoint)
`reserved
`EP0 OUT was pinged and it NAK’d
`EP1 OUT was pinged and it NAK’d
`EP2 OUT was pinged and it NAK’d
`EP4 OUT was pinged and it NAK’d
`EP6 OUT was pinged and it NAK’d
`EP8 OUT was pinged and it NAK’d
`Bus errors exceeded the programmed limit
`–
`Reserved
`Reserved
`ISO EP2 OUT PID sequence error
`ISO EP4 OUT PID sequence error
`ISO EP6 OUT PID sequence error
`ISO EP8 OUT PID sequence error
`
`The FX2LP jump instruction is encoded as follows:
`Table 3. INT2 USB Interrupts
`
`Priority
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`
`INT2VEC Value
` 00
` 04
` 08
`0C
`10
`14
`18
`1C
`20
`24
`28
`2C
`30
`34
`38
`3C
`40
`44
`48
`4C
`50
`54
`58
`5C
`60
`64
`68
`6C
`70
`74
`78
`7C
`
`EP0-IN
`EP0-OUT
`EP1-IN
`EP1-OUT
`EP2
`EP4
`EP6
`EP8
`IBN
`
`EP0PING
`EP1PING
`EP2PING
`EP4PING
`EP6PING
`EP8PING
`ERRLIMIT
`–
`–
`–
`EP2ISOERR
`EP4ISOERR
`EP6ISOERR
`EP8ISOERR
`
`If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP substitutes its INT2VEC byte. Therefore, if the high
`byte (“page”) of a jump table address is preloaded at the location 0x0044, the automatically inserted INT2VEC byte at 0x0045 directs
`the jump to the correct address out of the 27 addresses within the page.
`
`2.8.3 FIFO/GPIF Interrupt (INT4)
`Just as the USB Interrupt is shared among 27 individual USB interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual
`FIFO/GPIF sources. The FIFO/GPIF Interrupt, similar to the USB Interrupt, can employ autovectoring. Table 4 on page 7 shows the
`priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources.
`
`Document Number: 38-08032 Rev. *W
`
`Page 6 of 68
`
`Exhibit 2035 - Page 06 of 68
`
`

`

`CY7C68013A, CY7C68014A
`CY7C68015A, CY7C68016A
`
`Table 4. Individual FIFO/GPIF Interrupt Sources
`Priority
`INT4VEC Value
`Source
`1
`80
`EP2PF
`2
` 84
`EP4PF
`3
`88
`EP6PF
`4
`8C
`EP8PF
`5
`90
`EP2EF
`6
`94
`EP4EF
`7
`98
`EP6EF
`8
`9C
`EP8EF
`9
`A0
`EP2FF
`10
`A4
`EP4FF
`11
` A8
`EP6FF
`12
`AC
` EP8FF
`13
` B0
`GPIFDONE
`14
` B4
`GPIFWF
`
`Notes
`
`Endpoint 2 programmable flag
`Endpoint 4 programmable flag
`Endpoint 6 programmable flag
`Endpoint 8 programmable flag
`Endpoint 2 empty flag [3]
`Endpoint 4 empty flag
`Endpoint 6 empty flag
`Endpoint 8 empty flag
`Endpoint 2 full flag
`Endpoint 4 full flag
`Endpoint 6 full flag
`Endpoint 8 full flag
`GPIF operation complete
`GPIF waveform
`
`If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP
`register), the FX 2LP substitutes its INT4VEC byte. Therefore, if
`the high byte (“page”) of a jump-table address is preloaded at
`location 0x0054, the automatically inserted INT4VEC byte at
`0x0055 directs the jump to the correct address out of the 14
`
`addresses within the page. When the ISR occurs, the FX2LP
`pushes the program counter to its stack then jumps to address
`0x0053, where it expects to find a “jump” instruction to the ISR
`Interrupt service routine.
`
`Note
`3. Errata: In Slave FIFO Asynchronous Word Wide mode, if a single word data is transferred from the USB host to EP2, configured as OUT Endpoint (EP) in the first
`transaction, then the Empty flag behaves incorrectly. This does not happen if the data size is more than one word in the first transaction. For more information, see
`the “Errata” on page 64.
`
`Document Number: 38-08032 Rev. *W
`
`Page 7 of 68
`
`Exhibit 2035 - Page 07 of 68
`
`

`

`CY7C68013A, CY7C68014A
`CY7C68015A, CY7C68016A
`
`2.9 Reset and Wakeup
`2.9.1 Reset Pin
`The input pin, RESET#, resets the FX2LP when asserted. This
`pin has hysteresis and is active LOW. When a crystal is used with
`the CY7C680xxA the reset period must enable stabilization of
`the crystal and the PLL. This reset period must be approximately
`5 ms after VCC reaches 3.0V. If the crystal input pin is driven by
`a clock signal the internal PLL stabilizes in 200 s after VCC has
`reached 3.0V.[4]
`
`Figure 2-2 on page 8 shows a power on reset condition and a
`reset applied during operation. A power on reset is defined as
`the time reset that is asserted while power is being applied to the
`circuit. A powered reset is when the FX2LP powered on and
`operating and the RESET# pin is asserted.
`Cypress provides an application note which describes and
`recommends power on reset implementation. For more
`information about reset implementation for the FX2 family of
`products visit http://www.cypress.com.
`
`RESET#
`
`VCC
`
`Figure 2-2. Reset Timing Plots
`
`
`
`RESET#
`
`VCC
`
`VIL
`
`3.3V
`3.0V
`
`0V
`
`VIL
`3.3V
`
`0V
`
`TRESET
`
`Power on Reset
`
`Table 2-1. Reset Timing Values
`Condition
`Power on reset with crystal
`Power on reset with external
`clock
`Powered Reset
`
`TRESET
`
`5 ms
`200 s + Clock stability time
`
`200 s
`
`2.9.2 Wakeup Pins
`The 8051 puts itself and the rest of the chip into a power down
`mode by setting PCON.0 = 1. This stops the oscillator and PLL.
`When WAKEUP is asserted by external logic the oscillator
`restarts after the PLL stabilizes, and the 8051 receives a wakeup
`
`TRESET
`
`Powered Reset
`interrupt. This applies whether or not FX2LP is connected to the
`USB.
`The FX2LP exits the power down (USB suspend) state using one
`of the following methods:
`■ USB bus activity (if D+/D– lines are left floating, noise on these
`lines may indicate activity to the FX2LP and initiate a wakeup)
`■ External logic asserts the WAKEUP pin
`■ External logic asserts the PA3/WU2 pin
`The second wakeup pin, WU2, can also be configured as a
`general purpose I/O pin. This enables a simple external R-C
`network to be used as a periodic wakeup source. WAKEUP is by
`default active LOW.
`
`Note
`4.
`If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 s.
`
`Document Number: 38-08032 Rev. *W
`
`Page 8 of 68
`
`Exhibit 2035 - Page 08 of 68
`
`

`

`CY7C68013A, CY7C68014A
`CY7C68015A, CY7C68016A
`
`chip. This enables the user to connect a 64 KByte memory
`without requiring address decodes to keep clear of internal
`memory spaces.
`Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM
`spaces have the following access:
`■ USB download
`■ USB upload
`■ Setup data pointer
`■ I2C interface boot load.
`2.10.3 External Code Memory, EA = 1
`The bottom 16 KBytes of program memory is external and
`therefore the bottom 16 KBytes of internal RAM is accessible
`only as a data memory.
`
`2.10 Program/Data RAM
`2.10.1 Size
`The FX2LP has 16 KBytes of internal program/data RAM, where
`PSEN#/RD# signals are internally ORed to enable the 8051 to
`access it as both program and data memory. No USB control
`registers appear in this space.
`Two memory maps are shown in the following diagrams:
`Figure 2-3 on page 9 shows the Internal Code Memory, EA = 0
`Figure 2-4 on page 10 shows the External Code Memory, EA = 1.
`
`2.10.2 Internal Code Memory, EA = 0
`This mode implements the internal 16 KByte block of RAM
`(starting at 0) as combined code and data memory. When
`external RAM or ROM is added, the external read and write
`strobes are suppressed for memory spaces that exist inside the
`Figure 2-3. Internal Code Memory, EA = 0
`
`Inside FX2LP
`
`Outside FX2LP
`
`FFFF
`
`E200
`E1FF
`
`E000
`
`7.5 KBytes
`USB regs and
`4K FIFO buffers
`(RD#,WR#)
`
`0.5 KBytes RAM
`Data (RD#,WR#)*
`
`(OK to populate
`data memory
`here—RD#/WR#
`strobes are not
`active)
`
`40 KBytes
`External
`Data
`Memory
`(RD#,WR#)
`
`48 KBytes
`External
`Code
`Memory
`(PSEN#)
`
`16 KBytes RAM
`Code and Data
`(PSEN#,RD#,WR#)*
`
`(Ok to populate
`data memory
`here—RD#/WR#
`strobes are not
`active)
`
`(OK to populate
`program
`memory here—
`PSEN# strobe
`is not active)
`
`3FFF
`
`0000
`
`*SUDPTR, USB upload/download, I2C interface boot access
`
`Data
`
`Code
`
`Document Number: 38-08032 Rev. *W
`
`Page 9 of 68
`
`Exhibit 2035 - Page 09 of 68
`
`

`

`CY7C68013A, CY7C68014A
`CY7C68015A, CY7C68016A
`
`2.11 Register Addresses
`
`Figure 2-4. External Code Memory, EA = 1
`
`Inside FX2LP
`
`Outside FX2LP
`
`FFFF
`
`E200
`E1FF
`E000
`
`7.5 KBytes
`USB regs and
`4K FIFO buffers
`(RD#,WR#)
`
`0.5 KBytes RAM
`Data (RD#,WR#)*
`
`(OK to populate
`data memory
`here—RD#/WR#
`strobes are not
`active)
`
`40 KBytes
`External
`Data
`Memory
`(RD#,WR#)
`
`64 KBytes
`External
`Code
`Memory
`(PSEN#)
`
`3FFF
`
`0000
`
`16 KBytes
`RAM
`Data
`(RD#,WR#)*
`
`(Ok to populate
`data memory
`here—RD#/WR#
`strobes are not
`active)
`
`Data
`Code
`*SUDPTR, USB upload/download, I2C interface boot access
`
`FFFF
`
`F000
`EFFF
`
`E800
`E7FF
`E7C0
`E7BF
`E780
`E77F
`E740
`E73F
`E700
`E6FF
`
`E500
`E4FF
`E480
`E47F
`E400
`E3FF
`E200
`E1FF
`
`E000
`
`4 KBytes EP2-EP8
`buffers
`(8 x 512)
`
`2 KBytes RESERVED
`
`64 Bytes EP1IN
`
`64 Bytes EP1OUT
`
`64 Bytes EP0 IN/OUT
`
`64 Bytes RESERVED
`
`8051 Addressable Registers
`(512)
`
`Reserved (128)
`
`128 bytes GPIF Waveforms
`
`Reserved (512)
`
`512 bytes
`8051 xdata RAM
`
`Document Number: 38-08032 Rev. *W
`
`Page 10 of 68
`
`Exhibit 2035 - Page 10 of 68
`
`

`

`CY7C68013A, CY7C68014A
`CY7C68015A, CY7C68016A
`
`2.12 Endpoint RAM
`2.12.1 Size
`■ 3 × 64 bytes
`■ 8 × 512 bytes
`
`(Endpoints 0 and 1)
`(Endpoints 2, 4, 6, 8)
`
`2.12.2 Organization
`■ EP0
`■ Bidirectional endpoint zero, 64 byte buffer
`■ EP1IN, EP1OUT
`■ 64 byte buffers, bulk or interrupt
`■ EP2, 4, 6, 8
`■ Eight 512 byte buffers, bulk, interrupt, or isochronous. EP4 and
`EP8 can be double buffered; EP2 and 6 can be either double,
`triple, or quad buffered. For high speed endpoint configuration
`options, see Figure 2-5.
`
`2.12.3 Setup Data Buffer
`A separate 8 byte buffer at 0xE6B8-0xE6BF holds the setup data
`from a CONTROL transfer.
`
`2.12.4 Endpoint Configurations (High Speed Mode)
`Endpoints 0 and 1 are the same for every configuration. Endpoint
`0 is the only CONTROL endpoint, and endpoint 1 can be either
`BULK or INTERRUPT.
`The endpoint buffers can be configured in any 1 of the 12
`configurations shown in the vertical columns. When operating in
`the full speed BULK mode only the first 64 bytes of each buffer
`are used. For example, in high speed, the max packet size is 512
`bytes but in full speed it is 64 bytes. Even though a buffer is
`configured to a 512 byte buffer, in full speed only the first 64 bytes
`are used. The unused endpoint buffer space is not available for
`other operations. An example endpoint configuration is the
`EP2–1024 double buffered; EP6–512 quad buffered (column 8).
`
`Figure 2-5. Endpoint Configuration
`
`EP0 IN&OUT
`EP1 IN
`EP1 OUT
`
`64
`64
`64
`
`EP2
`512
`512
`EP4
`512
`512
`
`EP6
`512
`512
`EP8
`512
`512
`
`1
`
`64
`64
`64
`
`EP2
`512
`512
`EP4
`512
`512
`
`EP6
`512
`512
`
`512
`512
`
`2
`
`64
`64
`64
`
`EP2
`512
`512
`EP4
`512
`512
`
`EP6
`
`1024
`
`1024
`
`3
`
`64
`64
`64
`
`EP2
`512
`512
`
`512
`512
`
`EP6
`512
`512
`EP8
`512
`512
`4
`
`64
`64
`64
`
`EP2
`512
`512
`
`512
`512
`
`EP6
`512
`512
`
`512
`512
`5
`
`64
`64
`64
`
`EP2
`512
`512
`
`512
`512
`
`EP6
`
`1024
`
`1024
`
`6
`
`64
`64
`64
`
`64
`64
`64
`
`64
`64
`64
`
`64
`64
`64
`
`64
`64
`64
`
`64
`64
`64
`
`EP2
`
`1024
`
`EP2
`
`1024
`
`EP2
`
`1024
`
`1024
`
`1024
`
`1024
`
`EP6
`512
`512
`EP8
`512
`512
`
`7
`
`EP6
`512
`512
`
`512
`512
`
`8
`
`EP6
`
`1024
`
`1024
`
`9
`
`1024
`
`1024
`
`EP2 EP2 EP2
`512
`512
`512
`EP6
`512
`
`1024
`
`1024
`
`512
`
`1024
`1024
`
`512
`EP8 EP8
`512
`512
`
`512
`
`10
`
`512
`
`11
`
`1024
`
`1024
`
`12
`
`Document Number: 38-08032 Rev. *W
`
`Page 11 of 68
`
`Exhibit 2035 - Page 11 of 68
`
`

`

`2.12.5 Default Full Speed Alternate Settings
`Table 5. Default Full Speed Alternate Settings[5, 6]
`Alternate Setting
`0
`64
`0
`0
`0
`0
`0
`0
`
`ep0
`ep1out
`ep1in
`ep2
`ep4
`ep6
`ep8
`
`1
`
`64
`64 bulk
`64 bulk
`64 bulk out (2×)
`64 bulk out (2×)
`64 bulk in (2×)
`64 bulk in (2×)
`
`2.12.6 Default High Speed Alternate Settings
`Table 6. Default High Speed Alternate Settings[5, 6]
`Alternate Setting
`0
`1
`
`ep0
`ep1out
`ep1in
`ep2
`ep4
`ep6
`ep8
`
`64
`0
`0
`0
`0
`0
`0
`
`64
`512 bulk[7]
`512 bulk[7]
`512 bulk out (2×)
`512 bulk out (2×)
`512 bulk in (2×)
`512 bulk in (2×)
`
`CY7C68013A, CY7C68014A
`CY7C68015A, CY7C68016A
`
`2
`
`64
`64 int
`64 int
`64 int out (2×)
`64 bulk out (2×)
`64 int in (2×)
`64 bulk in (2×)
`
`2
`
`64
`64 int
`64 int
`512 int out (2×)
`512 bulk out (2×)
`512 int in (2×)
`512 bulk in (2×)
`
`3
`
`64
`64 int
`64 int
`64 iso out (2×)
`64 bulk out (2×)
`64 iso in (2×)
`64 bulk in (2×)
`
`3
`
`64
`64 int
`64 int
`512 iso out (2×)
`512 bulk out (2×)
`512 iso in (2×)
`512 bulk in (2×)
`
`2.13 External FIFO Interface
`2.13.1 Architecture
`The FX2LP slave FIFO architecture has eight 512 byte blocks in
`the endpoint RAM that directly serve as FIFO memories and are
`controlled by FIFO control signals (such as IFCLK, SLCS#,
`SLRD, SLWR, SLOE, PKTEND, and flags).
`In operation, some of the eight RAM blocks fill or empty from the
`SIE, while the others are connected to the I/O transfer logic. The
`transfer logic takes two forms, the GPIF for internally generated
`control signals and the slave FIFO interface for externally
`controlled transfers.
`
`2.13.2 Master/Slave Control Signals
`The FX2LP endpoint FIFOS are implemented as eight physically
`distinct 256x16 RAM blocks. The 8051/SIE can switch any of the
`RAM blocks between two domains, the USB (SIE) domain and
`the 8051-I/O Unit domain. This switching is done virtually
`instantaneously, giving essentially zero transfer time between
`“USB FIFOS” and “Slave FIFOS.” Because they are physically
`the same memory no bytes are actually transferred between
`buffers.
`At any time, some RAM blocks are filling/emptying with USB data
`under SIE control, while other RAM blocks are available to the
`8051, the I/O control unit or both. The RAM blocks operate as
`single port in the USB domain, and dual port in the 8051-I/O
`
`domain. The blocks can be configured as single, double, triple,
`or quad buffered as previously shown.
`The I/O control unit implements either an internal master (M for
`master) or external master (S for Slave) interface.
`In Master (M) mode, the GPIF internally controls FIFOADR[1..0]
`to select a FIFO. The RDY pins (two in the 56-pin package, six
`in the 100-pin and 128-pin packages) can be used as flag inputs
`from an external FIFO or other logic if desired. The GPIF can be
`run from either an internally derived clock or externally supplied
`clock (IFCLK), at a rate that transfers data up to 96 Megabytes/s
`(48 MHz IFCLK with 16-bit interface).
`In Slave (S) mode, the FX2LP accepts either an internally
`derived clock or externally supplied clock (IFCLK, max frequency
`48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals
`from external logic. When using an external IFCLK, the external
`clock must be present before switching to the external clock with
`the IFCLKSRC bit. Each endpoint can individually be selected
`for byte or word operation by an internal configuration bi