CY7C64713
`EZ-USB FX1™ USB Microcontroller
`Full Speed USB Peripheral Controller
`
`EZ-USB FX1™ USB Microcontroller Full Speed USB Peripheral Controller
`
`Features
`■ Single chip integrated USB transceiver, SIE, and enhanced
`8051 microprocessor
`■ Fit, form, and function upgradable to the FX2LP (CY7C68013A)
`❐ Pin compatible
`❐ Object code compatible
`❐ Functionally compatible (FX1 functionality is a subset of the
`FX2LP)
`■ Draws no more than 65 mA in any mode, making the FX1
`suitable for bus powered applications
`■ Software: 8051 runs from internal RAM, which is:
`❐ Downloaded using USB
`❐ Loaded from EEPROM
`❐ External memory device (128 pin configuration only)
`■ 16 KB of on-chip code/data RAM
`■ Four programmable BULK/INTERRUPT/ISOCHRONOUS
`endpoints
`❐ Buffering options: double, triple, and quad
`■ Additional programmable
`(BULK/INTERRUPT) 64-byte
`endpoint
`■ 8- or 16-bit external data interface
`■ Smart media standard ECC generation
`■ GPIF
`❐ Allows direct connection to most parallel interfaces; 8- and
`16-bit
`❐ Programmable waveform descriptors and configuration
`registers to define waveforms
`❐ Supports multiple ready (RDY) inputs and Control (CTL)
`outputs
`■ Integrated, industry standard 8051 with enhanced features:
`
`❐ Up to 48 MHz clock rate
`❐ Four clocks for each instruction cycle
`❐ Two USARTS
`❐ Three counters or timers
`❐ Expanded interrupt system
`❐ Two data pointers
`■ 3.3 V operation with 5 V tolerant inputs
`■ Smart SIE
`■ Vectored USB interrupts
`■ Separate data buffers for the setup and DATA portions of a
`CONTROL transfer
`■ Integrated I2C controller, running at 100 or 400 KHz
`■ 48 MHz, 24 MHz, or 12 MHz 8051 operation
`■ Four integrated FIFOs
`❐ Brings glue and FIFOs inside for lower system cost
`❐ Automatic conversion to and from 16-bit buses
`❐ Master or slave operation
`❐ FIFOs can use externally supplied clock or asynchronous
`strobes
`❐ Easy interface to ASIC and DSP ICs
`■ Vectored for FIFO and GPIF Interrupts
`■ Up to 40 general purpose IOs (GPIO)
`■ Four package options:
`❐ 128-pin TQFP
`❐ 100-pin TQFP
`❐ 56-pin SSOP
`❐ 56-pin QFN Pb-free
`
`Errata: For information on silicon errata, see “Errata” on page 71. Details include trigger conditions, devices affected, and proposed workaround.
`
`Cypress Semiconductor Corporation
`Document Number: 38-08039 Rev. *L
`
`•
`
`198 Champion Court
`
`•
`
`San Jose, CA 95134-1709
`
`408-943-2600
`•
` Revised March 9, 2014
`
`Exhibit 2034 - Page 01 of 74
`
`

`

`CY7C64713
`
`I2C
`Master
`
`Additional IOs (24)
`
`GPIF
`
`ADDR (9)
`
`RDY (6)
`CTL (6)
`
`ECC
`
`Abundant I/O
`including two USARTS
`
`General
`programmable I/F
`to ASIC/DSP or bus
`standards such as
`ATAPI, EPP, etc.
`
`4 kB
`FIFO
`
`8/16
`
`Up to 96 MBytes
`burst rate
`
`Logic Block Diagram
`
`24 MHz
`Ext. XTAL
`
`High performance micro
`using standard tools
`with lower-power options
`
`Data (8)
`
`Address (16) / Data Bus (8)
`
`Address (16)
`
`8051 Core
`12/24/48 MHz,
`four clocks/cycle
`
`CY
`Smart
`USB
`Engine
`
`16 KB
`RAM
`
`FX1
`
`VCC
`
`x20
`PLL
`
`/0.5
`/1.0
`/2.0
`
`1.5k
`connected for
`enumeration
`
`D+
`
`D–
`
`USB
`
`XCVR
`
`Integrated
`full speed XCVR
`
`Enhanced USB core
`Simplifies 8051 code
`
`‘Soft Configuration’
`Easy firmware changes
`
`FIFO and endpoint memory
`(master or slave operation)
`
`Document Number: 38-08039 Rev. *L
`
`Page 2 of 74
`
`Exhibit 2034 - Page 02 of 74
`
`

`

`CY7C64713
`
`Contents
`Functional Description .....................................................4
`Applications ......................................................................4
`Functional Overview ........................................................4
`USB Signaling Speed ..................................................4
`8051 Microprocessor ...................................................4
`I2C Bus ........................................................................5
`Buses ..........................................................................5
`USB Boot Methods ......................................................5
`ReNumeration™ ..........................................................6
`Bus-powered Applications ...........................................6
`Interrupt System ..........................................................6
`Reset and Wakeup ......................................................8
`Program/Data RAM .....................................................9
`Endpoint RAM ...........................................................11
`External FIFO Interface .............................................11
`GPIF ..........................................................................12
`ECC Generation ........................................................13
`USB Uploads and Downloads ...................................13
`Autopointer Access ...................................................13
`I2C Controller .............................................................13
`Compatible with Previous Generation
`EZ-USB FX2 .....................................................................14
`Pin Assignments ............................................................14
`CY7C64713 Pin Definitions ............................................20
`Register Summary ..........................................................28
`Absolute Maximum Ratings ..........................................47
`Operating Conditions .....................................................47
`DC Characteristics .........................................................47
`USB Transceiver .......................................................47
`AC Electrical Characteristics ........................................48
`USB Transceiver .......................................................48
`PORTC Strobe Feature Timings ...............................51
`
`GPIF Synchronous Signals ....................................... 52
`Slave FIFO Synchronous Read ................................. 53
`Slave FIFO Asynchronous Read ............................... 54
`Slave FIFO Synchronous Write ................................. 55
`Slave FIFO Asynchronous Write ............................... 56
`Slave FIFO Synchronous Packet End Strobe ........... 56
`Slave FIFO Asynchronous Packet End Strobe ......... 58
`Slave FIFO Output Enable ........................................ 58
`Slave FIFO Address to Flags/Data ............................ 58
`Slave FIFO Synchronous Address ............................ 59
`Slave FIFO Asynchronous Address .......................... 59
`Sequence Diagram .................................................... 60
`Ordering Information ...................................................... 64
`Ordering Code Definitions ......................................... 64
`Package Diagrams .......................................................... 65
`Quad Flat Package No Leads (QFN) Package
`Design Notes ................................................................... 68
`Acronyms ........................................................................ 70
`Document Conventions ................................................. 70
`Units of Measure ....................................................... 70
`Errata ............................................................................... 71
`Part Numbers Affected .............................................. 71
`EZ-USB FX1 Qualification Status .............................. 71
`EZ-USB FX1 Errata Summary .................................. 71
`Document History Page ................................................. 72
`Sales, Solutions, and Legal Information ...................... 74
`Worldwide Sales and Design Support ....................... 74
`Products .................................................................... 74
`PSoC® Solutions ...................................................... 74
`Cypress Developer Community ................................. 74
`Technical Support ..................................................... 74
`
`Document Number: 38-08039 Rev. *L
`
`Page 3 of 74
`
`Exhibit 2034 - Page 03 of 74
`
`

`

`Functional Description
`EZ-USB FX1 (CY7C64713) is a full speed, highly integrated,
`USB microcontroller. By integrating the USB transceiver, Serial
`Interface Engine (SIE), enhanced 8051 microcontroller, and a
`programmable peripheral interface in a single chip, Cypress has
`created a very cost effective solution that provides superior
`time-to-market advantages.
`The EZ-USB FX1 is more economical, because it incorporates
`the USB transceiver and provides a smaller footprint solution
`than the USB SIE or external transceiver implementations. With
`EZ-USB FX1, the Cypress Smart SIE handles most of the USB
`protocol in hardware, freeing the embedded microcontroller for
`application specific functions and decreasing the development
`time to ensure USB compatibility.
`The General Programmable Interface (GPIF) and Master/Slave
`Endpoint FIFO (8 or 16-bit data bus) provide an easy and
`glueless interface to popular interfaces such as ATA, UTOPIA,
`EPP, PCMCIA, and most DSP/processors.
`Four Pb-free packages are defined for the family: 56-pin SSOP,
`56-pin QFN, 100-pin TQFP, and 128-pin TQFP.
`Applications
`■ DSL modems
`■ ATA interface
`■ Memory card readers
`■ Legacy conversion devices
`■ Home PNA
`■ Wireless LAN
`■ MP3 players
`■ Networking
`The Reference Designs section of the cypress website provides
`additional tools for typical USB applications. Each reference
`design comes complete with firmware source and object code,
`schematics,
`and
`documentation.
`Please
`visit
`http://www.cypress.com for more information.
`Functional Overview
`USB Signaling Speed
`FX1 operates at one of the three rates defined in the USB
`Specification Revision 2.0, dated April 27, 2000:
`Full speed, with a signaling bit rate of 12 Mbps.
`
`CY7C64713
`
`FX1 does not support the low speed signaling mode of 1.5 Mbps
`or the high speed mode of 480 Mbps.
`8051 Microprocessor
`The 8051 microprocessor embedded in the FX1 family has
`256 bytes of register RAM, an expanded interrupt system, three
`timer/counters, and two USARTs.
`
`8051 Clock Frequency
`FX1 has an on-chip oscillator circuit that uses an external
`24 MHz (±100 ppm) crystal with the following characteristics:
`■ Parallel resonant
`■ Fundamental mode
`■ 500 W drive level
`■ 12 pF (5% tolerance) load capacitors.
`An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz,
`as required by the transceiver/PHY, and the internal counters
`divide it down for use as the 8051 clock. The default 8051 clock
`frequency is 12 MHz. The clock frequency of the 8051 is
`dynamically changed by the 8051 through the CPUCS register.
`The CLKOUT pin, which is three-stated and inverted using the
`internal control bits, outputs the 50% duty cycle 8051 clock at the
`selected 8051 clock frequency which is 48, 24, or 12 MHz.
`
`USARTS
`FX1 contains two standard 8051 USARTs, addressed by Special
`Function Register (SFR) bits. The USART interface pins are
`available on separate I/O pins, and are not multiplexed with port
`pins.
`UART0 and UART1 can operate using an internal clock at
`230 KBaud with no more than 1% baud rate error. 230 KBaud
`operation is achieved by an internally derived clock source that
`generates overflow pulses at the appropriate time. The internal
`clock adjusts for the 8051 clock rate (48, 24, 12 MHz) such that
`it always presents the correct frequency for 230-KBaud
`operation.[1]
`Special Function Registers
`Certain 8051 SFR addresses are populated to provide fast
`access to critical FX1 functions. These SFR additions are shown
`in Table 1 on page 5. Bold type indicates non-standard,
`enhanced 8051 registers. The two SFR rows that end with ‘0’ and
`‘8’ contain bit addressable registers. The four I/O ports A–D use
`the SFR addresses used in the standard 8051 for ports 0–3,
`which are not implemented in the FX1. Because of the faster and
`more efficient SFR addressing, the FX1 I/O ports are not
`addressable in the external RAM space (using the MOVX
`instruction).
`
`Note
`1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a ‘1’ for UART0 and UART1, respectively.
`
`Document Number: 38-08039 Rev. *L
`
`Page 4 of 74
`
`Exhibit 2034 - Page 04 of 74
`
`

`

`CY7C64713
`
`Figure 1. Crystal Configuration
`24 MHz
`C1
`
`C2
`
`12 pF
`
`12 pF
`
`12-pF capacitor values assumes
`a trace capacitance of 3 pF per
`side on a four layer FR4 PCA
`
`20 × PLL
`
`Table 1. Special Function Registers
`x
`8x
`9x
`IOA
`IOB
`0
`EXIF
`1
`SP
`MPAGE
`2
`DPL0
`3
`DPH0
`DPL1
`4
`DPH1
`5
`DPS
`6
`7
`PCON
`8
`TCON
`9
`TMOD
`A
`TL0
`B
`TL1
`C
`TH0
`D
`TH1
`CKCON
`E
`F
`
`SCON0
`SBUF0
`AUTOPTRH1
`AUTOPTRL1
`reserved
`AUTOPTRH2
`AUTOPTRL2
`reserved
`
`Ax
`IOC
`INT2CLR
`INT4CLR
`
`IE
`
`EP2468STAT
`EP24FIFOFLGS
`EP68FIFOFLGS
`
`Bx
`IOD
`IOE
`OEA
`OEB
`OEC
`OED
`OEE
`
`IP
`
`EP01STAT
`GPIFTRIG
`
`GPIFSGLDATH
`GPIFSGLDATLX
`AUTOPTRSETUP GPIFSGLDATLNOX
`
`Cx
`SCON1
`SBUF1
`
`Ex
`Dx
`PSW ACC
`
`Fx
`B
`
`T2CON
`
`EICON
`
`EIE
`
`EIP
`
`RCAP2L
`RCAP2H
`TL2
`TH2
`
`I2C Bus
`FX1 supports the I2C bus as a master only at 100/400 KHz. SCL
`and SDA pins have open drain outputs and hysteresis inputs.
`These signals must be pulled up to 3.3 V, even if no I2C device
`is connected.
`Buses
`All packages: 8 or 16-bit ‘FIFO’ bidirectional data bus,
`multiplexed on I/O ports B and D. 128-pin package: adds 16-bit
`output only 8051 address bus, 8-bit bidirectional data bus.
`USB Boot Methods
`During the power up sequence, internal logic checks the I2C port
`for the connection of an EEPROM whose first byte is either 0xC0
`or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM
`
`in place of the internally stored values (0xC0). Alternatively, it
`boot-loads the EEPROM contents into an internal RAM (0xC2).
`If no EEPROM is detected, FX1 enumerates using internally
`stored descriptors. The default
`ID values
`for FX1 are
`VID/PID/DID
`(0x04B4, 0x6473, 0xAxxx where xxx=Chip
`revision).[2]
`Table 2. Default ID Values for FX1
`Default VID/PID/DID
`Vendor ID 0x04B4 Cypress Semiconductor
`Product ID 0x6473 EZ-USB FX1
`Device
`0xAnnn Depends on chip revision (nnn = chip
`release
`revision where first silicon = 001)
`
`Notes
`2. The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
`
`Document Number: 38-08039 Rev. *L
`
`Page 5 of 74
`
`Exhibit 2034 - Page 05 of 74
`
`

`

`ReNumeration™
`Because the FX1’s configuration is soft, one chip can take on the
`identities of multiple distinct USB devices.
`When first plugged into the USB, the FX1 enumerates
`automatically and downloads firmware and the USB descriptor
`tables over the USB cable. Next, the FX1 enumerates again, this
`time as a device defined by the downloaded information. This
`patented two step process, called ReNumeration, happens
`instantly when the device is plugged in, with no indication that
`the initial download step has occurred.
`Two control bits in the USBCS (USB Control and Status) register
`control the ReNumeration process: DISCON and RENUM. To
`simulate a USB disconnect, the firmware sets DISCON to 1. To
`reconnect, the firmware clears DISCON to 0.
`Before reconnecting, the firmware sets or clears the RENUM bit
`to indicate if the firmware or the Default USB Device handles
`device requests over endpoint zero:
`■ RENUM = 0, the Default USB Device handles device requests
`■ RENUM = 1, the firmware handles device requests
`Bus-powered Applications
`The FX1 fully supports bus powered designs by enumerating
`with less than 100 mA as required by the USB specification.
`Interrupt System
`INT2 Interrupt Request and Enable Registers
`FX1 implements an autovector feature for INT2 and INT4. There
`are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors.
`See EZ-USB Technical Reference Manual (TRM) for more
`details.
`Table 3. INT2 USB Interrupts
`
`CY7C64713
`
`USB-Interrupt Autovectors
`The main USB interrupt is shared by 27 interrupt sources. The
`FX1 provides a second level of interrupt vectoring, called
`Autovectoring, to save code and processing time that is normally
`required to identify the individual USB interrupt source. When a
`USB interrupt is asserted, the FX1 pushes the program counter
`on to its stack and then jumps to address 0x0043, where it
`expects to find a “jump” instruction to the USB Interrupt service
`routine.
`The FX1 jump instruction is encoded as shown in Table 3.
`If Autovectoring is enabled (AV2EN = 1 in the INTSETUP
`register), the FX1 substitutes its INT2VEC byte. Therefore, if the
`high byte (“page”) of a jump table address is preloaded at
`location 0x0044, the automatically inserted INT2VEC byte at
`0x0045 directs the jump to the correct address out of the 27
`addresses within the page.
`FIFO/GPIF Interrupt (INT4)
`Just as the USB Interrupt is shared among 27 individual
`USB-interrupt sources, the FIFO/GPIF interrupt is shared among
`14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, such
`as the USB Interrupt, can employ autovectoring. Table 4 on page
`7 shows the priority and INT4VEC values for the 14 FIFO/GPIF
`interrupt sources.
`
`FIFO/GPIF Interrupt (INT4)
`Just as the USB Interrupt is shared among 27 individual
`USB-interrupt sources, the FIFO/GPIF interrupt is shared among
`14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, such
`as the USB Interrupt, can employ autovectoring.
`Table 4 on page 7 shows the priority and INT4VEC values for the
`14 FIFO/GPIF interrupt sources.
`
`Priority
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`
`INT2VEC Value
` 00
` 04
` 08
`0C
`10
`14
`18
`1C
`20
`24
`28
`2C
`30
`34
`38
`3C
`40
`
`USB INTERRUPT TABLE FOR INT2
`Source
`
`Notes
`
`SUDAV
`SOF
`SUTOK
`SUSPEND
`USB RESET
`
`EP0ACK
`
`EP0-IN
`EP0-OUT
`EP1-IN
`EP1-OUT
`EP2
`EP4
`EP6
`EP8
`IBN
`
`Setup Data Available
`Start of Frame
`Setup Token Received
`USB Suspend request
`Bus reset
`Reserved
`FX1 ACK’d the CONTROL Handshake
`Reserved
`EP0-IN ready to be loaded with data
`EP0-OUT has USB data
`EP1-IN ready to be loaded with data
`EP1-OUT has USB data
`IN: buffer available. OUT: buffer has data
`IN: buffer available. OUT: buffer has data
`IN: buffer available. OUT: buffer has data
`IN: buffer available. OUT: buffer has data
`IN-Bulk-NAK (any IN endpoint)
`
`Document Number: 38-08039 Rev. *L
`
`Page 6 of 74
`
`Exhibit 2034 - Page 06 of 74
`
`

`

`Table 3. INT2 USB Interrupts (continued)
`
`CY7C64713
`
`USB INTERRUPT TABLE FOR INT2
`Source
`
`Notes
`
`Reserved
`EP0 OUT was Pinged and it NAK’d
`EP1 OUT was Pinged and it NAK’d
`EP2 OUT was Pinged and it NAK’d
`EP4 OUT was Pinged and it NAK’d
`EP6 OUT was Pinged and it NAK’d
`EP8 OUT was Pinged and it NAK’d
`Bus errors exceeded the programmed limit
`
`Reserved
`Reserved
`ISO EP2 OUT PID sequence error
`ISO EP4 OUT PID sequence error
`ISO EP6 OUT PID sequence error
`ISO EP8 OUT PID sequence error
`
`Notes
`Endpoint 2 Programmable Flag
`Endpoint 4 Programmable Flag
`Endpoint 6 Programmable Flag
`Endpoint 8 Programmable Flag
`Endpoint 2 Empty Flag [3]
`Endpoint 4 Empty Flag
`Endpoint 6 Empty Flag
`Endpoint 8 Empty Flag
`Endpoint 2 Full Flag
`Endpoint 4 Full Flag
`Endpoint 6 Full Flag
`Endpoint 8 Full Flag
`GPIF Operation Complete
`GPIF Waveform
`
`Priority
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`
`INT2VEC Value
`44
`48
`4C
`50
`54
`58
`5C
`60
`64
`68
`6C
`70
`74
`78
`7C
`
`EP0PING
`EP1PING
`EP2PING
`EP4PING
`EP6PING
`EP8PING
`ERRLIMIT
`
`EP2ISOERR
`EP4ISOERR
`EP6ISOERR
`EP8ISOERR
`
`Table 4. Individual FIFO/GPIF Interrupt Sources
`Priority
`INT4VEC Value
`Source
`1
`80
`2
` 84
`3
`88
`4
`8C
`5
`90
`6
`94
`7
`98
`8
`9C
`9
`A0
`10
`A4
`11
` A8
`12
`AC
`13
` B0
`14
` B4
`
`EP2PF
`EP4PF
`EP6PF
`EP8PF
`EP2EF
`EP4EF
`EP6EF
`EP8EF
`EP2FF
`EP4FF
`EP6FF
`EP8FF
`GPIFDONE
`GPIFWF
`
`If Autovectoring is enabled (AV4EN = 1 in the INTSETUP
`register), the FX1 substitutes its INT4VEC byte. Therefore, if the
`high byte (“page”) of a jump-table address is preloaded at
`location 0x0054, the automatically inserted INT4VEC byte at
`0x0055 directs the jump to the correct address out of the 14
`addresses within the page. When the ISR occurs, the FX1
`
`pushes the program counter onto its stack and then jumps to
`address 0x0053, where it expects to find a “jump” instruction to
`the ISR Interrupt service routine.
`
`Note
`3. Errata: In Slave FIFO Asynchronous Word Wide mode, if a single word data is transferred from the USB host to EP2, configured as OUT Endpoint (EP) in the first
`transaction, then the Empty flag behaves incorrectly. This does not happen if the data size is more than one word in the first transaction. For more information, see
`the “Errata” on page 71.
`
`Document Number: 38-08039 Rev. *L
`
`Page 7 of 74
`
`Exhibit 2034 - Page 07 of 74
`
`

`

`CY7C64713
`
`Reset and Wakeup
`Reset Pin
`The input pin, RESET#, resets the FX1 when asserted. This pin
`has hysteresis and is active LOW. When a crystal is used with
`the CY7C64713, the reset period must allow for the stabilization
`of the crystal and the PLL. This reset period must be
`approximately 5 ms after VCC has reached 3.0 Volts. If the
`crystal input pin is driven by a clock signal the internal PLL
`stabilizes in 200 s after VCC has reached 3.0 V[4]. Figure 2 on
`page 8 shows a power on reset condition and a reset applied
`Figure 2. Reset Timing Plots
`
`during operation. A power on reset is defined as the time a reset
`is asserted when power is being applied to the circuit. A powered
`reset is defined to be when the FX1 has been previously
`powered on and operating and the RESET# pin is asserted.
`Cypress provides an application note which describes and
`recommends power on reset implementation and is found on the
`Cypress web site. While the application note discusses the FX2,
`the information provided applies also to the FX1. For more
`information on reset implementation for the FX2 family of
`products visit http://www.cypress.com.
`
`RESET#
`
`VCC
`
`RESET#
`
`VCC
`
`VIL
`
`3.3 V
`3.0 V
`
`0 V
`
`VIL
`3.3 V
`
`0 V
`
`TRESET
`
`Power on Reset
`
`TRESET
`
`Powered Reset
`
`
`
`Table 5. Reset Timing Values
`Condition
`Power On Reset with crystal
`Power On Reset with external
`clock
`Powered Reset
`
`TRESET
`
`5 ms
`200 s + Clock stability time
`
`200 s
`
`Wakeup Pins
`The 8051 puts itself and the rest of the chip into a power down
`mode by setting PCON.0 = 1. This stops the oscillator and PLL.
`When WAKEUP is asserted by external logic, the oscillator
`restarts, after the PLL stabilizes, and then the 8051 receives a
`
`wakeup interrupt. This applies irrespective of whether the FX1 is
`connected to the USB or not.
`The FX1 exits the power down (USB suspend) state using one
`of the following methods:
`■ USB bus activity (if D+/D– lines are left floating, noise on these
`lines may indicate activity to the FX1 and initiate a wakeup).
`■ External logic asserts the WAKEUP pin.
`■ External logic asserts the PA3/WU2 pin.
`The second wakeup pin, WU2, can also be configured as a
`general purpose I/O pin. This allows a simple external R-C
`network to be used as a periodic wakeup source. Note that
`WAKEUP is by default active LOW.
`
`Note
`4.
`If the external clock is powered at the same time as the CY7C64713 and has a stabilization wait period. It must be added to the 200 s.
`
`Document Number: 38-08039 Rev. *L
`
`Page 8 of 74
`
`Exhibit 2034 - Page 08 of 74
`
`

`

`CY7C64713
`
`Program/Data RAM
`Size
`The FX1 has 16 KBytes of internal program/data RAM, where
`PSEN#/RD# signals are internally ORed to allow the 8051 to
`access it as both program and data memory. No USB control
`registers appear in this space.
`Two memory maps are shown in the following diagrams:
`■ Figure 3 on page 9 Internal Code Memory, EA = 0
`■ Figure 4 on page 10 External Code Memory, EA = 1.
`
`external RAM or ROM is added, the external read and write
`strobes are suppressed for memory spaces that exist inside the
`chip. This allows the user to connect a 64 KByte memory without
`requiring the address decodes to keep clear of internal memory
`spaces.
`Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM
`spaces have the following access:
`■ USB download
`■ USB upload
`■ Setup data pointer
`■ I2C interface boot load
`
`Internal Code Memory, EA = 0
`This mode implements the internal 16 KByte block of RAM
`(starting at 0) as combined code and data memory. When the
`Figure 3. Internal Code Memory, EA = 0.
`Inside FX1
`Outside FX1
`
`FFFF
`
`E200
`E1FF
`
`E000
`
`7.5 KBytes
`USB regs and
`4K FIFO buffers
`(RD#,WR#)
`
`0.5 KBytes RAM
`Data (RD#,WR#)*
`
`(OK to populate
`data memory
`here—RD#/WR#
`strobes are not
`active)
`
`40 KBytes
`External
`Data
`Memory
`(RD#,WR#)
`
`48 KBytes
`External
`Code
`Memory
`(PSEN#)
`
`16 KBytes RAM
`Code and Data
`(PSEN#,RD#,WR#)*
`
`(Ok to populate
`data memory
`here—RD#/WR#
`strobes are not
`active)
`
`(OK to populate
`program
`memory here—
`PSEN# strobe
`is not active)
`
`3FFF
`
`0000
`
`Code
`Data
`*SUDPTR, USB upload/download, I2C interface boot access
`
`Document Number: 38-08039 Rev. *L
`
`Page 9 of 74
`
`Exhibit 2034 - Page 09 of 74
`
`

`

`External Code Memory, EA = 1
`The bottom 16 KBytes of program memory is external, and therefore the bottom 16 KBytes of internal RAM is accessible only as data
`memory.
`
`CY7C64713
`
`Figure 4. External Code Memory, EA = 1
`
`Inside FX1
`
`Outside FX1
`
`FFFF
`
`E200
`E1FF
`E000
`
`7.5 KBytes
`USB regs and
`4K FIFO buffers
`(RD#,WR#)
`
`0.5 KBytes RAM
`Data (RD#,WR#)*
`
`(OK to populate
`data memory
`here—RD#/WR#
`strobes are not
`active)
`
`40 KBytes
`External
`Data
`Memory
`(RD#,WR#)
`
`64 KBytes
`External
`Code
`Memory
`(PSEN#)
`
`3FFF
`
`0000
`
`16 KBytes
`RAM
`Data
`(RD#,WR#)*
`
`(Ok to populate
`data memory
`here—RD#/WR#
`strobes are not
`active)
`
`Code
`Data
`*SUDPTR, USB upload/download, I2C interface boot access
`
`Document Number: 38-08039 Rev. *L
`
`Page 10 of 74
`
`Exhibit 2034 - Page 10 of 74
`
`

`

`CY7C64713
`
`2
`
`3
`
`0
`
`1
`
`Table 6. Default Alternate Settings
`Alternate
`Setting
`ep0
`ep1out
`ep1in
`ep2
`ep4
`ep6
`ep8
`
`Endpoint RAM
`Size
`■ 3 × 64 bytes
`■ 8 × 512 bytes
`
`(Endpoints 0 and 1)
`(Endpoints 2, 4, 6, 8)
`
`Organization
`■ EP0—Bidirectional endpoint zero, 64 byte buffer
`■ EP1IN, EP1OUT—64 byte buffers, bulk or interrupt
`■ EP2, 4, 6, 8—Eight 512-byte buffers, bulk, interrupt, or
`isochronous, of which only the transfer size is available. EP4
`and EP8 are double buffered, while EP2 and 6 are either
`double, triple, or quad buffered. Regardless of the physical size
`of the buffer, each endpoint buffer accommodates only one full
`speed packet. For bulk endpoints, the maximum number of
`bytes it can accommodate is 64, even though the physical
`buffer size is 512 or 1024. For an ISOCHRONOUS endpoint
`the maximum number of bytes it can accommodate is 1023.
`For endpoint configuration options, see Figure 6 on page 12.
`
`Setup Data Buffer
`A separate 8-byte buffer at 0xE6B8-0xE6BF holds the Setup
`data from a CONTROL transfer.
`
`Default Alternate Settings
`In the following table, ‘0’ means “not implemented”, and ‘2×’
`means “double buffered”.
`
`Figure 5. Register Addresses
`
`FFFF
`
`F000
`EFFF
`
`E800
`E7FF
`E7C0
`E7BF
`E780
`E77F
`E740
`E73F
`E700
`E6FF
`
`E500
`E4FF
`E480
`E47F
`E400
`E3FF
`E200
`E1FF
`
`E000
`
`4 KBytes EP2-EP8
`buffers
`(8 x 512)
`Not all Space is available
` for all transfer types
`
`2 KBytes RESERVED
`
`64 Bytes EP1IN
`
`64 Bytes EP1OUT
`
`64 Bytes EP0 IN/OUT
`
`64 Bytes RESERVED
`
`8051 Addressable Registers
`(512)
`
`Reserved (128)
`
`128 bytes GPIF Waveforms
`
`Reserved (512)
`
`512 bytes
`8051 xdata RAM
`
`64
`64
`64 64
`64 int
`64 int
`0
`64 bulk
`64 int
`64 int
`0
`64 bulk
`0
`64 bulk out (2×) 64 int out (2×) 64 iso out (2×)
`0
`64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×)
`0
`64 bulk in (2×) 64 int in (2×)
`64 iso in (2×)
`0
`64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)
`
`External FIFO Interface
`Architecture
`The FX1 slave FIFO architecture has eight 512-byte blocks in the
`endpoint RAM that directly serve as FIFO memories, and are
`controlled by FIFO control signals (such as IFCLK, SLCS#,
`SLRD, SLWR, SLOE, PKTEND, and flags). The usable size of
`these buffers depend on the USB transfer mode as described in
`the section Organization.
`In operation, some of the eight RAM blocks fill or empty from the
`SIE, while the others are connected to the I/O transfer logic. The
`transfer logic takes two forms: the GPIF for internally generated
`control signals or the slave FIFO interface for externally
`controlled transfers.
`
`Document Number: 38-08039 Rev. *L
`
`Page 11 of 74
`
`Exhibit 2034 - Page 11 of 74
`
`

`

`Figure 6. Endpoint Configuration
`64
`64
`64
`64
`64
`64
`
`64
`64
`64
`
`64
`64
`64
`
`64
`64
`64
`
`CY7C64713
`
`64
`64
`64
`
`64
`64
`64
`
`64
`64
`64
`
`64
`64
`64
`
`EP2
`64
`64
`
`64
`64
`
`EP6
`64
`64
`EP8
`64
`64
`4
`
`EP2
`64
`64
`
`64
`64
`
`EP6
`64
`64
`
`64
`64
`5
`
`EP2
`64
`64
`
`64
`64
`
`EP6
`
`1023
`
`1023
`
`6
`
`EP2
`
`1023
`
`EP2
`
`1023
`
`EP2
`
`1023
`
`1023
`
`1023
`
`1023
`
`EP6
`64
`64
`EP8
`64
`64
`
`7
`
`EP6
`64
`64
`
`64
`64
`
`8
`
`EP6
`
`1023
`
`1023
`
`9
`
`EP2 EP2 EP2
`64
`
`1023
`
`1023
`
`1023
`
`1023
`
`64
`64
`EP6
`64
`
`64
`
`1023
`1023
`
`64
`EP8 EP8
`64
`64
`
`64
`
`10
`
`64
`
`11
`
`1023
`
`1023
`
`12
`
`EP0 IN&OUT
`EP1 IN
`EP1 OUT
`
`64
`64
`64
`
`EP2
`64
`64
`EP4
`64
`64
`
`EP6
`64
`64
`EP8
`64
`64
`
`1
`
`64
`64
`64
`
`EP2
`64
`64
`EP4
`64
`64
`
`EP6
`64
`64
`
`64
`64
`
`2
`
`64
`64
`64
`
`EP2
`64
`64
`EP4
`64
`64
`
`EP6
`
`1023
`
`1023
`
`3
`
`Master/Slave Control Signals
`The FX1 endpoint FIFOS are implemented as eight physically
`distinct 256 × 16 RAM blocks. The 8051/SIE can switch any of
`the RAM blocks between two domains: the USB (SIE) domain
`and
`the 8051-I/O Unit domain. This switching
`is done
`instantaneously, giving essentially zero transfer time between
`“USB FIFOS” and “Slave FIFOS”. While they are physically the
`same memory, no bytes are actually transferred between
`buffers.
`At any time, some RAM blocks fill or empty with USB data under
`SIE control, while other RAM blocks are available to the 8051
`and the I/O control unit. The RAM blocks operate as a single-port
`in the USB domain, and dual port in the 8051-I/O domain. The
`blocks are configured as single, double, triple, or quad buffered.
`The I/O control unit implements either an internal master (M for
`master) or external master (S for Slave) interface.
`In Master (M) mode, the GPIF internally controls FIFOADR[1..0]
`to select a FIFO. The RDY pins (two in the 56-pin package, six
`in the 100-pin and 128-pin packages) are used as flag inputs
`from an external FIFO or other logic if desired. The GPIF is run
`from either an internally derived clock or an externally supplied
`clock (IFCLK), at a rate that transfers data up to 96 Megabytes/s
`(48 MHz IFCLK with 16-bit interface).
`In Slave (S) mode, the FX1 accepts either an internally derived
`clock or an externally supplied clock (IFCLK with a maximum
`frequency of 48 MHz) and SLCS#, SLRD, SLWR, SLOE,
`PKTEND signals from external logic. When using an external
`IFCLK, the external clock must be present before switching to
`the external clock with the IFCLKSRC bit. Each endpoint can
`individually be selected for byte or word operation by an internal
`configuration bit, and a Slave FIFO Output Enable signal SLOE
`enables data of the selected width. External logic must ensure
`that the output enable signal is inactive when writing data to a
`slave FIFO. The slave
`interface can also operate
`asynchronously, where the SLRD and SLWR signals act directly
`
`as strobes, rather than a clock qualifier as in the synchronous
`mode. The signals SLRD, SLWR, SLOE, and PKTEND are gated
`by the signal SLCS#.
`
`GPIF and FIFO Clock Rates
`An 8051 register bit selects one of two frequencies for the
`internally supplied interface clock: 30 MHz and 48 MHz.
`Alternatively, an externally supplied clock of 5 to 48 MHz feeding
`the IFCLK pin is used as the interface clock. IFCLK is configured
`to function as an output clock when the GPIF and FIFOs are
`internally clocked. An output enable bit in the IFCONFIG register
`turns this clock output off, if desired. Another bit within the
`IFCONFIG register inverts the IFCLK signal whether internally or
`externally sourced.
`GPIF
`The GPIF is a flexible 8 or 16-bit parallel interface driven by a
`user programmable
`finite state machine.
`It allows
`the
`CY7C64713 to perform local bus mastering, and can implement
`a wide variety of protocols such as ATA interface, printer parallel
`port, and Utopia.
`The GPIF has six programmable control outputs (CTL), nine
`address outputs (GPIFADRx), and six general purpose Ready
`inputs (RDY). The data bus width is 8 or 16 bits. Each GPIF
`vector defines the state of the control outputs, and determines
`what state a Ready input (or multiple inputs) must be before
`proceeding. The GPIF vector is programmed to advance a FIFO
`to the next data value, advance an address, and so on. A
`sequence of the GPIF vectors create a single waveform that
`executes to perform the data move between the FX1 and the
`external device.
`
`Six Control OUT Signals
`The 100-pin and 128-pin packages bring out all six Control
`Output pins (CTL0–CTL5). The 8051 programs the GPIF unit to
`define the CTL waveforms. The 56-pin package brings out three
`
`Document Number: 38-08039 Rev. *L
`
`Page 12 of 74
`
`Exhibit 2034 - Page 12 of 74
`
`

`

`of these signals: CTL0–CTL2. CTLx waveform edges are
`programmed to make transitions as fast as once per clock
`(20.8 ns using a 48 MHz clock).
`
`Six Ready IN Signals
`The 100-pin and 128-pin packages bring out all six Ready inputs
`(RDY0–RDY5). The 8051 programs the GPIF unit to test the
`RDY pins for GPIF branching. The 56 pin package brings out two
`of these signals, RDY0–1.
`
`Nine GPIF Address OUT Signals
`Nine GPIF address lines are available in the 100-pin and 128-pin
`packages: GPIFADR[8..0]. The GPIF address lines allow
`indexing through up to a 512 byte block of RAM. If more address
`lines are needed, I/O port pins are used.
`
`Long Transfer Mode
`In Master mode, the 8051 appropriately sets the GPIF
`transaction count registers